Lines Matching +full:5 +full:- +full:6
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
135 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
198 BUS_MSTOP(5, BIT(9))),
207 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
210 BUS_MSTOP(3, BIT(5))),
212 BUS_MSTOP(6, BIT(11))),
214 BUS_MSTOP(6, BIT(12))),
220 BUS_MSTOP(5, BIT(12))),
221 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
222 BUS_MSTOP(5, BIT(12))),
223 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
224 BUS_MSTOP(5, BIT(13))),
225 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
226 BUS_MSTOP(5, BIT(13))),
227 DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
229 DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
231 DEF_MOD("rsci0_ps_ps3_n", CLK_PLLCLN_DIV1024, 5, 15, 2, 31,
233 DEF_MOD("rsci0_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 0, 3, 0,
235 DEF_MOD("rsci0_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 1, 3, 1,
237 DEF_MOD("rsci1_pclk", CLK_PLLCLN_DIV16, 6, 2, 3, 2,
239 DEF_MOD("rsci1_tclk", CLK_PLLCLN_DIV16, 6, 3, 3, 3,
241 DEF_MOD("rsci1_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 4, 3, 4,
243 DEF_MOD("rsci1_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 5, 3, 5,
245 DEF_MOD("rsci1_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 6, 3, 6,
247 DEF_MOD("rsci2_pclk", CLK_PLLCLN_DIV16, 6, 7, 3, 7,
248 BUS_MSTOP(11, BIT(5))),
249 DEF_MOD("rsci2_tclk", CLK_PLLCLN_DIV16, 6, 8, 3, 8,
250 BUS_MSTOP(11, BIT(5))),
251 DEF_MOD("rsci2_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 9, 3, 9,
252 BUS_MSTOP(11, BIT(5))),
253 DEF_MOD("rsci2_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 10, 3, 10,
254 BUS_MSTOP(11, BIT(5))),
255 DEF_MOD("rsci2_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 11, 3, 11,
256 BUS_MSTOP(11, BIT(5))),
257 DEF_MOD("rsci3_pclk", CLK_PLLCLN_DIV16, 6, 12, 3, 12,
258 BUS_MSTOP(11, BIT(6))),
259 DEF_MOD("rsci3_tclk", CLK_PLLCLN_DIV16, 6, 13, 3, 13,
260 BUS_MSTOP(11, BIT(6))),
261 DEF_MOD("rsci3_ps_ps3_n", CLK_PLLCLN_DIV1024, 6, 14, 3, 14,
262 BUS_MSTOP(11, BIT(6))),
263 DEF_MOD("rsci3_ps_ps2_n", CLK_PLLCLN_DIV256, 6, 15, 3, 15,
264 BUS_MSTOP(11, BIT(6))),
266 BUS_MSTOP(11, BIT(6))),
275 DEF_MOD("rsci4_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 5, 3, 21,
277 DEF_MOD("rsci5_pclk", CLK_PLLCLN_DIV16, 7, 6, 3, 22,
307 DEF_MOD("rsci8_pclk", CLK_PLLCLN_DIV16, 8, 5, 4, 5,
309 DEF_MOD("rsci8_tclk", CLK_PLLCLN_DIV16, 8, 6, 4, 6,
339 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
341 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
346 BUS_MSTOP(1, BIT(5))),
348 BUS_MSTOP(1, BIT(6))),
360 BUS_MSTOP(4, BIT(5))),
361 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
362 BUS_MSTOP(4, BIT(5))),
363 DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
364 BUS_MSTOP(4, BIT(5))),
365 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
367 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
369 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
371 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
373 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
375 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
377 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
379 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
381 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
383 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
385 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
387 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
389 DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
391 DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
393 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
395 DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
397 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
399 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
401 DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
403 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
404 BUS_MSTOP(8, BIT(5)), 1),
405 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
406 BUS_MSTOP(8, BIT(5)), 1),
407 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
408 BUS_MSTOP(8, BIT(5)), 1),
409 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
410 BUS_MSTOP(8, BIT(5)), 1),
411 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
412 BUS_MSTOP(8, BIT(5))),
413 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
414 BUS_MSTOP(8, BIT(5))),
415 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
416 BUS_MSTOP(8, BIT(6)), 1),
417 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
418 BUS_MSTOP(8, BIT(6)), 1),
419 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
420 BUS_MSTOP(8, BIT(6)), 1),
421 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
422 BUS_MSTOP(8, BIT(6)), 1),
423 DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
424 BUS_MSTOP(8, BIT(6))),
425 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
426 BUS_MSTOP(8, BIT(6))),
427 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
429 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
431 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
448 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
449 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
450 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
453 DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */
454 DEF_RST(5, 10, 2, 11), /* GPT_0_RST_S_REG */
455 DEF_RST(5, 11, 2, 12), /* GPT_1_RST_P_REG */
456 DEF_RST(5, 12, 2, 13), /* GPT_1_RST_S_REG */
457 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
464 DEF_RST(8, 5, 3, 22), /* RSCI2_PRESETN */
465 DEF_RST(8, 6, 3, 23), /* RSCI2_TRESETN */
479 DEF_RST(9, 4, 4, 5), /* RSCI9_TRESETN */
480 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
481 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
503 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
504 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
505 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
506 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
507 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
508 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
509 DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */
510 DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */
511 DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */