Lines Matching +full:15 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
190 BUS_MSTOP(5, BIT(9))),
211 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
219 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
221 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
222 BUS_MSTOP(10, BIT(15))),
223 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
224 BUS_MSTOP(10, BIT(15))),
225 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
226 BUS_MSTOP(10, BIT(15))),
227 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
229 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
231 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
233 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
235 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
237 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
239 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
241 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
243 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
245 DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28,
247 DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29,
249 DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30,
251 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
269 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
281 DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
287 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
299 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
310 BUS_MSTOP(9, BIT(4))),
312 BUS_MSTOP(9, BIT(4))),
314 BUS_MSTOP(9, BIT(4))),
315 DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
317 DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
319 DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
322 BUS_MSTOP(2, BIT(15))),
333 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
334 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
335 DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */
341 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
342 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
343 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
344 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
345 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
346 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
347 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
348 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
349 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
350 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
351 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
352 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
360 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
368 DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */
369 DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */
370 DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */