Lines Matching +full:11 +full:- +full:7
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
204 BUS_MSTOP(10, BIT(11))),
212 BUS_MSTOP(6, BIT(11))),
228 BUS_MSTOP(11, BIT(3))),
230 BUS_MSTOP(11, BIT(3))),
232 BUS_MSTOP(11, BIT(3))),
234 BUS_MSTOP(11, BIT(3))),
236 BUS_MSTOP(11, BIT(3))),
238 BUS_MSTOP(11, BIT(4))),
240 BUS_MSTOP(11, BIT(4))),
242 BUS_MSTOP(11, BIT(4))),
244 BUS_MSTOP(11, BIT(4))),
246 BUS_MSTOP(11, BIT(4))),
247 DEF_MOD("rsci2_pclk", CLK_PLLCLN_DIV16, 6, 7, 3, 7,
248 BUS_MSTOP(11, BIT(5))),
250 BUS_MSTOP(11, BIT(5))),
252 BUS_MSTOP(11, BIT(5))),
254 BUS_MSTOP(11, BIT(5))),
255 DEF_MOD("rsci2_ps_ps1_n", CLK_PLLCLN_DIV64, 6, 11, 3, 11,
256 BUS_MSTOP(11, BIT(5))),
258 BUS_MSTOP(11, BIT(6))),
260 BUS_MSTOP(11, BIT(6))),
262 BUS_MSTOP(11, BIT(6))),
264 BUS_MSTOP(11, BIT(6))),
265 DEF_MOD("rsci3_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 0, 3, 16,
266 BUS_MSTOP(11, BIT(6))),
267 DEF_MOD("rsci4_pclk", CLK_PLLCLN_DIV16, 7, 1, 3, 17,
268 BUS_MSTOP(11, BIT(7))),
269 DEF_MOD("rsci4_tclk", CLK_PLLCLN_DIV16, 7, 2, 3, 18,
270 BUS_MSTOP(11, BIT(7))),
271 DEF_MOD("rsci4_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 3, 3, 19,
272 BUS_MSTOP(11, BIT(7))),
273 DEF_MOD("rsci4_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 4, 3, 20,
274 BUS_MSTOP(11, BIT(7))),
275 DEF_MOD("rsci4_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 5, 3, 21,
276 BUS_MSTOP(11, BIT(7))),
277 DEF_MOD("rsci5_pclk", CLK_PLLCLN_DIV16, 7, 6, 3, 22,
278 BUS_MSTOP(11, BIT(8))),
279 DEF_MOD("rsci5_tclk", CLK_PLLCLN_DIV16, 7, 7, 3, 23,
280 BUS_MSTOP(11, BIT(8))),
281 DEF_MOD("rsci5_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 8, 3, 24,
282 BUS_MSTOP(11, BIT(8))),
283 DEF_MOD("rsci5_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 9, 3, 25,
284 BUS_MSTOP(11, BIT(8))),
285 DEF_MOD("rsci5_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 10, 3, 26,
286 BUS_MSTOP(11, BIT(8))),
287 DEF_MOD("rsci6_pclk", CLK_PLLCLN_DIV16, 7, 11, 3, 27,
288 BUS_MSTOP(11, BIT(9))),
289 DEF_MOD("rsci6_tclk", CLK_PLLCLN_DIV16, 7, 12, 3, 28,
290 BUS_MSTOP(11, BIT(9))),
291 DEF_MOD("rsci6_ps_ps3_n", CLK_PLLCLN_DIV1024, 7, 13, 3, 29,
292 BUS_MSTOP(11, BIT(9))),
293 DEF_MOD("rsci6_ps_ps2_n", CLK_PLLCLN_DIV256, 7, 14, 3, 30,
294 BUS_MSTOP(11, BIT(9))),
295 DEF_MOD("rsci6_ps_ps1_n", CLK_PLLCLN_DIV64, 7, 15, 3, 31,
296 BUS_MSTOP(11, BIT(9))),
298 BUS_MSTOP(11, BIT(10))),
300 BUS_MSTOP(11, BIT(10))),
302 BUS_MSTOP(11, BIT(10))),
304 BUS_MSTOP(11, BIT(10))),
306 BUS_MSTOP(11, BIT(10))),
308 BUS_MSTOP(11, BIT(11))),
310 BUS_MSTOP(11, BIT(11))),
311 DEF_MOD("rsci8_ps_ps3_n", CLK_PLLCLN_DIV1024, 8, 7, 4, 7,
312 BUS_MSTOP(11, BIT(11))),
314 BUS_MSTOP(11, BIT(11))),
316 BUS_MSTOP(11, BIT(11))),
318 BUS_MSTOP(11, BIT(12))),
319 DEF_MOD("rsci9_tclk", CLK_PLLCLN_DIV16, 8, 11, 4, 11,
320 BUS_MSTOP(11, BIT(12))),
322 BUS_MSTOP(11, BIT(12))),
324 BUS_MSTOP(11, BIT(12))),
326 BUS_MSTOP(11, BIT(12))),
343 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
350 BUS_MSTOP(1, BIT(7))),
351 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
373 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
381 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
390 BUS_MSTOP(7, BIT(12))),
391 DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
392 BUS_MSTOP(7, BIT(14))),
393 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
394 BUS_MSTOP(7, BIT(7))),
395 DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
396 BUS_MSTOP(7, BIT(8))),
397 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
398 BUS_MSTOP(7, BIT(9))),
399 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
400 BUS_MSTOP(7, BIT(10))),
401 DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
402 BUS_MSTOP(7, BIT(11))),
403 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
405 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
407 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
409 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
411 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
413 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
415 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
417 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
433 DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
435 DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
437 DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
450 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
454 DEF_RST(5, 10, 2, 11), /* GPT_0_RST_S_REG */
455 DEF_RST(5, 11, 2, 12), /* GPT_1_RST_P_REG */
457 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
458 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
459 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
466 DEF_RST(8, 7, 3, 24), /* RSCI3_PRESETN */
470 DEF_RST(8, 11, 3, 28), /* RSCI5_PRESETN */
481 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
482 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
485 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
486 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
496 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
504 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
505 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
508 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
512 DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */