Lines Matching +full:10 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
102 {1, 10},
190 BUS_MSTOP(5, BIT(9))),
192 BUS_MSTOP(3, BIT(2))),
194 BUS_MSTOP(3, BIT(3))),
196 BUS_MSTOP(10, BIT(11))),
198 BUS_MSTOP(10, BIT(12))),
202 BUS_MSTOP(3, BIT(5))),
204 BUS_MSTOP(6, BIT(11))),
206 BUS_MSTOP(6, BIT(12))),
208 BUS_MSTOP(1, BIT(0))),
210 BUS_MSTOP(1, BIT(0))),
212 BUS_MSTOP(5, BIT(12))),
214 BUS_MSTOP(5, BIT(12))),
216 BUS_MSTOP(5, BIT(13))),
218 BUS_MSTOP(5, BIT(13))),
220 BUS_MSTOP(3, BIT(14))),
222 BUS_MSTOP(10, BIT(15))),
224 BUS_MSTOP(10, BIT(15))),
226 BUS_MSTOP(10, BIT(15))),
228 BUS_MSTOP(3, BIT(13))),
230 BUS_MSTOP(1, BIT(1))),
232 BUS_MSTOP(1, BIT(2))),
234 BUS_MSTOP(1, BIT(3))),
236 BUS_MSTOP(1, BIT(4))),
238 BUS_MSTOP(1, BIT(5))),
240 BUS_MSTOP(1, BIT(6))),
241 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
242 BUS_MSTOP(1, BIT(7))),
244 BUS_MSTOP(1, BIT(8))),
246 BUS_MSTOP(10, BIT(14))),
248 BUS_MSTOP(10, BIT(14))),
250 BUS_MSTOP(10, BIT(14))),
252 BUS_MSTOP(4, BIT(5))),
253 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
254 BUS_MSTOP(4, BIT(5))),
255 DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
256 BUS_MSTOP(4, BIT(5))),
257 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
258 BUS_MSTOP(8, BIT(2))),
259 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
260 BUS_MSTOP(8, BIT(2))),
261 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
262 BUS_MSTOP(8, BIT(2))),
263 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
264 BUS_MSTOP(8, BIT(2))),
265 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
266 BUS_MSTOP(8, BIT(3))),
267 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
268 BUS_MSTOP(8, BIT(3))),
269 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
270 BUS_MSTOP(8, BIT(3))),
271 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
272 BUS_MSTOP(8, BIT(3))),
273 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
274 BUS_MSTOP(8, BIT(4))),
275 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
276 BUS_MSTOP(8, BIT(4))),
277 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
278 BUS_MSTOP(8, BIT(4))),
279 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
280 BUS_MSTOP(8, BIT(4))),
281 DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
282 BUS_MSTOP(7, BIT(12))),
284 BUS_MSTOP(7, BIT(14))),
286 BUS_MSTOP(8, BIT(5)), 1),
288 BUS_MSTOP(8, BIT(5)), 1),
289 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
290 BUS_MSTOP(8, BIT(5)), 1),
292 BUS_MSTOP(8, BIT(5)), 1),
294 BUS_MSTOP(8, BIT(5))),
296 BUS_MSTOP(8, BIT(5))),
298 BUS_MSTOP(8, BIT(6)), 1),
300 BUS_MSTOP(8, BIT(6)), 1),
302 BUS_MSTOP(8, BIT(6)), 1),
304 BUS_MSTOP(8, BIT(6)), 1),
306 BUS_MSTOP(8, BIT(6))),
308 BUS_MSTOP(8, BIT(6))),
310 BUS_MSTOP(9, BIT(4))),
312 BUS_MSTOP(9, BIT(4))),
314 BUS_MSTOP(9, BIT(4))),
316 BUS_MSTOP(3, BIT(4))),
318 BUS_MSTOP(3, BIT(4))),
320 BUS_MSTOP(3, BIT(4))),
321 DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
322 BUS_MSTOP(2, BIT(15))),
334 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
335 DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */
336 DEF_RST(5, 10, 2, 11), /* GPT_0_RST_S_REG */
346 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
347 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
353 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
354 DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */
355 DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */
356 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
357 DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
358 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
359 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
360 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
361 DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */