Lines Matching +full:1 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
70 {0, 1},
71 {1, 2},
79 {1, 4},
85 {1, 4},
93 {1, 4},
102 {1, 10},
130 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
131 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
132 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
133 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
141 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
142 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
143 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
144 DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
147 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
148 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
149 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
151 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
152 DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
161 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
163 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
169 DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
178 DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
179 DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
181 CLK_PLLETH_DIV_125_FIX, 1, 1),
183 CLK_PLLETH_DIV_125_FIX, 1, 1),
184 DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G047_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
185 DEF_FIXED("usb3_0_core_clk", R9A09G047_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
190 BUS_MSTOP(5, BIT(9))),
191 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
201 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
203 DEF_MOD("gpt_0_pclk_sfr", CLK_PLLCLN_DIV8, 3, 1, 1, 17,
205 DEF_MOD("gpt_1_pclk_sfr", CLK_PLLCLN_DIV8, 3, 2, 1, 18,
208 BUS_MSTOP(1, BIT(0))),
210 BUS_MSTOP(1, BIT(0))),
215 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
221 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
223 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
225 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
227 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
229 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
230 BUS_MSTOP(1, BIT(1))),
231 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
232 BUS_MSTOP(1, BIT(2))),
233 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
234 BUS_MSTOP(1, BIT(3))),
235 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
236 BUS_MSTOP(1, BIT(4))),
237 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
238 BUS_MSTOP(1, BIT(5))),
239 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
240 BUS_MSTOP(1, BIT(6))),
241 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
242 BUS_MSTOP(1, BIT(7))),
243 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
244 BUS_MSTOP(1, BIT(8))),
245 DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28,
247 DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29,
249 DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30,
251 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
255 DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
269 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
286 BUS_MSTOP(8, BIT(5)), 1),
287 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
288 BUS_MSTOP(8, BIT(5)), 1),
290 BUS_MSTOP(8, BIT(5)), 1),
292 BUS_MSTOP(8, BIT(5)), 1),
298 BUS_MSTOP(8, BIT(6)), 1),
300 BUS_MSTOP(8, BIT(6)), 1),
302 BUS_MSTOP(8, BIT(6)), 1),
303 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
304 BUS_MSTOP(8, BIT(6)), 1),
310 BUS_MSTOP(9, BIT(4))),
312 BUS_MSTOP(9, BIT(4))),
314 BUS_MSTOP(9, BIT(4))),
317 DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
326 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
327 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
328 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
329 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
330 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
331 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
332 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
333 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
334 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
335 DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */
341 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
342 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
343 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
344 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
345 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
346 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
347 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
348 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
349 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
350 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
351 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
352 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
354 DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */
360 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
362 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
363 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
370 DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */