Lines Matching +full:1 +full:- +full:5
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
70 {0, 1},
71 {1, 2},
79 {1, 4},
85 {1, 4},
93 {1, 4},
102 {1, 10},
130 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
131 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
132 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
133 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
141 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
142 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
143 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
144 DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
147 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
148 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
149 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
151 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
152 DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
161 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
163 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
169 DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
178 DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
179 DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
181 CLK_PLLETH_DIV_125_FIX, 1, 1),
183 CLK_PLLETH_DIV_125_FIX, 1, 1),
184 DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G047_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
185 DEF_FIXED("usb3_0_core_clk", R9A09G047_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
190 BUS_MSTOP(5, BIT(9))),
191 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
199 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
201 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
202 BUS_MSTOP(3, BIT(5))),
203 DEF_MOD("gpt_0_pclk_sfr", CLK_PLLCLN_DIV8, 3, 1, 1, 17,
205 DEF_MOD("gpt_1_pclk_sfr", CLK_PLLCLN_DIV8, 3, 2, 1, 18,
208 BUS_MSTOP(1, BIT(0))),
210 BUS_MSTOP(1, BIT(0))),
212 BUS_MSTOP(5, BIT(12))),
213 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
214 BUS_MSTOP(5, BIT(12))),
215 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
216 BUS_MSTOP(5, BIT(13))),
217 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
218 BUS_MSTOP(5, BIT(13))),
223 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
230 BUS_MSTOP(1, BIT(1))),
231 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
232 BUS_MSTOP(1, BIT(2))),
234 BUS_MSTOP(1, BIT(3))),
236 BUS_MSTOP(1, BIT(4))),
238 BUS_MSTOP(1, BIT(5))),
240 BUS_MSTOP(1, BIT(6))),
242 BUS_MSTOP(1, BIT(7))),
244 BUS_MSTOP(1, BIT(8))),
252 BUS_MSTOP(4, BIT(5))),
253 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
254 BUS_MSTOP(4, BIT(5))),
255 DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
256 BUS_MSTOP(4, BIT(5))),
257 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
259 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
261 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
263 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
265 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
267 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
269 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
271 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
273 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
275 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
277 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
279 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
281 DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
283 DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
285 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
286 BUS_MSTOP(8, BIT(5)), 1),
287 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
288 BUS_MSTOP(8, BIT(5)), 1),
289 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
290 BUS_MSTOP(8, BIT(5)), 1),
291 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
292 BUS_MSTOP(8, BIT(5)), 1),
293 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
294 BUS_MSTOP(8, BIT(5))),
295 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
296 BUS_MSTOP(8, BIT(5))),
297 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
298 BUS_MSTOP(8, BIT(6)), 1),
299 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
300 BUS_MSTOP(8, BIT(6)), 1),
302 BUS_MSTOP(8, BIT(6)), 1),
303 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
304 BUS_MSTOP(8, BIT(6)), 1),
317 DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
326 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
327 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
328 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
329 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
330 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
331 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
332 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
333 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
334 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
335 DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */
336 DEF_RST(5, 10, 2, 11), /* GPT_0_RST_S_REG */
337 DEF_RST(5, 11, 2, 12), /* GPT_1_RST_P_REG */
338 DEF_RST(5, 12, 2, 13), /* GPT_1_RST_S_REG */
342 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
354 DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */
362 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
363 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
364 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
365 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
366 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */