Lines Matching +full:- +full:5
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
132 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
190 BUS_MSTOP(5, BIT(9))),
199 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
202 BUS_MSTOP(3, BIT(5))),
212 BUS_MSTOP(5, BIT(12))),
213 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
214 BUS_MSTOP(5, BIT(12))),
215 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
216 BUS_MSTOP(5, BIT(13))),
217 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
218 BUS_MSTOP(5, BIT(13))),
231 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
238 BUS_MSTOP(1, BIT(5))),
252 BUS_MSTOP(4, BIT(5))),
253 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
254 BUS_MSTOP(4, BIT(5))),
255 DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
256 BUS_MSTOP(4, BIT(5))),
257 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
259 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
261 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
263 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
265 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
267 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
269 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
271 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
273 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
275 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
277 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
279 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
281 DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
283 DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
285 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
286 BUS_MSTOP(8, BIT(5)), 1),
287 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
288 BUS_MSTOP(8, BIT(5)), 1),
289 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
290 BUS_MSTOP(8, BIT(5)), 1),
291 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
292 BUS_MSTOP(8, BIT(5)), 1),
293 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
294 BUS_MSTOP(8, BIT(5))),
295 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
296 BUS_MSTOP(8, BIT(5))),
297 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
299 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
330 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
331 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
335 DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */
336 DEF_RST(5, 10, 2, 11), /* GPT_0_RST_S_REG */
337 DEF_RST(5, 11, 2, 12), /* GPT_1_RST_P_REG */
338 DEF_RST(5, 12, 2, 13), /* GPT_1_RST_S_REG */
342 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
362 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
363 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
364 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
365 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
366 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */