Lines Matching +full:0 +full:x160
101 DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074),
102 DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078),
103 DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268),
104 DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c),
105 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074),
106 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078),
107 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),
108 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),
118 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
119 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
120 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
121 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
130 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
291 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
292 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
293 * 0 0 1 0 Prohibited setting
294 * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
295 * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
296 * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
297 * 0 1 1 0 Prohibited setting
298 * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
299 * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
300 * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
301 * 1 0 1 0 Prohibited setting
302 * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
303 * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
304 * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
305 * 1 1 1 0 Prohibited setting
317 { 0, /* Prohibited setting */ },
321 { 0, /* Prohibited setting */ },
325 { 0, /* Prohibited setting */ },
329 { 0, /* Prohibited setting */ },
345 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); in r8a77965_cpg_mssr_init()