Lines Matching +full:0 +full:x32000
64 .offset = 0x0,
67 .enable_reg = 0x52020,
68 .enable_mask = BIT(0),
81 .offset = 0x0,
84 .enable_reg = 0x57020,
85 .enable_mask = BIT(0),
98 { 0x1, 2 },
103 .offset = 0x0,
120 .offset = 0x0,
137 .offset = 0x4000,
140 .enable_reg = 0x52020,
154 .offset = 0x1000,
157 .enable_reg = 0x57020,
171 .offset = 0x3000,
174 .enable_reg = 0x52020,
188 .offset = 0x3000,
191 .enable_reg = 0x57020,
205 .offset = 0x4000,
208 .enable_reg = 0x52020,
222 .offset = 0x4000,
225 .enable_reg = 0x57020,
239 .offset = 0x6000,
242 .enable_reg = 0x52020,
256 .offset = 0x6000,
259 .enable_reg = 0x57020,
273 .offset = 0x7000,
276 .enable_reg = 0x52020,
290 .offset = 0x9000,
293 .enable_reg = 0x52020,
307 { P_BI_TCXO, 0 },
319 { P_BI_TCXO, 0 },
333 { P_BI_TCXO, 0 },
349 { P_BI_TCXO, 0 },
363 { P_BI_TCXO, 0 },
373 { P_BI_TCXO, 0 },
381 { P_PCIE_1_PHY_AUX_CLK, 0 },
391 { P_BI_TCXO, 0 },
405 { P_BI_TCXO, 0 },
421 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
431 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
441 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
451 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
461 .reg = 0x6b070,
475 .reg = 0x8d094,
476 .shift = 0,
490 .reg = 0x8d078,
504 .reg = 0x77064,
505 .shift = 0,
519 .reg = 0x770e0,
520 .shift = 0,
534 .reg = 0x77054,
535 .shift = 0,
549 .reg = 0x3906c,
550 .shift = 0,
564 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
565 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
566 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
571 .cmd_rcgr = 0x64004,
586 .cmd_rcgr = 0x65004,
601 .cmd_rcgr = 0x66004,
616 F(19200000, P_BI_TCXO, 1, 0, 0),
621 .cmd_rcgr = 0x6b074,
636 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
641 .cmd_rcgr = 0x6b058,
642 .mnd_width = 0,
656 .cmd_rcgr = 0x8d07c,
671 .cmd_rcgr = 0x8d060,
672 .mnd_width = 0,
686 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
691 .cmd_rcgr = 0x33010,
692 .mnd_width = 0,
706 .cmd_rcgr = 0x17008,
707 .mnd_width = 0,
721 .cmd_rcgr = 0x17024,
722 .mnd_width = 0,
736 .cmd_rcgr = 0x17040,
737 .mnd_width = 0,
751 .cmd_rcgr = 0x1705c,
752 .mnd_width = 0,
766 .cmd_rcgr = 0x17078,
767 .mnd_width = 0,
781 .cmd_rcgr = 0x17094,
782 .mnd_width = 0,
796 .cmd_rcgr = 0x170b0,
797 .mnd_width = 0,
811 .cmd_rcgr = 0x170cc,
812 .mnd_width = 0,
826 .cmd_rcgr = 0x170e8,
827 .mnd_width = 0,
841 .cmd_rcgr = 0x17104,
842 .mnd_width = 0,
856 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
857 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
870 .cmd_rcgr = 0x188a0,
881 F(19200000, P_BI_TCXO, 1, 0, 0),
886 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
889 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
893 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
906 .cmd_rcgr = 0x18010,
923 .cmd_rcgr = 0x18148,
934 F(19200000, P_BI_TCXO, 1, 0, 0),
939 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
942 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
955 .cmd_rcgr = 0x18290,
966 F(19200000, P_BI_TCXO, 1, 0, 0),
971 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
974 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
987 .cmd_rcgr = 0x183c8,
1004 .cmd_rcgr = 0x18500,
1021 .cmd_rcgr = 0x18638,
1038 .cmd_rcgr = 0x18770,
1047 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
1052 .cmd_rcgr = 0x1e9d4,
1053 .mnd_width = 0,
1075 .cmd_rcgr = 0x1e010,
1092 .cmd_rcgr = 0x1e148,
1109 .cmd_rcgr = 0x1e280,
1126 .cmd_rcgr = 0x1e3b8,
1143 .cmd_rcgr = 0x1e4f0,
1160 .cmd_rcgr = 0x1e628,
1171 F(19200000, P_BI_TCXO, 1, 0, 0),
1176 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1179 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1193 .cmd_rcgr = 0x1e760,
1210 .cmd_rcgr = 0x1e898,
1219 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1220 F(400000000, P_GCC_GPLL0_OUT_MAIN, 1.5, 0, 0),
1233 .cmd_rcgr = 0x19018,
1243 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1244 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1245 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1250 .cmd_rcgr = 0x14018,
1266 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1267 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1272 .cmd_rcgr = 0x16018,
1287 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1288 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1289 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1290 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1295 .cmd_rcgr = 0x77030,
1310 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1311 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1312 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1317 .cmd_rcgr = 0x77080,
1318 .mnd_width = 0,
1332 F(9600000, P_BI_TCXO, 2, 0, 0),
1333 F(19200000, P_BI_TCXO, 1, 0, 0),
1338 .cmd_rcgr = 0x770b4,
1339 .mnd_width = 0,
1353 .cmd_rcgr = 0x77098,
1354 .mnd_width = 0,
1368 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1369 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1370 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1371 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1376 .cmd_rcgr = 0x3902c,
1391 .cmd_rcgr = 0x39044,
1392 .mnd_width = 0,
1406 .cmd_rcgr = 0x39070,
1407 .mnd_width = 0,
1421 .reg = 0x18280,
1422 .shift = 0,
1436 .reg = 0x19010,
1437 .shift = 0,
1451 .reg = 0x3905c,
1452 .shift = 0,
1466 .halt_reg = 0x10064,
1468 .hwcg_reg = 0x10064,
1471 .enable_reg = 0x52000,
1481 .halt_reg = 0x770e4,
1483 .hwcg_reg = 0x770e4,
1486 .enable_reg = 0x770e4,
1487 .enable_mask = BIT(0),
1501 .halt_reg = 0x770e4,
1503 .hwcg_reg = 0x770e4,
1506 .enable_reg = 0x770e4,
1521 .halt_reg = 0x3908c,
1523 .hwcg_reg = 0x3908c,
1526 .enable_reg = 0x3908c,
1527 .enable_mask = BIT(0),
1541 .halt_reg = 0x38004,
1543 .hwcg_reg = 0x38004,
1546 .enable_reg = 0x52000,
1556 .halt_reg = 0x26010,
1558 .hwcg_reg = 0x26010,
1561 .enable_reg = 0x26010,
1562 .enable_mask = BIT(0),
1571 .halt_reg = 0x2601c,
1573 .hwcg_reg = 0x2601c,
1576 .enable_reg = 0x2601c,
1577 .enable_mask = BIT(0),
1586 .halt_reg = 0x10050,
1588 .hwcg_reg = 0x10050,
1591 .enable_reg = 0x52000,
1601 .halt_reg = 0x39088,
1603 .hwcg_reg = 0x39088,
1606 .enable_reg = 0x39088,
1607 .enable_mask = BIT(0),
1621 .halt_reg = 0x10058,
1623 .hwcg_reg = 0x10058,
1626 .enable_reg = 0x52008,
1636 .halt_reg = 0x71154,
1638 .hwcg_reg = 0x71154,
1641 .enable_reg = 0x71154,
1642 .enable_mask = BIT(0),
1651 .halt_reg = 0x10074,
1653 .hwcg_reg = 0x10074,
1656 .enable_reg = 0x52000,
1666 .halt_reg = 0x2700c,
1668 .hwcg_reg = 0x2700c,
1671 .enable_reg = 0x2700c,
1672 .enable_mask = BIT(0),
1681 .halt_reg = 0x64000,
1684 .enable_reg = 0x64000,
1685 .enable_mask = BIT(0),
1699 .halt_reg = 0x65000,
1702 .enable_reg = 0x65000,
1703 .enable_mask = BIT(0),
1717 .halt_reg = 0x66000,
1720 .enable_reg = 0x66000,
1721 .enable_mask = BIT(0),
1737 .enable_reg = 0x52000,
1754 .enable_reg = 0x52000,
1769 .halt_reg = 0x71010,
1771 .hwcg_reg = 0x71010,
1774 .enable_reg = 0x71010,
1775 .enable_mask = BIT(0),
1784 .halt_reg = 0x71018,
1787 .enable_reg = 0x71018,
1788 .enable_mask = BIT(0),
1797 .halt_reg = 0x6b03c,
1800 .enable_reg = 0x52008,
1815 .halt_reg = 0x6b038,
1817 .hwcg_reg = 0x6b038,
1820 .enable_reg = 0x52008,
1830 .halt_reg = 0x6b02c,
1832 .hwcg_reg = 0x6b02c,
1835 .enable_reg = 0x52008,
1845 .halt_reg = 0x6b054,
1848 .enable_reg = 0x52000,
1863 .halt_reg = 0x6b048,
1866 .enable_reg = 0x52008,
1881 .halt_reg = 0x6b020,
1883 .hwcg_reg = 0x6b020,
1886 .enable_reg = 0x52008,
1887 .enable_mask = BIT(0),
1896 .halt_reg = 0x6b01c,
1899 .enable_reg = 0x52008,
1909 .halt_reg = 0x8d038,
1912 .enable_reg = 0x52000,
1927 .halt_reg = 0x8d034,
1929 .hwcg_reg = 0x8d034,
1932 .enable_reg = 0x52000,
1942 .halt_reg = 0x8d028,
1944 .hwcg_reg = 0x8d028,
1947 .enable_reg = 0x52000,
1957 .halt_reg = 0x8d044,
1960 .enable_reg = 0x52000,
1975 .halt_reg = 0x8d05c,
1978 .enable_reg = 0x52000,
1993 .halt_reg = 0x8d050,
1996 .enable_reg = 0x52000,
2011 .halt_reg = 0x8d01c,
2013 .hwcg_reg = 0x8d01c,
2016 .enable_reg = 0x52000,
2026 .halt_reg = 0x8d018,
2029 .enable_reg = 0x52000,
2039 .halt_reg = 0x3300c,
2042 .enable_reg = 0x3300c,
2043 .enable_mask = BIT(0),
2057 .halt_reg = 0x33004,
2059 .hwcg_reg = 0x33004,
2062 .enable_reg = 0x33004,
2063 .enable_mask = BIT(0),
2072 .halt_reg = 0x33008,
2075 .enable_reg = 0x33008,
2076 .enable_mask = BIT(0),
2085 .halt_reg = 0x26008,
2087 .hwcg_reg = 0x26008,
2090 .enable_reg = 0x26008,
2091 .enable_mask = BIT(0),
2100 .halt_reg = 0x2600c,
2102 .hwcg_reg = 0x2600c,
2105 .enable_reg = 0x2600c,
2106 .enable_mask = BIT(0),
2115 .halt_reg = 0x27008,
2117 .hwcg_reg = 0x27008,
2120 .enable_reg = 0x27008,
2121 .enable_mask = BIT(0),
2130 .halt_reg = 0x71008,
2132 .hwcg_reg = 0x71008,
2135 .enable_reg = 0x71008,
2136 .enable_mask = BIT(0),
2145 .halt_reg = 0x6b018,
2147 .hwcg_reg = 0x6b018,
2150 .enable_reg = 0x52000,
2160 .halt_reg = 0x32014,
2162 .hwcg_reg = 0x32014,
2165 .enable_reg = 0x32014,
2166 .enable_mask = BIT(0),
2175 .halt_reg = 0x32008,
2177 .hwcg_reg = 0x32008,
2180 .enable_reg = 0x32008,
2181 .enable_mask = BIT(0),
2190 .halt_reg = 0x32010,
2192 .hwcg_reg = 0x32010,
2195 .enable_reg = 0x32010,
2196 .enable_mask = BIT(0),
2205 .halt_reg = 0x3200c,
2207 .hwcg_reg = 0x3200c,
2210 .enable_reg = 0x3200c,
2211 .enable_mask = BIT(0),
2220 .halt_reg = 0x23004,
2223 .enable_reg = 0x52008,
2233 .halt_reg = 0x17004,
2236 .enable_reg = 0x52008,
2251 .halt_reg = 0x17020,
2254 .enable_reg = 0x52008,
2269 .halt_reg = 0x1703c,
2272 .enable_reg = 0x52008,
2287 .halt_reg = 0x17058,
2290 .enable_reg = 0x52008,
2305 .halt_reg = 0x17074,
2308 .enable_reg = 0x52008,
2323 .halt_reg = 0x17090,
2326 .enable_reg = 0x52008,
2341 .halt_reg = 0x170ac,
2344 .enable_reg = 0x52008,
2359 .halt_reg = 0x170c8,
2362 .enable_reg = 0x52008,
2377 .halt_reg = 0x170e4,
2380 .enable_reg = 0x52010,
2395 .halt_reg = 0x17100,
2398 .enable_reg = 0x52010,
2413 .halt_reg = 0x23000,
2415 .hwcg_reg = 0x23000,
2418 .enable_reg = 0x52008,
2428 .halt_reg = 0x23154,
2431 .enable_reg = 0x52008,
2441 .halt_reg = 0x23144,
2444 .enable_reg = 0x52008,
2454 .halt_reg = 0x1889c,
2457 .enable_reg = 0x52010,
2472 .halt_reg = 0x18004,
2475 .enable_reg = 0x52008,
2490 .halt_reg = 0x1813c,
2493 .enable_reg = 0x52008,
2508 .halt_reg = 0x18274,
2511 .enable_reg = 0x52008,
2526 .halt_reg = 0x18284,
2529 .enable_reg = 0x52008,
2544 .halt_reg = 0x183bc,
2547 .enable_reg = 0x52008,
2562 .halt_reg = 0x184f4,
2565 .enable_reg = 0x52008,
2580 .halt_reg = 0x1862c,
2583 .enable_reg = 0x52008,
2598 .halt_reg = 0x18764,
2601 .enable_reg = 0x52010,
2616 .halt_reg = 0x232a4,
2619 .enable_reg = 0x52010,
2629 .halt_reg = 0x23294,
2632 .enable_reg = 0x52010,
2633 .enable_mask = BIT(0),
2642 .halt_reg = 0x1e9cc,
2644 .hwcg_reg = 0x1e9cc,
2647 .enable_reg = 0x52010,
2662 .halt_reg = 0x1e9d0,
2664 .hwcg_reg = 0x1e9d0,
2667 .enable_reg = 0x52010,
2682 .halt_reg = 0x1e004,
2685 .enable_reg = 0x52010,
2700 .halt_reg = 0x1e13c,
2703 .enable_reg = 0x52010,
2718 .halt_reg = 0x1e274,
2721 .enable_reg = 0x52010,
2736 .halt_reg = 0x1e3ac,
2739 .enable_reg = 0x52010,
2754 .halt_reg = 0x1e4e4,
2757 .enable_reg = 0x52010,
2772 .halt_reg = 0x1e61c,
2775 .enable_reg = 0x52010,
2790 .halt_reg = 0x1e754,
2793 .enable_reg = 0x52010,
2808 .halt_reg = 0x1e88c,
2811 .enable_reg = 0x52010,
2826 .halt_reg = 0x233f4,
2829 .enable_reg = 0x52018,
2839 .halt_reg = 0x233e4,
2842 .enable_reg = 0x52018,
2843 .enable_mask = BIT(0),
2852 .halt_reg = 0x19014,
2855 .enable_reg = 0x52018,
2870 .halt_reg = 0x19004,
2873 .enable_reg = 0x52018,
2888 .halt_reg = 0x2313c,
2890 .hwcg_reg = 0x2313c,
2893 .enable_reg = 0x52008,
2903 .halt_reg = 0x23140,
2905 .hwcg_reg = 0x23140,
2908 .enable_reg = 0x52008,
2918 .halt_reg = 0x1e9c4,
2920 .hwcg_reg = 0x1e9c4,
2923 .enable_reg = 0x52010,
2933 .halt_reg = 0x1e9c8,
2935 .hwcg_reg = 0x1e9c8,
2938 .enable_reg = 0x52010,
2948 .halt_reg = 0x2328c,
2950 .hwcg_reg = 0x2328c,
2953 .enable_reg = 0x52010,
2963 .halt_reg = 0x23290,
2965 .hwcg_reg = 0x23290,
2968 .enable_reg = 0x52010,
2978 .halt_reg = 0x233dc,
2980 .hwcg_reg = 0x233dc,
2983 .enable_reg = 0x52010,
2993 .halt_reg = 0x233e0,
2995 .hwcg_reg = 0x233e0,
2998 .enable_reg = 0x52010,
3008 .halt_reg = 0x14010,
3011 .enable_reg = 0x14010,
3012 .enable_mask = BIT(0),
3021 .halt_reg = 0x14004,
3024 .enable_reg = 0x14004,
3025 .enable_mask = BIT(0),
3039 .halt_reg = 0x16010,
3042 .enable_reg = 0x16010,
3043 .enable_mask = BIT(0),
3052 .halt_reg = 0x16004,
3055 .enable_reg = 0x16004,
3056 .enable_mask = BIT(0),
3070 .halt_reg = 0x77024,
3072 .hwcg_reg = 0x77024,
3075 .enable_reg = 0x77024,
3076 .enable_mask = BIT(0),
3085 .halt_reg = 0x77018,
3087 .hwcg_reg = 0x77018,
3090 .enable_reg = 0x77018,
3091 .enable_mask = BIT(0),
3105 .halt_reg = 0x77018,
3107 .hwcg_reg = 0x77018,
3110 .enable_reg = 0x77018,
3125 .halt_reg = 0x77074,
3127 .hwcg_reg = 0x77074,
3130 .enable_reg = 0x77074,
3131 .enable_mask = BIT(0),
3145 .halt_reg = 0x77074,
3147 .hwcg_reg = 0x77074,
3150 .enable_reg = 0x77074,
3165 .halt_reg = 0x770b0,
3167 .hwcg_reg = 0x770b0,
3170 .enable_reg = 0x770b0,
3171 .enable_mask = BIT(0),
3185 .halt_reg = 0x770b0,
3187 .hwcg_reg = 0x770b0,
3190 .enable_reg = 0x770b0,
3205 .halt_reg = 0x7702c,
3208 .enable_reg = 0x7702c,
3209 .enable_mask = BIT(0),
3223 .halt_reg = 0x770cc,
3226 .enable_reg = 0x770cc,
3227 .enable_mask = BIT(0),
3241 .halt_reg = 0x77028,
3244 .enable_reg = 0x77028,
3245 .enable_mask = BIT(0),
3259 .halt_reg = 0x77068,
3261 .hwcg_reg = 0x77068,
3264 .enable_reg = 0x77068,
3265 .enable_mask = BIT(0),
3279 .halt_reg = 0x77068,
3281 .hwcg_reg = 0x77068,
3284 .enable_reg = 0x77068,
3299 .halt_reg = 0x39018,
3302 .enable_reg = 0x39018,
3303 .enable_mask = BIT(0),
3317 .halt_reg = 0x39028,
3320 .enable_reg = 0x39028,
3321 .enable_mask = BIT(0),
3335 .halt_reg = 0x39024,
3338 .enable_reg = 0x39024,
3339 .enable_mask = BIT(0),
3348 .halt_reg = 0x39060,
3351 .enable_reg = 0x39060,
3352 .enable_mask = BIT(0),
3366 .halt_reg = 0x39064,
3369 .enable_reg = 0x39064,
3370 .enable_mask = BIT(0),
3384 .halt_reg = 0x39068,
3386 .hwcg_reg = 0x39068,
3389 .enable_reg = 0x39068,
3390 .enable_mask = BIT(0),
3404 .halt_reg = 0x32018,
3406 .hwcg_reg = 0x32018,
3409 .enable_reg = 0x32018,
3410 .enable_mask = BIT(0),
3419 .halt_reg = 0x32024,
3421 .hwcg_reg = 0x32024,
3424 .enable_reg = 0x32024,
3425 .enable_mask = BIT(0),
3434 .gdscr = 0x6b004,
3435 .collapse_ctrl = 0x5214c,
3436 .collapse_mask = BIT(0),
3445 .gdscr = 0x6c000,
3446 .collapse_ctrl = 0x5214c,
3456 .gdscr = 0x8d004,
3457 .collapse_ctrl = 0x5214c,
3467 .gdscr = 0x8e000,
3468 .collapse_ctrl = 0x5214c,
3478 .gdscr = 0x77004,
3487 .gdscr = 0x9e000,
3496 .gdscr = 0x39004,
3505 .gdscr = 0x50018,
3704 [GCC_CAMERA_BCR] = { 0x26000 },
3705 [GCC_DISPLAY_BCR] = { 0x27000 },
3706 [GCC_GPU_BCR] = { 0x71000 },
3707 [GCC_PCIE_0_BCR] = { 0x6b000 },
3708 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3709 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3710 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3711 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3712 [GCC_PCIE_1_BCR] = { 0x8d000 },
3713 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3714 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3715 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3716 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
3717 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3718 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3719 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3720 [GCC_PDM_BCR] = { 0x33000 },
3721 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3722 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3723 [GCC_QUPV3_WRAPPER_3_BCR] = { 0x19000 },
3724 [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 },
3725 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3726 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3727 [GCC_SDCC2_BCR] = { 0x14000 },
3728 [GCC_SDCC4_BCR] = { 0x16000 },
3729 [GCC_UFS_PHY_BCR] = { 0x77000 },
3730 [GCC_USB30_PRIM_BCR] = { 0x39000 },
3731 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3732 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3733 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3734 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3735 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3736 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3737 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
3738 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
3739 [GCC_VIDEO_BCR] = { 0x32000 },
3777 .max_register = 0x1f41f0,
3812 qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ in gcc_sm8650_probe()
3813 qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ in gcc_sm8650_probe()
3814 qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ in gcc_sm8650_probe()
3815 qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ in gcc_sm8650_probe()
3816 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_sm8650_probe()
3817 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ in gcc_sm8650_probe()
3818 qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ in gcc_sm8650_probe()
3823 regmap_write(regmap, 0x52150, 0x0); in gcc_sm8650_probe()