Lines Matching +full:x1e80100 +full:- +full:gcc

1 # SPDX-License-Identifier: GPL-2.0-only
50 	tristate "X1E80100 Camera Clock Controller"
54 	  Support for the camera clock controller on X1E80100 devices.
58 	tristate "X1E80100 Display Clock Controller"
63 	  Technologies, Inc. X1E80100 devices.
68 	tristate "X1E80100 Global Clock Controller"
73 	  X1E80100 devices.
78 	tristate "X1E80100 Graphics Clock Controller"
82 	  Support for the graphics clock controller on X1E80100 devices.
87 	tristate "X1E80100 TCSR Clock Controller"
91 	  Support for the TCSR clock controller on X1E80100 devices.
242 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
243 	  the output clocks to the networking hardware and GCC blocks.
326 	  NSSCC receives the clock sources from GCC, CMN PLL and UNIPHY (PCS).
1425 	  Say Y if you want to toggle LPASS-adjacent resets within
1530 	  SM8550 or SM8650 or X1E80100 devices.
1555 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1557 	  Support for the high-frequency PLLs present on Qualcomm devices.
1564 	  Support for the Krait ACC and GCC clock controllers. Say Y