Lines Matching +full:sm8650 +full:- +full:gcc

1 # SPDX-License-Identifier: GPL-2.0-only
206 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 	  the output clocks to the networking hardware and GCC blocks.
955 	tristate "SM8650 Camera Clock Controller"
959 	  Support for the camera clock controller on SM8650 devices.
1048 	  SAR2130P, SM8550 or SM8650 devices.
1164 	tristate "SM8650 Global Clock Controller"
1168 	  Support for the global clock controller on SM8650 devices.
1273 	tristate "SM8650 Graphics Clock Controller"
1277 	  Support for the graphics clock controller on SM8650 devices.
1287 	  Say Y if you want to toggle LPASS-adjacent resets within
1299 	tristate "SM8650 TCSR Clock Controller"
1303 	  Support for the TCSR clock controller on SM8650 devices.
1372 	  SM8550 or SM8650 devices.
1386 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1388 	  Support for the high-frequency PLLs present on Qualcomm devices.
1395 	  Support for the Krait ACC and GCC clock controllers. Say Y