Lines Matching +full:interrupt +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
26 #clock-cells = <0>;
30 compatible = "simple-bus";
31 #address-cells = <2>;
32 #size-cells = <2>;
36 compatible = "sophgo,sg2044-pcie";
41 reg-names = "dbi", "atu", "config", "app";
42 #address-cells = <3>;
43 #size-cells = <2>;
44 #interrupt-cells = <1>;
46 clock-names = "core";
48 interrupt-map-mask = <0 0 0 7>;
49 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
53 msi-parent = <&msi>;
61 pcie_intc0: interrupt-controller {
62 #address-cells = <0>;
63 #interrupt-cells = <1>;
64 interrupt-parent = <&intc>;
66 interrupt-controller;
71 compatible = "sophgo,sg2044-pcie";
76 reg-names = "dbi", "atu", "config", "app";
77 #address-cells = <3>;
78 #size-cells = <2>;
79 #interrupt-cells = <1>;
81 clock-names = "core";
83 interrupt-map-mask = <0 0 0 7>;
84 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
88 msi-parent = <&msi>;
96 pcie_intc1: interrupt-controller {
97 #address-cells = <0>;
98 #interrupt-cells = <1>;
99 interrupt-parent = <&intc>;
101 interrupt-controller;
106 compatible = "sophgo,sg2044-pcie";
111 reg-names = "dbi", "atu", "config", "app";
112 #address-cells = <3>;
113 #size-cells = <2>;
114 #interrupt-cells = <1>;
116 clock-names = "core";
118 interrupt-map-mask = <0 0 0 7>;
119 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
123 msi-parent = <&msi>;
131 pcie_intc2: interrupt-controller {
132 #address-cells = <0>;
133 #interrupt-cells = <1>;
134 interrupt-parent = <&intc>;
136 interrupt-controller;
141 compatible = "sophgo,sg2044-pcie";
146 reg-names = "dbi", "atu", "config", "app";
147 #address-cells = <3>;
148 #size-cells = <2>;
149 #interrupt-cells = <1>;
151 clock-names = "core";
153 interrupt-map-mask = <0 0 0 7>;
154 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
158 msi-parent = <&msi>;
166 pcie_intc3: interrupt-controller {
167 #address-cells = <0>;
168 #interrupt-cells = <1>;
169 interrupt-parent = <&intc>;
171 interrupt-controller;
176 compatible = "sophgo,sg2044-pcie";
181 reg-names = "dbi", "atu", "config", "app";
182 #address-cells = <3>;
183 #size-cells = <2>;
184 #interrupt-cells = <1>;
186 clock-names = "core";
188 interrupt-map-mask = <0 0 0 7>;
189 interrupt-map = <0 0 0 1 &pcie_intc4 0>,
193 msi-parent = <&msi>;
201 pcie_intc4: interrupt-controller {
202 #address-cells = <0>;
203 #interrupt-cells = <1>;
204 interrupt-parent = <&intc>;
206 interrupt-controller;
210 msi: msi-controller@6d50000000 {
211 compatible = "sophgo,sg2044-msi";
214 reg-names = "clr", "doorbell";
215 #msi-cells = <0>;
216 msi-controller;
217 msi-ranges = <&intc 352 IRQ_TYPE_LEVEL_HIGH 512>;
222 compatible = "sophgo,sg2044-spifmc-nor";
224 #address-cells = <1>;
225 #size-cells = <0>;
227 interrupt-parent = <&intc>;
234 compatible = "sophgo,sg2044-spifmc-nor";
236 #address-cells = <1>;
237 #size-cells = <0>;
239 interrupt-parent = <&intc>;
245 dmac0: dma-controller@7020000000 {
246 compatible = "snps,axi-dma-1.01a";
248 #dma-cells = <1>;
249 clock-names = "core-clk", "cfgr-clk";
252 dma-noncoherent;
253 interrupt-parent = <&intc>;
255 dma-channels = <8>;
257 snps,block-size = <4096 4096 4096 4096
259 snps,dma-masters = <2>;
260 snps,data-width = <2>;
261 snps,axi-max-burst-len = <4>;
266 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
268 clock-frequency = <500000000>;
271 clock-names = "baudclk", "apb_pclk";
272 interrupt-parent = <&intc>;
274 reg-shift = <2>;
275 reg-io-width = <4>;
281 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
283 clock-frequency = <500000000>;
286 clock-names = "baudclk", "apb_pclk";
287 interrupt-parent = <&intc>;
289 reg-shift = <2>;
290 reg-io-width = <4>;
296 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
298 clock-frequency = <500000000>;
301 clock-names = "baudclk", "apb_pclk";
302 interrupt-parent = <&intc>;
304 reg-shift = <2>;
305 reg-io-width = <4>;
311 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
313 clock-frequency = <500000000>;
316 clock-names = "baudclk", "apb_pclk";
317 interrupt-parent = <&intc>;
319 reg-shift = <2>;
320 reg-io-width = <4>;
326 compatible = "sophgo,sg2044-dwmac", "snps,dwmac-5.30a";
331 clock-names = "stmmaceth", "ptp_ref", "tx";
332 dma-noncoherent;
333 interrupt-parent = <&intc>;
335 interrupt-names = "macirq";
337 reset-names = "stmmaceth";
338 snps,multicast-filter-bins = <0>;
339 snps,perfect-filter-entries = <1>;
344 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
345 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
346 snps,axi-config = <&gmac0_stmmac_axi_setup>;
350 compatible = "snps,dwmac-mdio";
351 #address-cells = <1>;
352 #size-cells = <0>;
355 gmac0_mtl_rx_setup: rx-queues-config {
356 snps,rx-queues-to-use = <8>;
357 snps,rx-sched-wsp;
368 gmac0_mtl_tx_setup: tx-queues-config {
369 snps,tx-queues-to-use = <8>;
380 gmac0_stmmac_axi_setup: stmmac-axi-config {
388 compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
393 clock-names = "core", "bus", "timer";
394 interrupt-parent = <&intc>;
400 compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
405 clock-names = "core", "bus", "timer";
406 interrupt-parent = <&intc>;
412 compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
414 #address-cells = <1>;
415 #size-cells = <0>;
416 clock-frequency = <100000>;
418 clock-names = "ref";
419 interrupt-parent = <&intc>;
426 compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
428 #address-cells = <1>;
429 #size-cells = <0>;
430 clock-frequency = <100000>;
432 clock-names = "ref";
433 interrupt-parent = <&intc>;
440 compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
442 #address-cells = <1>;
443 #size-cells = <0>;
444 clock-frequency = <100000>;
446 clock-names = "ref";
447 interrupt-parent = <&intc>;
454 compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
456 #address-cells = <1>;
457 #size-cells = <0>;
458 clock-frequency = <100000>;
460 clock-names = "ref";
461 interrupt-parent = <&intc>;
468 compatible = "snps,dw-apb-gpio";
470 #address-cells = <1>;
471 #size-cells = <0>;
474 clock-names = "bus", "db";
477 porta: gpio-controller@0 {
478 compatible = "snps,dw-apb-gpio-port";
480 gpio-controller;
481 #gpio-cells = <2>;
483 interrupt-controller;
484 #interrupt-cells = <2>;
485 interrupt-parent = <&intc>;
491 compatible = "snps,dw-apb-gpio";
493 #address-cells = <1>;
494 #size-cells = <0>;
497 clock-names = "bus", "db";
500 portb: gpio-controller@0 {
501 compatible = "snps,dw-apb-gpio-port";
503 gpio-controller;
504 #gpio-cells = <2>;
506 interrupt-controller;
507 #interrupt-cells = <2>;
508 interrupt-parent = <&intc>;
514 compatible = "snps,dw-apb-gpio";
516 #address-cells = <1>;
517 #size-cells = <0>;
520 clock-names = "bus", "db";
523 portc: gpio-controller@0 {
524 compatible = "snps,dw-apb-gpio-port";
526 gpio-controller;
527 #gpio-cells = <2>;
529 interrupt-controller;
530 #interrupt-cells = <2>;
531 interrupt-parent = <&intc>;
537 compatible = "sophgo,sg2044-pwm";
539 #pwm-cells = <3>;
541 clock-names = "apb";
547 compatible = "sophgo,sg2044-top-syscon", "syscon";
549 #clock-cells = <1>;
554 compatible = "sophgo,sg2044-pinctrl";
558 clk: clock-controller@7050002000 {
559 compatible = "sophgo,sg2044-clk";
561 #clock-cells = <1>;
571 clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
578 rst: reset-controller@7050003000 {
579 compatible = "sophgo,sg2044-reset",
580 "sophgo,sg2042-reset";
582 #reset-cells = <1>;