Lines Matching +full:cv1800b +full:- +full:rtc
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "cv18xx-reset.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
17 compatible = "fixed-clock";
18 clock-output-names = "osc_25m";
19 #clock-cells = <0>;
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <1>;
28 rst: reset-controller@3003000 {
29 compatible = "sophgo,cv1800b-reset";
31 #reset-cells = <1>;
34 mdio: mdio-mux@3009800 {
35 compatible = "mdio-mux-mmioreg", "mdio-mux";
37 #address-cells = <1>;
38 #size-cells = <0>;
39 mdio-parent-bus = <&gmac0_mdio>;
40 mux-mask = <0x80>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "ethernet-phy-ieee802.3-c22";
55 #address-cells = <1>;
56 #size-cells = <0>;
62 compatible = "snps,dw-apb-gpio";
64 #address-cells = <1>;
65 #size-cells = <0>;
68 porta: gpio-controller@0 {
69 compatible = "snps,dw-apb-gpio-port";
70 gpio-controller;
71 #gpio-cells = <2>;
74 interrupt-controller;
75 #interrupt-cells = <2>;
81 compatible = "snps,dw-apb-gpio";
83 #address-cells = <1>;
84 #size-cells = <0>;
87 portb: gpio-controller@0 {
88 compatible = "snps,dw-apb-gpio-port";
89 gpio-controller;
90 #gpio-cells = <2>;
93 interrupt-controller;
94 #interrupt-cells = <2>;
100 compatible = "snps,dw-apb-gpio";
102 #address-cells = <1>;
103 #size-cells = <0>;
106 portc: gpio-controller@0 {
107 compatible = "snps,dw-apb-gpio-port";
108 gpio-controller;
109 #gpio-cells = <2>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
119 compatible = "snps,dw-apb-gpio";
121 #address-cells = <1>;
122 #size-cells = <0>;
125 portd: gpio-controller@0 {
126 compatible = "snps,dw-apb-gpio-port";
127 gpio-controller;
128 #gpio-cells = <2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
138 compatible = "sophgo,cv1800b-saradc";
142 #address-cells = <1>;
143 #size-cells = <0>;
160 compatible = "snps,designware-i2c";
162 #address-cells = <1>;
163 #size-cells = <0>;
165 clock-names = "ref", "pclk";
172 compatible = "snps,designware-i2c";
174 #address-cells = <1>;
175 #size-cells = <0>;
177 clock-names = "ref", "pclk";
184 compatible = "snps,designware-i2c";
186 #address-cells = <1>;
187 #size-cells = <0>;
189 clock-names = "ref", "pclk";
196 compatible = "snps,designware-i2c";
198 #address-cells = <1>;
199 #size-cells = <0>;
201 clock-names = "ref", "pclk";
208 compatible = "snps,designware-i2c";
210 #address-cells = <1>;
211 #size-cells = <0>;
213 clock-names = "ref", "pclk";
220 compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a";
223 clock-names = "stmmaceth", "ptp_ref";
225 interrupt-names = "macirq";
226 phy-handle = <&internal_ephy>;
227 phy-mode = "internal";
229 reset-names = "stmmaceth";
230 rx-fifo-depth = <8192>;
231 tx-fifo-depth = <8192>;
232 snps,multicast-filter-bins = <0>;
233 snps,perfect-filter-entries = <1>;
237 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
238 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
239 snps,axi-config = <&gmac0_stmmac_axi_setup>;
243 compatible = "snps,dwmac-mdio";
244 #address-cells = <1>;
245 #size-cells = <0>;
248 gmac0_mtl_rx_setup: rx-queues-config {
249 snps,rx-queues-to-use = <1>;
253 gmac0_mtl_tx_setup: tx-queues-config {
254 snps,tx-queues-to-use = <1>;
258 gmac0_stmmac_axi_setup: stmmac-axi-config {
266 compatible = "snps,dw-apb-uart";
270 clock-names = "baudclk", "apb_pclk";
271 reg-shift = <2>;
272 reg-io-width = <4>;
278 compatible = "snps,dw-apb-uart";
282 clock-names = "baudclk", "apb_pclk";
283 reg-shift = <2>;
284 reg-io-width = <4>;
290 compatible = "snps,dw-apb-uart";
294 clock-names = "baudclk", "apb_pclk";
295 reg-shift = <2>;
296 reg-io-width = <4>;
302 compatible = "snps,dw-apb-uart";
306 clock-names = "baudclk", "apb_pclk";
307 reg-shift = <2>;
308 reg-io-width = <4>;
314 compatible = "snps,dw-apb-ssi";
316 #address-cells = <1>;
317 #size-cells = <0>;
319 clock-names = "ssi_clk", "pclk";
326 compatible = "snps,dw-apb-ssi";
328 #address-cells = <1>;
329 #size-cells = <0>;
331 clock-names = "ssi_clk", "pclk";
338 compatible = "snps,dw-apb-ssi";
340 #address-cells = <1>;
341 #size-cells = <0>;
343 clock-names = "ssi_clk", "pclk";
350 compatible = "snps,dw-apb-ssi";
352 #address-cells = <1>;
353 #size-cells = <0>;
355 clock-names = "ssi_clk", "pclk";
362 compatible = "snps,dw-apb-uart";
366 clock-names = "baudclk", "apb_pclk";
367 reg-shift = <2>;
368 reg-io-width = <4>;
374 compatible = "sophgo,cv1800b-dwcmshc";
379 clock-names = "core", "bus";
384 compatible = "sophgo,cv1800b-dwcmshc";
389 clock-names = "core", "bus";
393 dmac: dma-controller@4330000 {
394 compatible = "snps,axi-dma-1.01a";
398 clock-names = "core-clk", "cfgr-clk";
399 #dma-cells = <1>;
400 dma-channels = <8>;
401 snps,block-size = <1024 1024 1024 1024
404 snps,dma-masters = <2>;
405 snps,data-width = <2>;
409 rtc@5025000 {
410 compatible = "sophgo,cv1800b-rtc", "syscon";
415 interrupt-names = "alarm", "longpress", "vbat";
418 clock-names = "rtc", "mcu";