Lines Matching full:have
90 bool "Have write through data caches"
107 bool "Have instruction l.ff1"
113 bool "Have instruction l.fl1"
119 bool "Have instruction l.mul for hardware multiply"
125 bool "Have instruction l.div for hardware divide"
131 bool "Have instruction l.cmov for conditional move"
144 bool "Have instruction l.ror for rotate right"
157 bool "Have instruction l.rori for rotate right with immediate"
170 bool "Have instructions l.ext* for sign extension"
193 This enables support for systems with more than one CPU. If you have
194 a system with only one CPU, say N. If you have a system with more
217 OpenRISC architecture makes it optional to have it implemented
218 in hardware and the OR1200 does not have it.
250 your kernel crashes this doesn't have any influence.