Lines Matching defs:opcode
530 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
541 offset = opcode & OFFSET;
546 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
564 regs->regs[(opcode & RT) >> 16] = value;
569 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
581 offset = opcode & OFFSET;
586 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
587 reg = (opcode & RT) >> 16;
611 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
617 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
619 if ((opcode & OPCODE) == LL) {
622 return simulate_ll(regs, opcode);
624 if ((opcode & OPCODE) == SC) {
627 return simulate_sc(regs, opcode);
672 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
674 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
675 int rd = (opcode & RD) >> 11;
676 int rt = (opcode & RT) >> 16;
686 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
688 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
689 int rd = (opcode & MM_RS) >> 16;
690 int rt = (opcode & MM_RT) >> 21;
699 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
701 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
724 unsigned int opcode)
726 int op = opcode & OPCODE;
727 int op2 = opcode & CSR_OPCODE2_MASK;
728 int csr_func = (opcode & CSR_FUNC_MASK) >> 16;
731 int rd = (opcode & RD) >> 11;
732 int rs = (opcode & RS) >> 21;
824 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
827 union mips_instruction inst = { .word = opcode };
833 switch (inst.i_format.opcode) {
961 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
1032 unsigned int opcode, bcode;
1054 opcode = (instr[0] << 16) | instr[1];
1055 bcode = (opcode >> 6) & ((1 << 20) - 1);
1058 if (__get_inst32(&opcode, (u32 *)epc, user))
1060 bcode = (opcode >> 6) & ((1 << 20) - 1);
1065 * code starts left to bit 16 instead to bit 6 in the opcode.
1118 u32 opcode, tcode = 0;
1130 opcode = (instr[0] << 16) | instr[1];
1132 if (!(opcode & OPCODE))
1133 tcode = (opcode >> 12) & ((1 << 4) - 1);
1135 if (__get_inst32(&opcode, (u32 *)epc, user))
1138 if (!(opcode & OPCODE))
1139 tcode = (opcode >> 6) & ((1 << 10) - 1);
1159 unsigned int opcode = 0;
1168 likely(get_user(opcode, epc) >= 0)) {
1171 status = mipsr2_decoder(regs, opcode, &fcr31);
1201 if (unlikely(get_user(opcode, epc) < 0))
1205 status = simulate_llsc(regs, opcode);
1208 status = simulate_rdhwr_normal(regs, opcode);
1211 status = simulate_sync(regs, opcode);
1214 status = simulate_fp(regs, opcode, old_epc, old31);
1218 status = simulate_loongson3_cpucfg(regs, opcode);
1227 opcode = mmop[0];
1228 opcode = (opcode << 16) | mmop[1];
1231 status = simulate_rdhwr_mm(regs, opcode);
1409 unsigned int opcode;
1424 opcode = 0;
1431 if (unlikely(get_user(opcode, epc) < 0))
1435 status = simulate_llsc(regs, opcode);
1452 * The COP3 opcode space and consequently the CP0.Status.CU3