Lines Matching +full:dcb +full:- +full:algorithm
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 /* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */
31 #address-cells = <2>;
32 #size-cells = <2>;
33 interrupt-parent = <&gic>;
35 audio_extal_clk: audio-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
39 clock-frequency = <0>;
49 cluster0_opp: opp-table-0 {
50 compatible = "operating-points-v2";
52 opp-1700000000 {
53 opp-hz = /bits/ 64 <1700000000>;
54 opp-microvolt = <900000>;
55 clock-latency-ns = <300000>;
57 opp-850000000 {
58 opp-hz = /bits/ 64 <850000000>;
59 opp-microvolt = <800000>;
60 clock-latency-ns = <300000>;
62 opp-425000000 {
63 opp-hz = /bits/ 64 <425000000>;
64 opp-microvolt = <800000>;
65 clock-latency-ns = <300000>;
67 opp-212500000 {
68 opp-hz = /bits/ 64 <212500000>;
69 opp-microvolt = <800000>;
70 clock-latency-ns = <300000>;
71 opp-suspend;
76 #address-cells = <1>;
77 #size-cells = <0>;
80 compatible = "arm,cortex-a55";
83 next-level-cache = <&L3_CA55>;
84 enable-method = "psci";
86 operating-points-v2 = <&cluster0_opp>;
90 compatible = "arm,cortex-a55";
93 next-level-cache = <&L3_CA55>;
94 enable-method = "psci";
96 operating-points-v2 = <&cluster0_opp>;
100 compatible = "arm,cortex-a55";
103 next-level-cache = <&L3_CA55>;
104 enable-method = "psci";
106 operating-points-v2 = <&cluster0_opp>;
110 compatible = "arm,cortex-a55";
113 next-level-cache = <&L3_CA55>;
114 enable-method = "psci";
116 operating-points-v2 = <&cluster0_opp>;
119 L3_CA55: cache-controller-0 {
121 cache-unified;
122 cache-size = <0x100000>;
123 cache-level = <3>;
127 gpu_opp_table: opp-table-1 {
128 compatible = "operating-points-v2";
130 opp-630000000 {
131 opp-hz = /bits/ 64 <630000000>;
132 opp-microvolt = <800000>;
135 opp-315000000 {
136 opp-hz = /bits/ 64 <315000000>;
137 opp-microvolt = <800000>;
140 opp-157500000 {
141 opp-hz = /bits/ 64 <157500000>;
142 opp-microvolt = <800000>;
145 opp-78750000 {
146 opp-hz = /bits/ 64 <78750000>;
147 opp-microvolt = <800000>;
150 opp-19687500 {
151 opp-hz = /bits/ 64 <19687500>;
152 opp-microvolt = <800000>;
157 compatible = "arm,cortex-a55-pmu";
162 compatible = "arm,psci-1.0", "arm,psci-0.2";
166 qextal_clk: qextal-clk {
167 compatible = "fixed-clock";
168 #clock-cells = <0>;
170 clock-frequency = <0>;
173 rtxin_clk: rtxin-clk {
174 compatible = "fixed-clock";
175 #clock-cells = <0>;
177 clock-frequency = <0>;
181 compatible = "simple-bus";
182 #address-cells = <2>;
183 #size-cells = <2>;
187 compatible = "renesas,r9a09g056-pinctrl";
190 gpio-controller;
191 #gpio-cells = <2>;
192 gpio-ranges = <&pinctrl 0 0 96>;
193 power-domains = <&cpg>;
197 cpg: clock-controller@10420000 {
198 compatible = "renesas,r9a09g056-cpg";
201 clock-names = "audio_extal", "rtxin", "qextal";
202 #clock-cells = <2>;
203 #reset-cells = <1>;
204 #power-domain-cells = <0>;
207 sys: system-controller@10430000 {
208 compatible = "renesas,r9a09g056-sys";
215 compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi";
218 reg-names = "regs", "dirmap";
221 interrupt-names = "pulse", "err_pulse";
226 clock-names = "ahb", "axi", "spi", "spix2";
228 reset-names = "hresetn", "aresetn";
229 power-domains = <&cpg>;
230 #address-cells = <1>;
231 #size-cells = <0>;
236 compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
241 power-domains = <&cpg>;
246 compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
251 power-domains = <&cpg>;
256 compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
261 power-domains = <&cpg>;
266 compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
271 power-domains = <&cpg>;
276 compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
281 power-domains = <&cpg>;
286 compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
291 power-domains = <&cpg>;
296 compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
301 power-domains = <&cpg>;
306 compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
311 power-domains = <&cpg>;
316 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
319 clock-names = "pclk", "oscclk";
321 power-domains = <&cpg>;
326 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
329 clock-names = "pclk", "oscclk";
331 power-domains = <&cpg>;
336 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
339 clock-names = "pclk", "oscclk";
341 power-domains = <&cpg>;
346 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
349 clock-names = "pclk", "oscclk";
351 power-domains = <&cpg>;
356 compatible = "renesas,scif-r9a09g056",
357 "renesas,scif-r9a09g057";
368 interrupt-names = "eri", "rxi", "txi", "bri", "dri",
369 "tei", "tei-dri", "rxi-edge", "txi-edge";
371 clock-names = "fck";
372 power-domains = <&cpg>;
378 compatible = "renesas,r9a09g056-i3c", "renesas,r9a09g047-i3c";
381 clock-names = "pclk", "tclk", "pclkrw";
398 interrupt-names = "ierr", "terr", "abort", "resp",
403 reset-names = "presetn", "tresetn";
404 power-domains = <&cpg>;
405 #address-cells = <3>;
406 #size-cells = <0>;
411 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
421 interrupt-names = "tei", "ri", "ti", "spi", "sti",
425 power-domains = <&cpg>;
426 #address-cells = <1>;
427 #size-cells = <0>;
432 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
442 interrupt-names = "tei", "ri", "ti", "spi", "sti",
446 power-domains = <&cpg>;
447 #address-cells = <1>;
448 #size-cells = <0>;
453 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
463 interrupt-names = "tei", "ri", "ti", "spi", "sti",
467 power-domains = <&cpg>;
468 #address-cells = <1>;
469 #size-cells = <0>;
474 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
484 interrupt-names = "tei", "ri", "ti", "spi", "sti",
488 power-domains = <&cpg>;
489 #address-cells = <1>;
490 #size-cells = <0>;
495 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
505 interrupt-names = "tei", "ri", "ti", "spi", "sti",
509 power-domains = <&cpg>;
510 #address-cells = <1>;
511 #size-cells = <0>;
516 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
526 interrupt-names = "tei", "ri", "ti", "spi", "sti",
530 power-domains = <&cpg>;
531 #address-cells = <1>;
532 #size-cells = <0>;
537 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
547 interrupt-names = "tei", "ri", "ti", "spi", "sti",
551 power-domains = <&cpg>;
552 #address-cells = <1>;
553 #size-cells = <0>;
558 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
568 interrupt-names = "tei", "ri", "ti", "spi", "sti",
572 power-domains = <&cpg>;
573 #address-cells = <1>;
574 #size-cells = <0>;
579 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
589 interrupt-names = "tei", "ri", "ti", "spi", "sti",
593 power-domains = <&cpg>;
594 #address-cells = <1>;
595 #size-cells = <0>;
600 compatible = "renesas,r9a09g056-mali",
601 "arm,mali-bifrost";
607 interrupt-names = "job", "mmu", "gpu", "event";
611 clock-names = "gpu", "bus", "bus_ace";
615 reset-names = "rst", "axi_rst", "ace_rst";
616 power-domains = <&cpg>;
617 operating-points-v2 = <&gpu_opp_table>;
621 gic: interrupt-controller@14900000 {
622 compatible = "arm,gic-v3";
625 #interrupt-cells = <3>;
626 #address-cells = <0>;
627 interrupt-controller;
632 compatible = "generic-ohci";
638 phy-names = "usb";
639 power-domains = <&cpg>;
644 compatible = "generic-ehci";
650 phy-names = "usb";
652 power-domains = <&cpg>;
656 usb2_phy0: usb-phy@15800200 {
657 compatible = "renesas,usb2-phy-r9a09g056", "renesas,usb2-phy-r9a09g057";
662 clock-names = "fck", "usb_x1";
664 #phy-cells = <1>;
665 power-domains = <&cpg>;
670 compatible = "renesas,usbhs-r9a09g056",
671 "renesas,rzg2l-usbhs";
681 phy-names = "usb";
682 power-domains = <&cpg>;
686 usb20phyrst: usb20phy-reset@15830000 {
687 compatible = "renesas,r9a09g056-usb2phy-reset",
688 "renesas,r9a09g057-usb2phy-reset";
692 power-domains = <&cpg>;
693 #reset-cells = <0>;
698 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
704 clock-names = "core", "clkh", "cd", "aclk";
706 power-domains = <&cpg>;
709 sdhi0_vqmmc: vqmmc-regulator {
710 regulator-name = "SDHI0-VQMMC";
711 regulator-min-microvolt = <1800000>;
712 regulator-max-microvolt = <3300000>;
718 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
724 clock-names = "core", "clkh", "cd", "aclk";
726 power-domains = <&cpg>;
729 sdhi1_vqmmc: vqmmc-regulator {
730 regulator-name = "SDHI1-VQMMC";
731 regulator-min-microvolt = <1800000>;
732 regulator-max-microvolt = <3300000>;
738 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
744 clock-names = "core", "clkh", "cd", "aclk";
746 power-domains = <&cpg>;
749 sdhi2_vqmmc: vqmmc-regulator {
750 regulator-name = "SDHI2-VQMMC";
751 regulator-min-microvolt = <1800000>;
752 regulator-max-microvolt = <3300000>;
758 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth",
759 "snps,dwmac-5.20";
772 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
773 "rx-queue-0", "rx-queue-1", "rx-queue-2",
774 "rx-queue-3", "tx-queue-0", "tx-queue-1",
775 "tx-queue-2", "tx-queue-3";
780 clock-names = "stmmaceth", "pclk", "ptp_ref",
781 "tx", "rx", "tx-180", "rx-180";
783 power-domains = <&cpg>;
784 snps,multicast-filter-bins = <256>;
785 snps,perfect-filter-entries = <128>;
786 rx-fifo-depth = <8192>;
787 tx-fifo-depth = <8192>;
788 snps,fixed-burst;
789 snps,no-pbl-x8;
791 snps,axi-config = <&stmmac_axi_setup>;
792 snps,mtl-rx-config = <&mtl_rx_setup0>;
793 snps,mtl-tx-config = <&mtl_tx_setup0>;
799 compatible = "snps,dwmac-mdio";
800 #address-cells = <1>;
801 #size-cells = <0>;
804 mtl_rx_setup0: rx-queues-config {
805 snps,rx-queues-to-use = <4>;
806 snps,rx-sched-sp;
809 snps,dcb-algorithm;
811 snps,map-to-dma-channel = <0>;
815 snps,dcb-algorithm;
817 snps,map-to-dma-channel = <1>;
821 snps,dcb-algorithm;
823 snps,map-to-dma-channel = <2>;
827 snps,dcb-algorithm;
829 snps,map-to-dma-channel = <3>;
833 mtl_tx_setup0: tx-queues-config {
834 snps,tx-queues-to-use = <4>;
837 snps,dcb-algorithm;
842 snps,dcb-algorithm;
847 snps,dcb-algorithm;
852 snps,dcb-algorithm;
859 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth",
860 "snps,dwmac-5.20";
873 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
874 "rx-queue-0", "rx-queue-1", "rx-queue-2",
875 "rx-queue-3", "tx-queue-0", "tx-queue-1",
876 "tx-queue-2", "tx-queue-3";
881 clock-names = "stmmaceth", "pclk", "ptp_ref",
882 "tx", "rx", "tx-180", "rx-180";
884 power-domains = <&cpg>;
885 snps,multicast-filter-bins = <256>;
886 snps,perfect-filter-entries = <128>;
887 rx-fifo-depth = <8192>;
888 tx-fifo-depth = <8192>;
889 snps,fixed-burst;
890 snps,no-pbl-x8;
892 snps,axi-config = <&stmmac_axi_setup>;
893 snps,mtl-rx-config = <&mtl_rx_setup1>;
894 snps,mtl-tx-config = <&mtl_tx_setup1>;
900 compatible = "snps,dwmac-mdio";
901 #address-cells = <1>;
902 #size-cells = <0>;
905 mtl_rx_setup1: rx-queues-config {
906 snps,rx-queues-to-use = <4>;
907 snps,rx-sched-sp;
910 snps,dcb-algorithm;
912 snps,map-to-dma-channel = <0>;
916 snps,dcb-algorithm;
918 snps,map-to-dma-channel = <1>;
922 snps,dcb-algorithm;
924 snps,map-to-dma-channel = <2>;
928 snps,dcb-algorithm;
930 snps,map-to-dma-channel = <3>;
934 mtl_tx_setup1: tx-queues-config {
935 snps,tx-queues-to-use = <4>;
938 snps,dcb-algorithm;
943 snps,dcb-algorithm;
948 snps,dcb-algorithm;
953 snps,dcb-algorithm;
960 stmmac_axi_setup: stmmac-axi-config {
968 compatible = "arm,armv8-timer";
974 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";