Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
11 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
12 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
13 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
16 #include <dt-bindings/dma/qcom-gpi.h>
17 #include <dt-bindings/firmware/qcom,scm.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/interconnect/qcom,icc.h>
20 #include <dt-bindings/interconnect/qcom,osm-l3.h>
21 #include <dt-bindings/interconnect/qcom,sdm845.h>
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 #include <dt-bindings/phy/phy-qcom-qmp.h>
24 #include <dt-bindings/phy/phy-qcom-qusb2.h>
25 #include <dt-bindings/power/qcom-rpmpd.h>
26 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
27 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
28 #include <dt-bindings/soc/qcom,apr.h>
29 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
30 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
31 #include <dt-bindings/thermal/thermal.h>
34 interrupt-parent = <&intc>;
36 #address-cells = <2>;
37 #size-cells = <2>;
77 xo_board: xo-board {
78 compatible = "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency = <38400000>;
81 clock-output-names = "xo_board";
84 sleep_clk: sleep-clk {
85 compatible = "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <32764>;
92 #address-cells = <2>;
93 #size-cells = <0>;
100 enable-method = "psci";
101 capacity-dmips-mhz = <611>;
102 dynamic-power-coefficient = <154>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
104 operating-points-v2 = <&cpu0_opp_table>;
107 power-domains = <&cpu_pd0>;
108 power-domain-names = "psci";
109 #cooling-cells = <2>;
110 next-level-cache = <&l2_0>;
111 l2_0: l2-cache {
113 cache-level = <2>;
114 cache-unified;
115 next-level-cache = <&l3_0>;
116 l3_0: l3-cache {
118 cache-level = <3>;
119 cache-unified;
129 enable-method = "psci";
130 capacity-dmips-mhz = <611>;
131 dynamic-power-coefficient = <154>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
133 operating-points-v2 = <&cpu0_opp_table>;
136 power-domains = <&cpu_pd1>;
137 power-domain-names = "psci";
138 #cooling-cells = <2>;
139 next-level-cache = <&l2_100>;
140 l2_100: l2-cache {
142 cache-level = <2>;
143 cache-unified;
144 next-level-cache = <&l3_0>;
153 enable-method = "psci";
154 capacity-dmips-mhz = <611>;
155 dynamic-power-coefficient = <154>;
156 qcom,freq-domain = <&cpufreq_hw 0>;
157 operating-points-v2 = <&cpu0_opp_table>;
160 power-domains = <&cpu_pd2>;
161 power-domain-names = "psci";
162 #cooling-cells = <2>;
163 next-level-cache = <&l2_200>;
164 l2_200: l2-cache {
166 cache-level = <2>;
167 cache-unified;
168 next-level-cache = <&l3_0>;
177 enable-method = "psci";
178 capacity-dmips-mhz = <611>;
179 dynamic-power-coefficient = <154>;
180 qcom,freq-domain = <&cpufreq_hw 0>;
181 operating-points-v2 = <&cpu0_opp_table>;
184 #cooling-cells = <2>;
185 power-domains = <&cpu_pd3>;
186 power-domain-names = "psci";
187 next-level-cache = <&l2_300>;
188 l2_300: l2-cache {
190 cache-level = <2>;
191 cache-unified;
192 next-level-cache = <&l3_0>;
201 enable-method = "psci";
202 capacity-dmips-mhz = <1024>;
203 dynamic-power-coefficient = <442>;
204 qcom,freq-domain = <&cpufreq_hw 1>;
205 operating-points-v2 = <&cpu4_opp_table>;
208 power-domains = <&cpu_pd4>;
209 power-domain-names = "psci";
210 #cooling-cells = <2>;
211 next-level-cache = <&l2_400>;
212 l2_400: l2-cache {
214 cache-level = <2>;
215 cache-unified;
216 next-level-cache = <&l3_0>;
225 enable-method = "psci";
226 capacity-dmips-mhz = <1024>;
227 dynamic-power-coefficient = <442>;
228 qcom,freq-domain = <&cpufreq_hw 1>;
229 operating-points-v2 = <&cpu4_opp_table>;
232 power-domains = <&cpu_pd5>;
233 power-domain-names = "psci";
234 #cooling-cells = <2>;
235 next-level-cache = <&l2_500>;
236 l2_500: l2-cache {
238 cache-level = <2>;
239 cache-unified;
240 next-level-cache = <&l3_0>;
249 enable-method = "psci";
250 capacity-dmips-mhz = <1024>;
251 dynamic-power-coefficient = <442>;
252 qcom,freq-domain = <&cpufreq_hw 1>;
253 operating-points-v2 = <&cpu4_opp_table>;
256 power-domains = <&cpu_pd6>;
257 power-domain-names = "psci";
258 #cooling-cells = <2>;
259 next-level-cache = <&l2_600>;
260 l2_600: l2-cache {
262 cache-level = <2>;
263 cache-unified;
264 next-level-cache = <&l3_0>;
273 enable-method = "psci";
274 capacity-dmips-mhz = <1024>;
275 dynamic-power-coefficient = <442>;
276 qcom,freq-domain = <&cpufreq_hw 1>;
277 operating-points-v2 = <&cpu4_opp_table>;
280 power-domains = <&cpu_pd7>;
281 power-domain-names = "psci";
282 #cooling-cells = <2>;
283 next-level-cache = <&l2_700>;
284 l2_700: l2-cache {
286 cache-level = <2>;
287 cache-unified;
288 next-level-cache = <&l3_0>;
292 cpu-map {
328 cpu_idle_states: idle-states {
329 entry-method = "psci";
331 little_cpu_sleep_0: cpu-sleep-0-0 {
332 compatible = "arm,idle-state";
333 idle-state-name = "little-rail-power-collapse";
334 arm,psci-suspend-param = <0x40000004>;
335 entry-latency-us = <350>;
336 exit-latency-us = <461>;
337 min-residency-us = <1890>;
338 local-timer-stop;
341 big_cpu_sleep_0: cpu-sleep-1-0 {
342 compatible = "arm,idle-state";
343 idle-state-name = "big-rail-power-collapse";
344 arm,psci-suspend-param = <0x40000004>;
345 entry-latency-us = <264>;
346 exit-latency-us = <621>;
347 min-residency-us = <952>;
348 local-timer-stop;
352 domain-idle-states {
353 cluster_sleep_0: cluster-sleep-0 {
354 compatible = "domain-idle-state";
355 arm,psci-suspend-param = <0x4100c244>;
356 entry-latency-us = <3263>;
357 exit-latency-us = <6562>;
358 min-residency-us = <9987>;
365 compatible = "qcom,scm-sdm845", "qcom,scm";
375 cpu0_opp_table: opp-table-cpu0 {
376 compatible = "operating-points-v2";
377 opp-shared;
379 cpu0_opp1: opp-300000000 {
380 opp-hz = /bits/ 64 <300000000>;
381 opp-peak-kBps = <800000 4800000>;
384 cpu0_opp2: opp-403200000 {
385 opp-hz = /bits/ 64 <403200000>;
386 opp-peak-kBps = <800000 4800000>;
389 cpu0_opp3: opp-480000000 {
390 opp-hz = /bits/ 64 <480000000>;
391 opp-peak-kBps = <800000 6451200>;
394 cpu0_opp4: opp-576000000 {
395 opp-hz = /bits/ 64 <576000000>;
396 opp-peak-kBps = <800000 6451200>;
399 cpu0_opp5: opp-652800000 {
400 opp-hz = /bits/ 64 <652800000>;
401 opp-peak-kBps = <800000 7680000>;
404 cpu0_opp6: opp-748800000 {
405 opp-hz = /bits/ 64 <748800000>;
406 opp-peak-kBps = <1804000 9216000>;
409 cpu0_opp7: opp-825600000 {
410 opp-hz = /bits/ 64 <825600000>;
411 opp-peak-kBps = <1804000 9216000>;
414 cpu0_opp8: opp-902400000 {
415 opp-hz = /bits/ 64 <902400000>;
416 opp-peak-kBps = <1804000 10444800>;
419 cpu0_opp9: opp-979200000 {
420 opp-hz = /bits/ 64 <979200000>;
421 opp-peak-kBps = <1804000 11980800>;
424 cpu0_opp10: opp-1056000000 {
425 opp-hz = /bits/ 64 <1056000000>;
426 opp-peak-kBps = <1804000 11980800>;
429 cpu0_opp11: opp-1132800000 {
430 opp-hz = /bits/ 64 <1132800000>;
431 opp-peak-kBps = <2188000 13516800>;
434 cpu0_opp12: opp-1228800000 {
435 opp-hz = /bits/ 64 <1228800000>;
436 opp-peak-kBps = <2188000 15052800>;
439 cpu0_opp13: opp-1324800000 {
440 opp-hz = /bits/ 64 <1324800000>;
441 opp-peak-kBps = <2188000 16588800>;
444 cpu0_opp14: opp-1420800000 {
445 opp-hz = /bits/ 64 <1420800000>;
446 opp-peak-kBps = <3072000 18124800>;
449 cpu0_opp15: opp-1516800000 {
450 opp-hz = /bits/ 64 <1516800000>;
451 opp-peak-kBps = <3072000 19353600>;
454 cpu0_opp16: opp-1612800000 {
455 opp-hz = /bits/ 64 <1612800000>;
456 opp-peak-kBps = <4068000 19353600>;
459 cpu0_opp17: opp-1689600000 {
460 opp-hz = /bits/ 64 <1689600000>;
461 opp-peak-kBps = <4068000 20889600>;
464 cpu0_opp18: opp-1766400000 {
465 opp-hz = /bits/ 64 <1766400000>;
466 opp-peak-kBps = <4068000 22425600>;
470 cpu4_opp_table: opp-table-cpu4 {
471 compatible = "operating-points-v2";
472 opp-shared;
474 cpu4_opp1: opp-300000000 {
475 opp-hz = /bits/ 64 <300000000>;
476 opp-peak-kBps = <800000 4800000>;
479 cpu4_opp2: opp-403200000 {
480 opp-hz = /bits/ 64 <403200000>;
481 opp-peak-kBps = <800000 4800000>;
484 cpu4_opp3: opp-480000000 {
485 opp-hz = /bits/ 64 <480000000>;
486 opp-peak-kBps = <1804000 4800000>;
489 cpu4_opp4: opp-576000000 {
490 opp-hz = /bits/ 64 <576000000>;
491 opp-peak-kBps = <1804000 4800000>;
494 cpu4_opp5: opp-652800000 {
495 opp-hz = /bits/ 64 <652800000>;
496 opp-peak-kBps = <1804000 4800000>;
499 cpu4_opp6: opp-748800000 {
500 opp-hz = /bits/ 64 <748800000>;
501 opp-peak-kBps = <1804000 4800000>;
504 cpu4_opp7: opp-825600000 {
505 opp-hz = /bits/ 64 <825600000>;
506 opp-peak-kBps = <2188000 9216000>;
509 cpu4_opp8: opp-902400000 {
510 opp-hz = /bits/ 64 <902400000>;
511 opp-peak-kBps = <2188000 9216000>;
514 cpu4_opp9: opp-979200000 {
515 opp-hz = /bits/ 64 <979200000>;
516 opp-peak-kBps = <2188000 9216000>;
519 cpu4_opp10: opp-1056000000 {
520 opp-hz = /bits/ 64 <1056000000>;
521 opp-peak-kBps = <3072000 9216000>;
524 cpu4_opp11: opp-1132800000 {
525 opp-hz = /bits/ 64 <1132800000>;
526 opp-peak-kBps = <3072000 11980800>;
529 cpu4_opp12: opp-1209600000 {
530 opp-hz = /bits/ 64 <1209600000>;
531 opp-peak-kBps = <4068000 11980800>;
534 cpu4_opp13: opp-1286400000 {
535 opp-hz = /bits/ 64 <1286400000>;
536 opp-peak-kBps = <4068000 11980800>;
539 cpu4_opp14: opp-1363200000 {
540 opp-hz = /bits/ 64 <1363200000>;
541 opp-peak-kBps = <4068000 15052800>;
544 cpu4_opp15: opp-1459200000 {
545 opp-hz = /bits/ 64 <1459200000>;
546 opp-peak-kBps = <4068000 15052800>;
549 cpu4_opp16: opp-1536000000 {
550 opp-hz = /bits/ 64 <1536000000>;
551 opp-peak-kBps = <5412000 15052800>;
554 cpu4_opp17: opp-1612800000 {
555 opp-hz = /bits/ 64 <1612800000>;
556 opp-peak-kBps = <5412000 15052800>;
559 cpu4_opp18: opp-1689600000 {
560 opp-hz = /bits/ 64 <1689600000>;
561 opp-peak-kBps = <5412000 19353600>;
564 cpu4_opp19: opp-1766400000 {
565 opp-hz = /bits/ 64 <1766400000>;
566 opp-peak-kBps = <6220000 19353600>;
569 cpu4_opp20: opp-1843200000 {
570 opp-hz = /bits/ 64 <1843200000>;
571 opp-peak-kBps = <6220000 19353600>;
574 cpu4_opp21: opp-1920000000 {
575 opp-hz = /bits/ 64 <1920000000>;
576 opp-peak-kBps = <7216000 19353600>;
579 cpu4_opp22: opp-1996800000 {
580 opp-hz = /bits/ 64 <1996800000>;
581 opp-peak-kBps = <7216000 20889600>;
584 cpu4_opp23: opp-2092800000 {
585 opp-hz = /bits/ 64 <2092800000>;
586 opp-peak-kBps = <7216000 20889600>;
589 cpu4_opp24: opp-2169600000 {
590 opp-hz = /bits/ 64 <2169600000>;
591 opp-peak-kBps = <7216000 20889600>;
594 cpu4_opp25: opp-2246400000 {
595 opp-hz = /bits/ 64 <2246400000>;
596 opp-peak-kBps = <7216000 20889600>;
599 cpu4_opp26: opp-2323200000 {
600 opp-hz = /bits/ 64 <2323200000>;
601 opp-peak-kBps = <7216000 20889600>;
604 cpu4_opp27: opp-2400000000 {
605 opp-hz = /bits/ 64 <2400000000>;
606 opp-peak-kBps = <7216000 22425600>;
609 cpu4_opp28: opp-2476800000 {
610 opp-hz = /bits/ 64 <2476800000>;
611 opp-peak-kBps = <7216000 22425600>;
614 cpu4_opp29: opp-2553600000 {
615 opp-hz = /bits/ 64 <2553600000>;
616 opp-peak-kBps = <7216000 22425600>;
619 cpu4_opp30: opp-2649600000 {
620 opp-hz = /bits/ 64 <2649600000>;
621 opp-peak-kBps = <7216000 22425600>;
624 cpu4_opp31: opp-2745600000 {
625 opp-hz = /bits/ 64 <2745600000>;
626 opp-peak-kBps = <7216000 25497600>;
629 cpu4_opp32: opp-2803200000 {
630 opp-hz = /bits/ 64 <2803200000>;
631 opp-peak-kBps = <7216000 25497600>;
635 dsi_opp_table: opp-table-dsi {
636 compatible = "operating-points-v2";
638 opp-19200000 {
639 opp-hz = /bits/ 64 <19200000>;
640 required-opps = <&rpmhpd_opp_min_svs>;
643 opp-180000000 {
644 opp-hz = /bits/ 64 <180000000>;
645 required-opps = <&rpmhpd_opp_low_svs>;
648 opp-275000000 {
649 opp-hz = /bits/ 64 <275000000>;
650 required-opps = <&rpmhpd_opp_svs>;
653 opp-328580000 {
654 opp-hz = /bits/ 64 <328580000>;
655 required-opps = <&rpmhpd_opp_svs_l1>;
658 opp-358000000 {
659 opp-hz = /bits/ 64 <358000000>;
660 required-opps = <&rpmhpd_opp_nom>;
664 qspi_opp_table: opp-table-qspi {
665 compatible = "operating-points-v2";
667 opp-19200000 {
668 opp-hz = /bits/ 64 <19200000>;
669 required-opps = <&rpmhpd_opp_min_svs>;
672 opp-100000000 {
673 opp-hz = /bits/ 64 <100000000>;
674 required-opps = <&rpmhpd_opp_low_svs>;
677 opp-150000000 {
678 opp-hz = /bits/ 64 <150000000>;
679 required-opps = <&rpmhpd_opp_svs>;
682 opp-300000000 {
683 opp-hz = /bits/ 64 <300000000>;
684 required-opps = <&rpmhpd_opp_nom>;
688 qup_opp_table: opp-table-qup {
689 compatible = "operating-points-v2";
691 opp-50000000 {
692 opp-hz = /bits/ 64 <50000000>;
693 required-opps = <&rpmhpd_opp_min_svs>;
696 opp-75000000 {
697 opp-hz = /bits/ 64 <75000000>;
698 required-opps = <&rpmhpd_opp_low_svs>;
701 opp-100000000 {
702 opp-hz = /bits/ 64 <100000000>;
703 required-opps = <&rpmhpd_opp_svs>;
706 opp-128000000 {
707 opp-hz = /bits/ 64 <128000000>;
708 required-opps = <&rpmhpd_opp_nom>;
713 compatible = "arm,armv8-pmuv3";
718 compatible = "arm,psci-1.0";
721 cpu_pd0: power-domain-cpu0 {
722 #power-domain-cells = <0>;
723 power-domains = <&cluster_pd>;
724 domain-idle-states = <&little_cpu_sleep_0>;
727 cpu_pd1: power-domain-cpu1 {
728 #power-domain-cells = <0>;
729 power-domains = <&cluster_pd>;
730 domain-idle-states = <&little_cpu_sleep_0>;
733 cpu_pd2: power-domain-cpu2 {
734 #power-domain-cells = <0>;
735 power-domains = <&cluster_pd>;
736 domain-idle-states = <&little_cpu_sleep_0>;
739 cpu_pd3: power-domain-cpu3 {
740 #power-domain-cells = <0>;
741 power-domains = <&cluster_pd>;
742 domain-idle-states = <&little_cpu_sleep_0>;
745 cpu_pd4: power-domain-cpu4 {
746 #power-domain-cells = <0>;
747 power-domains = <&cluster_pd>;
748 domain-idle-states = <&big_cpu_sleep_0>;
751 cpu_pd5: power-domain-cpu5 {
752 #power-domain-cells = <0>;
753 power-domains = <&cluster_pd>;
754 domain-idle-states = <&big_cpu_sleep_0>;
757 cpu_pd6: power-domain-cpu6 {
758 #power-domain-cells = <0>;
759 power-domains = <&cluster_pd>;
760 domain-idle-states = <&big_cpu_sleep_0>;
763 cpu_pd7: power-domain-cpu7 {
764 #power-domain-cells = <0>;
765 power-domains = <&cluster_pd>;
766 domain-idle-states = <&big_cpu_sleep_0>;
769 cluster_pd: power-domain-cluster {
770 #power-domain-cells = <0>;
771 domain-idle-states = <&cluster_sleep_0>;
775 reserved-memory {
776 #address-cells = <2>;
777 #size-cells = <2>;
780 hyp_mem: hyp-mem@85700000 {
782 no-map;
785 xbl_mem: xbl-mem@85e00000 {
787 no-map;
790 aop_mem: aop-mem@85fc0000 {
792 no-map;
795 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
796 compatible = "qcom,cmd-db";
798 no-map;
804 no-map;
810 no-map;
814 compatible = "qcom,rmtfs-mem";
816 no-map;
818 qcom,client-id = <1>;
824 no-map;
827 camera_mem: camera-mem@8bf00000 {
829 no-map;
832 ipa_fw_mem: ipa-fw@8c400000 {
834 no-map;
837 ipa_gsi_mem: ipa-gsi@8c410000 {
839 no-map;
844 no-map;
849 no-map;
852 wlan_msa_mem: wlan-msa@8df00000 {
854 no-map;
859 no-map;
864 no-map;
869 no-map;
874 no-map;
879 no-map;
884 no-map;
887 mdata_mem: mpss-metadata {
888 alloc-ranges = <0 0xa0000000 0 0x20000000>;
890 no-map;
894 compatible = "shared-dma-pool";
895 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
902 adsp_pas: remoteproc-adsp {
903 compatible = "qcom,sdm845-adsp-pas";
905 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
910 interrupt-names = "wdog", "fatal", "ready",
911 "handover", "stop-ack";
914 clock-names = "xo";
916 memory-region = <&adsp_mem>;
920 qcom,smem-states = <&adsp_smp2p_out 0>;
921 qcom,smem-state-names = "stop";
925 glink-edge {
928 qcom,remote-pid = <2>;
932 compatible = "qcom,apr-v2";
933 qcom,glink-channels = "apr_audio_svc";
935 #address-cells = <1>;
936 #size-cells = <0>;
942 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
950 compatible = "qcom,q6afe-dais";
951 #address-cells = <1>;
952 #size-cells = <0>;
953 #sound-dai-cells = <1>;
960 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
962 compatible = "qcom,q6asm-dais";
963 #address-cells = <1>;
964 #size-cells = <0>;
965 #sound-dai-cells = <1>;
973 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
975 compatible = "qcom,q6adm-routing";
976 #sound-dai-cells = <0>;
983 qcom,glink-channels = "fastrpcglink-apps-dsp";
985 qcom,non-secure-domain;
986 #address-cells = <1>;
987 #size-cells = <0>;
989 compute-cb@3 {
990 compatible = "qcom,fastrpc-compute-cb";
995 compute-cb@4 {
996 compatible = "qcom,fastrpc-compute-cb";
1004 cdsp_pas: remoteproc-cdsp {
1005 compatible = "qcom,sdm845-cdsp-pas";
1007 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1012 interrupt-names = "wdog", "fatal", "ready",
1013 "handover", "stop-ack";
1016 clock-names = "xo";
1018 memory-region = <&cdsp_mem>;
1022 qcom,smem-states = <&cdsp_smp2p_out 0>;
1023 qcom,smem-state-names = "stop";
1027 glink-edge {
1030 qcom,remote-pid = <5>;
1034 qcom,glink-channels = "fastrpcglink-apps-dsp";
1036 qcom,non-secure-domain;
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1040 compute-cb@1 {
1041 compatible = "qcom,fastrpc-compute-cb";
1046 compute-cb@2 {
1047 compatible = "qcom,fastrpc-compute-cb";
1052 compute-cb@3 {
1053 compatible = "qcom,fastrpc-compute-cb";
1058 compute-cb@4 {
1059 compatible = "qcom,fastrpc-compute-cb";
1064 compute-cb@5 {
1065 compatible = "qcom,fastrpc-compute-cb";
1070 compute-cb@6 {
1071 compatible = "qcom,fastrpc-compute-cb";
1076 compute-cb@7 {
1077 compatible = "qcom,fastrpc-compute-cb";
1082 compute-cb@8 {
1083 compatible = "qcom,fastrpc-compute-cb";
1091 smp2p-cdsp {
1099 qcom,local-pid = <0>;
1100 qcom,remote-pid = <5>;
1102 cdsp_smp2p_out: master-kernel {
1103 qcom,entry-name = "master-kernel";
1104 #qcom,smem-state-cells = <1>;
1107 cdsp_smp2p_in: slave-kernel {
1108 qcom,entry-name = "slave-kernel";
1110 interrupt-controller;
1111 #interrupt-cells = <2>;
1115 smp2p-lpass {
1123 qcom,local-pid = <0>;
1124 qcom,remote-pid = <2>;
1126 adsp_smp2p_out: master-kernel {
1127 qcom,entry-name = "master-kernel";
1128 #qcom,smem-state-cells = <1>;
1131 adsp_smp2p_in: slave-kernel {
1132 qcom,entry-name = "slave-kernel";
1134 interrupt-controller;
1135 #interrupt-cells = <2>;
1139 smp2p-mpss {
1144 qcom,local-pid = <0>;
1145 qcom,remote-pid = <1>;
1147 modem_smp2p_out: master-kernel {
1148 qcom,entry-name = "master-kernel";
1149 #qcom,smem-state-cells = <1>;
1152 modem_smp2p_in: slave-kernel {
1153 qcom,entry-name = "slave-kernel";
1154 interrupt-controller;
1155 #interrupt-cells = <2>;
1158 ipa_smp2p_out: ipa-ap-to-modem {
1159 qcom,entry-name = "ipa";
1160 #qcom,smem-state-cells = <1>;
1163 ipa_smp2p_in: ipa-modem-to-ap {
1164 qcom,entry-name = "ipa";
1165 interrupt-controller;
1166 #interrupt-cells = <2>;
1170 smp2p-slpi {
1175 qcom,local-pid = <0>;
1176 qcom,remote-pid = <3>;
1178 slpi_smp2p_out: master-kernel {
1179 qcom,entry-name = "master-kernel";
1180 #qcom,smem-state-cells = <1>;
1183 slpi_smp2p_in: slave-kernel {
1184 qcom,entry-name = "slave-kernel";
1185 interrupt-controller;
1186 #interrupt-cells = <2>;
1191 #address-cells = <2>;
1192 #size-cells = <2>;
1194 dma-ranges = <0 0 0 0 0x10 0>;
1195 compatible = "simple-bus";
1197 gcc: clock-controller@100000 {
1198 compatible = "qcom,gcc-sdm845";
1205 clock-names = "bi_tcxo",
1210 #clock-cells = <1>;
1211 #reset-cells = <1>;
1212 #power-domain-cells = <1>;
1213 power-domains = <&rpmhpd SDM845_CX>;
1217 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1219 #address-cells = <1>;
1220 #size-cells = <1>;
1222 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1227 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1234 compatible = "qcom,prng-ee";
1237 clock-names = "core";
1240 gpi_dma0: dma-controller@800000 {
1241 #dma-cells = <3>;
1242 compatible = "qcom,sdm845-gpi-dma";
1257 dma-channels = <13>;
1258 dma-channel-mask = <0xfa>;
1264 compatible = "qcom,geni-se-qup";
1266 clock-names = "m-ahb", "s-ahb";
1270 #address-cells = <2>;
1271 #size-cells = <2>;
1274 interconnect-names = "qup-core";
1278 compatible = "qcom,geni-i2c";
1280 clock-names = "se";
1282 pinctrl-names = "default";
1283 pinctrl-0 = <&qup_i2c0_default>;
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1287 power-domains = <&rpmhpd SDM845_CX>;
1288 operating-points-v2 = <&qup_opp_table>;
1292 interconnect-names = "qup-core", "qup-config", "qup-memory";
1295 dma-names = "tx", "rx";
1300 compatible = "qcom,geni-spi";
1302 clock-names = "se";
1304 pinctrl-names = "default";
1305 pinctrl-0 = <&qup_spi0_default>;
1307 #address-cells = <1>;
1308 #size-cells = <0>;
1311 interconnect-names = "qup-core", "qup-config";
1314 dma-names = "tx", "rx";
1319 compatible = "qcom,geni-uart";
1321 clock-names = "se";
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&qup_uart0_default>;
1326 power-domains = <&rpmhpd SDM845_CX>;
1327 operating-points-v2 = <&qup_opp_table>;
1330 interconnect-names = "qup-core", "qup-config";
1335 compatible = "qcom,geni-i2c";
1337 clock-names = "se";
1339 pinctrl-names = "default";
1340 pinctrl-0 = <&qup_i2c1_default>;
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1344 power-domains = <&rpmhpd SDM845_CX>;
1345 operating-points-v2 = <&qup_opp_table>;
1349 interconnect-names = "qup-core", "qup-config", "qup-memory";
1352 dma-names = "tx", "rx";
1357 compatible = "qcom,geni-spi";
1359 clock-names = "se";
1361 pinctrl-names = "default";
1362 pinctrl-0 = <&qup_spi1_default>;
1364 #address-cells = <1>;
1365 #size-cells = <0>;
1368 interconnect-names = "qup-core", "qup-config";
1371 dma-names = "tx", "rx";
1376 compatible = "qcom,geni-uart";
1378 clock-names = "se";
1380 pinctrl-names = "default";
1381 pinctrl-0 = <&qup_uart1_default>;
1383 power-domains = <&rpmhpd SDM845_CX>;
1384 operating-points-v2 = <&qup_opp_table>;
1387 interconnect-names = "qup-core", "qup-config";
1392 compatible = "qcom,geni-i2c";
1394 clock-names = "se";
1396 pinctrl-names = "default";
1397 pinctrl-0 = <&qup_i2c2_default>;
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1401 power-domains = <&rpmhpd SDM845_CX>;
1402 operating-points-v2 = <&qup_opp_table>;
1406 interconnect-names = "qup-core", "qup-config", "qup-memory";
1409 dma-names = "tx", "rx";
1414 compatible = "qcom,geni-spi";
1416 clock-names = "se";
1418 pinctrl-names = "default";
1419 pinctrl-0 = <&qup_spi2_default>;
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1425 interconnect-names = "qup-core", "qup-config";
1428 dma-names = "tx", "rx";
1433 compatible = "qcom,geni-uart";
1435 clock-names = "se";
1437 pinctrl-names = "default";
1438 pinctrl-0 = <&qup_uart2_default>;
1440 power-domains = <&rpmhpd SDM845_CX>;
1441 operating-points-v2 = <&qup_opp_table>;
1444 interconnect-names = "qup-core", "qup-config";
1449 compatible = "qcom,geni-i2c";
1451 clock-names = "se";
1453 pinctrl-names = "default";
1454 pinctrl-0 = <&qup_i2c3_default>;
1456 #address-cells = <1>;
1457 #size-cells = <0>;
1458 power-domains = <&rpmhpd SDM845_CX>;
1459 operating-points-v2 = <&qup_opp_table>;
1463 interconnect-names = "qup-core", "qup-config", "qup-memory";
1466 dma-names = "tx", "rx";
1471 compatible = "qcom,geni-spi";
1473 clock-names = "se";
1475 pinctrl-names = "default";
1476 pinctrl-0 = <&qup_spi3_default>;
1478 #address-cells = <1>;
1479 #size-cells = <0>;
1482 interconnect-names = "qup-core", "qup-config";
1485 dma-names = "tx", "rx";
1490 compatible = "qcom,geni-uart";
1492 clock-names = "se";
1494 pinctrl-names = "default";
1495 pinctrl-0 = <&qup_uart3_default>;
1497 power-domains = <&rpmhpd SDM845_CX>;
1498 operating-points-v2 = <&qup_opp_table>;
1501 interconnect-names = "qup-core", "qup-config";
1506 compatible = "qcom,geni-i2c";
1508 clock-names = "se";
1510 pinctrl-names = "default";
1511 pinctrl-0 = <&qup_i2c4_default>;
1513 #address-cells = <1>;
1514 #size-cells = <0>;
1515 power-domains = <&rpmhpd SDM845_CX>;
1516 operating-points-v2 = <&qup_opp_table>;
1520 interconnect-names = "qup-core", "qup-config", "qup-memory";
1523 dma-names = "tx", "rx";
1528 compatible = "qcom,geni-spi";
1530 clock-names = "se";
1532 pinctrl-names = "default";
1533 pinctrl-0 = <&qup_spi4_default>;
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1539 interconnect-names = "qup-core", "qup-config";
1542 dma-names = "tx", "rx";
1547 compatible = "qcom,geni-uart";
1549 clock-names = "se";
1551 pinctrl-names = "default";
1552 pinctrl-0 = <&qup_uart4_default>;
1554 power-domains = <&rpmhpd SDM845_CX>;
1555 operating-points-v2 = <&qup_opp_table>;
1558 interconnect-names = "qup-core", "qup-config";
1563 compatible = "qcom,geni-i2c";
1565 clock-names = "se";
1567 pinctrl-names = "default";
1568 pinctrl-0 = <&qup_i2c5_default>;
1570 #address-cells = <1>;
1571 #size-cells = <0>;
1572 power-domains = <&rpmhpd SDM845_CX>;
1573 operating-points-v2 = <&qup_opp_table>;
1577 interconnect-names = "qup-core", "qup-config", "qup-memory";
1580 dma-names = "tx", "rx";
1585 compatible = "qcom,geni-spi";
1587 clock-names = "se";
1589 pinctrl-names = "default";
1590 pinctrl-0 = <&qup_spi5_default>;
1592 #address-cells = <1>;
1593 #size-cells = <0>;
1596 interconnect-names = "qup-core", "qup-config";
1599 dma-names = "tx", "rx";
1604 compatible = "qcom,geni-uart";
1606 clock-names = "se";
1608 pinctrl-names = "default";
1609 pinctrl-0 = <&qup_uart5_default>;
1611 power-domains = <&rpmhpd SDM845_CX>;
1612 operating-points-v2 = <&qup_opp_table>;
1615 interconnect-names = "qup-core", "qup-config";
1620 compatible = "qcom,geni-i2c";
1622 clock-names = "se";
1624 pinctrl-names = "default";
1625 pinctrl-0 = <&qup_i2c6_default>;
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1629 power-domains = <&rpmhpd SDM845_CX>;
1630 operating-points-v2 = <&qup_opp_table>;
1634 interconnect-names = "qup-core", "qup-config", "qup-memory";
1637 dma-names = "tx", "rx";
1642 compatible = "qcom,geni-spi";
1644 clock-names = "se";
1646 pinctrl-names = "default";
1647 pinctrl-0 = <&qup_spi6_default>;
1649 #address-cells = <1>;
1650 #size-cells = <0>;
1653 interconnect-names = "qup-core", "qup-config";
1656 dma-names = "tx", "rx";
1661 compatible = "qcom,geni-uart";
1663 clock-names = "se";
1665 pinctrl-names = "default";
1666 pinctrl-0 = <&qup_uart6_default>;
1668 power-domains = <&rpmhpd SDM845_CX>;
1669 operating-points-v2 = <&qup_opp_table>;
1672 interconnect-names = "qup-core", "qup-config";
1677 compatible = "qcom,geni-i2c";
1679 clock-names = "se";
1681 pinctrl-names = "default";
1682 pinctrl-0 = <&qup_i2c7_default>;
1684 #address-cells = <1>;
1685 #size-cells = <0>;
1686 power-domains = <&rpmhpd SDM845_CX>;
1687 operating-points-v2 = <&qup_opp_table>;
1692 compatible = "qcom,geni-spi";
1694 clock-names = "se";
1696 pinctrl-names = "default";
1697 pinctrl-0 = <&qup_spi7_default>;
1699 #address-cells = <1>;
1700 #size-cells = <0>;
1703 interconnect-names = "qup-core", "qup-config";
1706 dma-names = "tx", "rx";
1711 compatible = "qcom,geni-uart";
1713 clock-names = "se";
1715 pinctrl-names = "default";
1716 pinctrl-0 = <&qup_uart7_default>;
1718 power-domains = <&rpmhpd SDM845_CX>;
1719 operating-points-v2 = <&qup_opp_table>;
1722 interconnect-names = "qup-core", "qup-config";
1727 gpi_dma1: dma-controller@a00000 {
1728 #dma-cells = <3>;
1729 compatible = "qcom,sdm845-gpi-dma";
1744 dma-channels = <13>;
1745 dma-channel-mask = <0xfa>;
1751 compatible = "qcom,geni-se-qup";
1753 clock-names = "m-ahb", "s-ahb";
1757 #address-cells = <2>;
1758 #size-cells = <2>;
1761 interconnect-names = "qup-core";
1765 compatible = "qcom,geni-i2c";
1767 clock-names = "se";
1769 pinctrl-names = "default";
1770 pinctrl-0 = <&qup_i2c8_default>;
1772 #address-cells = <1>;
1773 #size-cells = <0>;
1774 power-domains = <&rpmhpd SDM845_CX>;
1775 operating-points-v2 = <&qup_opp_table>;
1779 interconnect-names = "qup-core", "qup-config", "qup-memory";
1782 dma-names = "tx", "rx";
1787 compatible = "qcom,geni-spi";
1789 clock-names = "se";
1791 pinctrl-names = "default";
1792 pinctrl-0 = <&qup_spi8_default>;
1794 #address-cells = <1>;
1795 #size-cells = <0>;
1798 interconnect-names = "qup-core", "qup-config";
1801 dma-names = "tx", "rx";
1806 compatible = "qcom,geni-uart";
1808 clock-names = "se";
1810 pinctrl-names = "default";
1811 pinctrl-0 = <&qup_uart8_default>;
1813 power-domains = <&rpmhpd SDM845_CX>;
1814 operating-points-v2 = <&qup_opp_table>;
1817 interconnect-names = "qup-core", "qup-config";
1822 compatible = "qcom,geni-i2c";
1824 clock-names = "se";
1826 pinctrl-names = "default";
1827 pinctrl-0 = <&qup_i2c9_default>;
1829 #address-cells = <1>;
1830 #size-cells = <0>;
1831 power-domains = <&rpmhpd SDM845_CX>;
1832 operating-points-v2 = <&qup_opp_table>;
1836 interconnect-names = "qup-core", "qup-config", "qup-memory";
1839 dma-names = "tx", "rx";
1844 compatible = "qcom,geni-spi";
1846 clock-names = "se";
1848 pinctrl-names = "default";
1849 pinctrl-0 = <&qup_spi9_default>;
1851 #address-cells = <1>;
1852 #size-cells = <0>;
1855 interconnect-names = "qup-core", "qup-config";
1858 dma-names = "tx", "rx";
1863 compatible = "qcom,geni-debug-uart";
1865 clock-names = "se";
1867 pinctrl-names = "default";
1868 pinctrl-0 = <&qup_uart9_default>;
1870 power-domains = <&rpmhpd SDM845_CX>;
1871 operating-points-v2 = <&qup_opp_table>;
1874 interconnect-names = "qup-core", "qup-config";
1879 compatible = "qcom,geni-i2c";
1881 clock-names = "se";
1883 pinctrl-names = "default";
1884 pinctrl-0 = <&qup_i2c10_default>;
1886 #address-cells = <1>;
1887 #size-cells = <0>;
1888 power-domains = <&rpmhpd SDM845_CX>;
1889 operating-points-v2 = <&qup_opp_table>;
1893 interconnect-names = "qup-core", "qup-config", "qup-memory";
1896 dma-names = "tx", "rx";
1901 compatible = "qcom,geni-spi";
1903 clock-names = "se";
1905 pinctrl-names = "default";
1906 pinctrl-0 = <&qup_spi10_default>;
1908 #address-cells = <1>;
1909 #size-cells = <0>;
1912 interconnect-names = "qup-core", "qup-config";
1915 dma-names = "tx", "rx";
1920 compatible = "qcom,geni-uart";
1922 clock-names = "se";
1924 pinctrl-names = "default";
1925 pinctrl-0 = <&qup_uart10_default>;
1927 power-domains = <&rpmhpd SDM845_CX>;
1928 operating-points-v2 = <&qup_opp_table>;
1931 interconnect-names = "qup-core", "qup-config";
1936 compatible = "qcom,geni-i2c";
1938 clock-names = "se";
1940 pinctrl-names = "default";
1941 pinctrl-0 = <&qup_i2c11_default>;
1943 #address-cells = <1>;
1944 #size-cells = <0>;
1945 power-domains = <&rpmhpd SDM845_CX>;
1946 operating-points-v2 = <&qup_opp_table>;
1950 interconnect-names = "qup-core", "qup-config", "qup-memory";
1953 dma-names = "tx", "rx";
1958 compatible = "qcom,geni-spi";
1960 clock-names = "se";
1962 pinctrl-names = "default";
1963 pinctrl-0 = <&qup_spi11_default>;
1965 #address-cells = <1>;
1966 #size-cells = <0>;
1969 interconnect-names = "qup-core", "qup-config";
1972 dma-names = "tx", "rx";
1977 compatible = "qcom,geni-uart";
1979 clock-names = "se";
1981 pinctrl-names = "default";
1982 pinctrl-0 = <&qup_uart11_default>;
1984 power-domains = <&rpmhpd SDM845_CX>;
1985 operating-points-v2 = <&qup_opp_table>;
1988 interconnect-names = "qup-core", "qup-config";
1993 compatible = "qcom,geni-i2c";
1995 clock-names = "se";
1997 pinctrl-names = "default";
1998 pinctrl-0 = <&qup_i2c12_default>;
2000 #address-cells = <1>;
2001 #size-cells = <0>;
2002 power-domains = <&rpmhpd SDM845_CX>;
2003 operating-points-v2 = <&qup_opp_table>;
2007 interconnect-names = "qup-core", "qup-config", "qup-memory";
2010 dma-names = "tx", "rx";
2015 compatible = "qcom,geni-spi";
2017 clock-names = "se";
2019 pinctrl-names = "default";
2020 pinctrl-0 = <&qup_spi12_default>;
2022 #address-cells = <1>;
2023 #size-cells = <0>;
2026 interconnect-names = "qup-core", "qup-config";
2029 dma-names = "tx", "rx";
2034 compatible = "qcom,geni-uart";
2036 clock-names = "se";
2038 pinctrl-names = "default";
2039 pinctrl-0 = <&qup_uart12_default>;
2041 power-domains = <&rpmhpd SDM845_CX>;
2042 operating-points-v2 = <&qup_opp_table>;
2045 interconnect-names = "qup-core", "qup-config";
2050 compatible = "qcom,geni-i2c";
2052 clock-names = "se";
2054 pinctrl-names = "default";
2055 pinctrl-0 = <&qup_i2c13_default>;
2057 #address-cells = <1>;
2058 #size-cells = <0>;
2059 power-domains = <&rpmhpd SDM845_CX>;
2060 operating-points-v2 = <&qup_opp_table>;
2064 interconnect-names = "qup-core", "qup-config", "qup-memory";
2067 dma-names = "tx", "rx";
2072 compatible = "qcom,geni-spi";
2074 clock-names = "se";
2076 pinctrl-names = "default";
2077 pinctrl-0 = <&qup_spi13_default>;
2079 #address-cells = <1>;
2080 #size-cells = <0>;
2083 interconnect-names = "qup-core", "qup-config";
2086 dma-names = "tx", "rx";
2091 compatible = "qcom,geni-uart";
2093 clock-names = "se";
2095 pinctrl-names = "default";
2096 pinctrl-0 = <&qup_uart13_default>;
2098 power-domains = <&rpmhpd SDM845_CX>;
2099 operating-points-v2 = <&qup_opp_table>;
2102 interconnect-names = "qup-core", "qup-config";
2107 compatible = "qcom,geni-i2c";
2109 clock-names = "se";
2111 pinctrl-names = "default";
2112 pinctrl-0 = <&qup_i2c14_default>;
2114 #address-cells = <1>;
2115 #size-cells = <0>;
2116 power-domains = <&rpmhpd SDM845_CX>;
2117 operating-points-v2 = <&qup_opp_table>;
2121 interconnect-names = "qup-core", "qup-config", "qup-memory";
2124 dma-names = "tx", "rx";
2129 compatible = "qcom,geni-spi";
2131 clock-names = "se";
2133 pinctrl-names = "default";
2134 pinctrl-0 = <&qup_spi14_default>;
2136 #address-cells = <1>;
2137 #size-cells = <0>;
2140 interconnect-names = "qup-core", "qup-config";
2143 dma-names = "tx", "rx";
2148 compatible = "qcom,geni-uart";
2150 clock-names = "se";
2152 pinctrl-names = "default";
2153 pinctrl-0 = <&qup_uart14_default>;
2155 power-domains = <&rpmhpd SDM845_CX>;
2156 operating-points-v2 = <&qup_opp_table>;
2159 interconnect-names = "qup-core", "qup-config";
2164 compatible = "qcom,geni-i2c";
2166 clock-names = "se";
2168 pinctrl-names = "default";
2169 pinctrl-0 = <&qup_i2c15_default>;
2171 #address-cells = <1>;
2172 #size-cells = <0>;
2173 power-domains = <&rpmhpd SDM845_CX>;
2174 operating-points-v2 = <&qup_opp_table>;
2179 interconnect-names = "qup-core", "qup-config", "qup-memory";
2182 dma-names = "tx", "rx";
2186 compatible = "qcom,geni-spi";
2188 clock-names = "se";
2190 pinctrl-names = "default";
2191 pinctrl-0 = <&qup_spi15_default>;
2193 #address-cells = <1>;
2194 #size-cells = <0>;
2197 interconnect-names = "qup-core", "qup-config";
2200 dma-names = "tx", "rx";
2205 compatible = "qcom,geni-uart";
2207 clock-names = "se";
2209 pinctrl-names = "default";
2210 pinctrl-0 = <&qup_uart15_default>;
2212 power-domains = <&rpmhpd SDM845_CX>;
2213 operating-points-v2 = <&qup_opp_table>;
2216 interconnect-names = "qup-core", "qup-config";
2221 llcc: system-cache-controller@1100000 {
2222 compatible = "qcom,sdm845-llcc";
2226 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2232 compatible = "qcom,sdm845-dcc", "qcom,dcc";
2238 compatible = "qcom,sdm845-llcc-bwmon";
2243 operating-points-v2 = <&llcc_bwmon_opp_table>;
2245 llcc_bwmon_opp_table: opp-table {
2246 compatible = "operating-points-v2";
2250 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2252 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2253 * bus width: 4 bytes) from msm-4.9 downstream
2256 opp-0 {
2257 opp-peak-kBps = <800000>;
2259 opp-1 {
2260 opp-peak-kBps = <1804000>;
2262 opp-2 {
2263 opp-peak-kBps = <3072000>;
2265 opp-3 {
2266 opp-peak-kBps = <5412000>;
2268 opp-4 {
2269 opp-peak-kBps = <7216000>;
2275 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2280 operating-points-v2 = <&cpu_bwmon_opp_table>;
2282 cpu_bwmon_opp_table: opp-table {
2283 compatible = "operating-points-v2";
2289 * from bandwidth table of qcom,cpu4-l3lat-mon
2290 * (qcom,core-dev-table, bus width: 16 bytes)
2291 * from msm-4.9 downstream kernel.
2293 opp-0 {
2294 opp-peak-kBps = <4800000>;
2296 opp-1 {
2297 opp-peak-kBps = <9216000>;
2299 opp-2 {
2300 opp-peak-kBps = <15052800>;
2302 opp-3 {
2303 opp-peak-kBps = <20889600>;
2305 opp-4 {
2306 opp-peak-kBps = <25497600>;
2312 compatible = "qcom,pcie-sdm845";
2318 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2320 linux,pci-domain = <0>;
2321 bus-range = <0x00 0xff>;
2322 num-lanes = <1>;
2324 #address-cells = <3>;
2325 #size-cells = <2>;
2331 interrupt-names = "msi";
2332 #interrupt-cells = <1>;
2333 interrupt-map-mask = <0 0 0 0x7>;
2334 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2346 clock-names = "pipe",
2354 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2372 reset-names = "pci";
2374 power-domains = <&gcc PCIE_0_GDSC>;
2377 phy-names = "pciephy";
2384 bus-range = <0x01 0xff>;
2386 #address-cells = <3>;
2387 #size-cells = <2>;
2393 compatible = "qcom,sdm845-qmp-pcie-phy";
2400 clock-names = "aux",
2406 clock-output-names = "pcie_0_pipe_clk";
2407 #clock-cells = <0>;
2409 #phy-cells = <0>;
2412 reset-names = "phy";
2414 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2415 assigned-clock-rates = <100000000>;
2421 compatible = "qcom,pcie-sdm845";
2427 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2429 linux,pci-domain = <1>;
2430 bus-range = <0x00 0xff>;
2431 num-lanes = <1>;
2433 #address-cells = <3>;
2434 #size-cells = <2>;
2440 interrupt-names = "msi";
2441 #interrupt-cells = <1>;
2442 interrupt-map-mask = <0 0 0 0x7>;
2443 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2456 clock-names = "pipe",
2465 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2466 assigned-clock-rates = <19200000>;
2468 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2486 reset-names = "pci";
2488 power-domains = <&gcc PCIE_1_GDSC>;
2491 phy-names = "pciephy";
2498 bus-range = <0x01 0xff>;
2500 #address-cells = <3>;
2501 #size-cells = <2>;
2507 compatible = "qcom,sdm845-qhp-pcie-phy";
2514 clock-names = "aux",
2520 clock-output-names = "pcie_1_pipe_clk";
2521 #clock-cells = <0>;
2523 #phy-cells = <0>;
2526 reset-names = "phy";
2528 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2529 assigned-clock-rates = <100000000>;
2535 compatible = "qcom,sdm845-mem-noc";
2537 #interconnect-cells = <2>;
2538 qcom,bcm-voters = <&apps_bcm_voter>;
2542 compatible = "qcom,sdm845-dc-noc";
2544 #interconnect-cells = <2>;
2545 qcom,bcm-voters = <&apps_bcm_voter>;
2549 compatible = "qcom,sdm845-config-noc";
2551 #interconnect-cells = <2>;
2552 qcom,bcm-voters = <&apps_bcm_voter>;
2556 compatible = "qcom,sdm845-system-noc";
2558 #interconnect-cells = <2>;
2559 qcom,bcm-voters = <&apps_bcm_voter>;
2563 compatible = "qcom,sdm845-aggre1-noc";
2565 #interconnect-cells = <2>;
2566 qcom,bcm-voters = <&apps_bcm_voter>;
2570 compatible = "qcom,sdm845-aggre2-noc";
2572 #interconnect-cells = <2>;
2573 qcom,bcm-voters = <&apps_bcm_voter>;
2577 compatible = "qcom,sdm845-mmss-noc";
2579 #interconnect-cells = <2>;
2580 qcom,bcm-voters = <&apps_bcm_voter>;
2584 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2585 "jedec,ufs-2.0";
2588 reg-names = "std", "ice";
2591 phy-names = "ufsphy";
2592 lanes-per-direction = <2>;
2593 power-domains = <&gcc UFS_PHY_GDSC>;
2594 #reset-cells = <1>;
2596 reset-names = "rst";
2600 clock-names =
2621 operating-points-v2 = <&ufs_opp_table>;
2625 interconnect-names = "ufs-ddr", "cpu-ufs";
2629 ufs_opp_table: opp-table {
2630 compatible = "operating-points-v2";
2632 opp-50000000 {
2633 opp-hz = /bits/ 64 <50000000>,
2642 required-opps = <&rpmhpd_opp_low_svs>;
2645 opp-200000000 {
2646 opp-hz = /bits/ 64 <200000000>,
2655 required-opps = <&rpmhpd_opp_nom>;
2661 compatible = "qcom,sdm845-qmp-ufs-phy";
2667 clock-names = "ref",
2671 power-domains = <&gcc UFS_PHY_GDSC>;
2674 reset-names = "ufsphy";
2676 #phy-cells = <0>;
2680 cryptobam: dma-controller@1dc4000 {
2681 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2685 clock-names = "bam_clk";
2686 #dma-cells = <1>;
2688 qcom,controlled-remotely;
2696 compatible = "qcom,crypto-v5.4";
2701 clock-names = "iface", "bus", "core";
2703 dma-names = "rx", "tx";
2711 compatible = "qcom,sdm845-ipa";
2718 reg-names = "ipa-reg",
2719 "ipa-shared",
2722 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2726 interrupt-names = "ipa",
2728 "ipa-clock-query",
2729 "ipa-setup-ready";
2732 clock-names = "core";
2737 interconnect-names = "memory",
2741 qcom,smem-states = <&ipa_smp2p_out 0>,
2743 qcom,smem-state-names = "ipa-clock-enabled-valid",
2744 "ipa-clock-enabled";
2750 compatible = "qcom,tcsr-mutex";
2752 #hwlock-cells = <1>;
2756 compatible = "qcom,sdm845-tcsr", "syscon";
2761 compatible = "qcom,sdm845-pinctrl";
2764 gpio-controller;
2765 #gpio-cells = <2>;
2766 interrupt-controller;
2767 #interrupt-cells = <2>;
2768 gpio-ranges = <&tlmm 0 0 151>;
2769 wakeup-parent = <&pdc_intc>;
2771 cci0_default: cci0-default-state {
2776 bias-pull-up;
2777 drive-strength = <2>; /* 2 mA */
2780 cci0_sleep: cci0-sleep-state {
2785 drive-strength = <2>; /* 2 mA */
2786 bias-pull-down;
2789 cci1_default: cci1-default-state {
2794 bias-pull-up;
2795 drive-strength = <2>; /* 2 mA */
2798 cci1_sleep: cci1-sleep-state {
2803 drive-strength = <2>; /* 2 mA */
2804 bias-pull-down;
2807 qspi_clk: qspi-clk-state {
2812 qspi_cs0: qspi-cs0-state {
2817 qspi_cs1: qspi-cs1-state {
2822 qspi_data0: qspi-data0-state {
2827 qspi_data1: qspi-data1-state {
2832 qspi_data23: qspi-data23-state {
2837 qup_i2c0_default: qup-i2c0-default-state {
2842 qup_i2c1_default: qup-i2c1-default-state {
2847 qup_i2c2_default: qup-i2c2-default-state {
2852 qup_i2c3_default: qup-i2c3-default-state {
2857 qup_i2c4_default: qup-i2c4-default-state {
2862 qup_i2c5_default: qup-i2c5-default-state {
2867 qup_i2c6_default: qup-i2c6-default-state {
2872 qup_i2c7_default: qup-i2c7-default-state {
2877 qup_i2c8_default: qup-i2c8-default-state {
2882 qup_i2c9_default: qup-i2c9-default-state {
2887 qup_i2c10_default: qup-i2c10-default-state {
2892 qup_i2c11_default: qup-i2c11-default-state {
2897 qup_i2c12_default: qup-i2c12-default-state {
2902 qup_i2c13_default: qup-i2c13-default-state {
2907 qup_i2c14_default: qup-i2c14-default-state {
2912 qup_i2c15_default: qup-i2c15-default-state {
2917 qup_spi0_default: qup-spi0-default-state {
2922 qup_spi1_default: qup-spi1-default-state {
2927 qup_spi2_default: qup-spi2-default-state {
2932 qup_spi3_default: qup-spi3-default-state {
2937 qup_spi4_default: qup-spi4-default-state {
2942 qup_spi5_default: qup-spi5-default-state {
2947 qup_spi6_default: qup-spi6-default-state {
2952 qup_spi7_default: qup-spi7-default-state {
2957 qup_spi8_default: qup-spi8-default-state {
2962 qup_spi9_default: qup-spi9-default-state {
2967 qup_spi10_default: qup-spi10-default-state {
2972 qup_spi11_default: qup-spi11-default-state {
2977 qup_spi12_default: qup-spi12-default-state {
2982 qup_spi13_default: qup-spi13-default-state {
2987 qup_spi14_default: qup-spi14-default-state {
2992 qup_spi15_default: qup-spi15-default-state {
2997 qup_uart0_default: qup-uart0-default-state {
2998 qup_uart0_tx: tx-pins {
3003 qup_uart0_rx: rx-pins {
3009 qup_uart1_default: qup-uart1-default-state {
3010 qup_uart1_tx: tx-pins {
3015 qup_uart1_rx: rx-pins {
3021 qup_uart2_default: qup-uart2-default-state {
3022 qup_uart2_tx: tx-pins {
3027 qup_uart2_rx: rx-pins {
3033 qup_uart3_default: qup-uart3-default-state {
3034 qup_uart3_tx: tx-pins {
3039 qup_uart3_rx: rx-pins {
3045 qup_uart3_4pin: qup-uart3-4pin-state {
3046 qup_uart3_4pin_cts: cts-pins {
3051 qup_uart3_4pin_rts_tx: rts-tx-pins {
3056 qup_uart3_4pin_rx: rx-pins {
3062 qup_uart4_default: qup-uart4-default-state {
3063 qup_uart4_tx: tx-pins {
3068 qup_uart4_rx: rx-pins {
3074 qup_uart5_default: qup-uart5-default-state {
3075 qup_uart5_tx: tx-pins {
3080 qup_uart5_rx: rx-pins {
3086 qup_uart6_default: qup-uart6-default-state {
3087 qup_uart6_tx: tx-pins {
3092 qup_uart6_rx: rx-pins {
3098 qup_uart6_4pin: qup-uart6-4pin-state {
3099 qup_uart6_4pin_cts: cts-pins {
3102 bias-pull-down;
3105 qup_uart6_4pin_rts_tx: rts-tx-pins {
3108 drive-strength = <2>;
3109 bias-disable;
3112 qup_uart6_4pin_rx: rx-pins {
3115 bias-pull-up;
3119 qup_uart7_default: qup-uart7-default-state {
3120 qup_uart7_tx: tx-pins {
3125 qup_uart7_rx: rx-pins {
3131 qup_uart8_default: qup-uart8-default-state {
3132 qup_uart8_tx: tx-pins {
3137 qup_uart8_rx: rx-pins {
3143 qup_uart9_default: qup-uart9-default-state {
3144 qup_uart9_tx: tx-pins {
3149 qup_uart9_rx: rx-pins {
3155 qup_uart10_default: qup-uart10-default-state {
3156 qup_uart10_tx: tx-pins {
3161 qup_uart10_rx: rx-pins {
3167 qup_uart11_default: qup-uart11-default-state {
3168 qup_uart11_tx: tx-pins {
3173 qup_uart11_rx: rx-pins {
3179 qup_uart12_default: qup-uart12-default-state {
3180 qup_uart12_tx: tx-pins {
3185 qup_uart12_rx: rx-pins {
3191 qup_uart13_default: qup-uart13-default-state {
3192 qup_uart13_tx: tx-pins {
3197 qup_uart13_rx: rx-pins {
3203 qup_uart14_default: qup-uart14-default-state {
3204 qup_uart14_tx: tx-pins {
3209 qup_uart14_rx: rx-pins {
3215 qup_uart15_default: qup-uart15-default-state {
3216 qup_uart15_tx: tx-pins {
3221 qup_uart15_rx: rx-pins {
3227 quat_mi2s_sleep: quat-mi2s-sleep-state {
3230 drive-strength = <2>;
3231 bias-pull-down;
3234 quat_mi2s_active: quat-mi2s-active-state {
3237 drive-strength = <8>;
3238 bias-disable;
3239 output-high;
3242 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3245 drive-strength = <2>;
3246 bias-pull-down;
3249 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3252 drive-strength = <8>;
3253 bias-disable;
3256 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3259 drive-strength = <2>;
3260 bias-pull-down;
3263 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3266 drive-strength = <8>;
3267 bias-disable;
3270 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3273 drive-strength = <2>;
3274 bias-pull-down;
3277 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3280 drive-strength = <8>;
3281 bias-disable;
3284 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3287 drive-strength = <2>;
3288 bias-pull-down;
3291 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3294 drive-strength = <8>;
3295 bias-disable;
3300 compatible = "qcom,sdm845-mss-pil";
3302 reg-names = "qdsp6", "rmb";
3304 interrupts-extended =
3311 interrupt-names = "wdog", "fatal", "ready",
3312 "handover", "stop-ack",
3313 "shutdown-ack";
3323 clock-names = "iface", "bus", "mem", "gpll0_mss",
3328 qcom,smem-states = <&modem_smp2p_out 0>;
3329 qcom,smem-state-names = "stop";
3333 reset-names = "mss_restart", "pdc_reset";
3335 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3337 power-domains = <&rpmhpd SDM845_CX>,
3340 power-domain-names = "cx", "mx", "mss";
3345 memory-region = <&mba_region>;
3349 memory-region = <&mpss_region>;
3353 memory-region = <&mdata_mem>;
3356 glink-edge {
3359 qcom,remote-pid = <1>;
3364 gpucc: clock-controller@5090000 {
3365 compatible = "qcom,sdm845-gpucc";
3367 #clock-cells = <1>;
3368 #reset-cells = <1>;
3369 #power-domain-cells = <1>;
3373 clock-names = "bi_tcxo",
3379 compatible = "qcom,sdm845-slpi-pas";
3382 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
3387 interrupt-names = "wdog", "fatal", "ready",
3388 "handover", "stop-ack";
3391 clock-names = "xo";
3395 power-domains = <&rpmhpd SDM845_LCX>,
3397 power-domain-names = "lcx", "lmx";
3399 memory-region = <&slpi_mem>;
3401 qcom,smem-states = <&slpi_smp2p_out 0>;
3402 qcom,smem-state-names = "stop";
3406 glink-edge {
3409 qcom,remote-pid = <3>;
3414 qcom,glink-channels = "fastrpcglink-apps-dsp";
3416 qcom,non-secure-domain;
3419 memory-region = <&fastrpc_mem>;
3420 #address-cells = <1>;
3421 #size-cells = <0>;
3423 compute-cb@0 {
3424 compatible = "qcom,fastrpc-compute-cb";
3432 compatible = "arm,coresight-stm", "arm,primecell";
3435 reg-names = "stm-base", "stm-stimulus-base";
3438 clock-names = "apb_pclk";
3440 out-ports {
3443 remote-endpoint =
3451 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3455 clock-names = "apb_pclk";
3457 out-ports {
3460 remote-endpoint =
3466 in-ports {
3467 #address-cells = <1>;
3468 #size-cells = <0>;
3473 remote-endpoint = <&stm_out>;
3480 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3484 clock-names = "apb_pclk";
3486 out-ports {
3489 remote-endpoint =
3495 in-ports {
3496 #address-cells = <1>;
3497 #size-cells = <0>;
3502 remote-endpoint =
3510 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3514 clock-names = "apb_pclk";
3516 out-ports {
3519 remote-endpoint = <&etf_in>;
3524 in-ports {
3525 #address-cells = <1>;
3526 #size-cells = <0>;
3531 remote-endpoint =
3539 remote-endpoint =
3547 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3551 clock-names = "apb_pclk";
3553 out-ports {
3556 remote-endpoint = <&etr_in>;
3561 in-ports {
3564 remote-endpoint = <&etf_out>;
3571 compatible = "arm,coresight-tmc", "arm,primecell";
3575 clock-names = "apb_pclk";
3577 out-ports {
3580 remote-endpoint =
3586 in-ports {
3590 remote-endpoint =
3598 compatible = "arm,coresight-tmc", "arm,primecell";
3602 clock-names = "apb_pclk";
3603 arm,scatter-gather;
3605 in-ports {
3608 remote-endpoint =
3616 compatible = "arm,coresight-etm4x", "arm,primecell";
3622 clock-names = "apb_pclk";
3623 arm,coresight-loses-context-with-cpu;
3625 out-ports {
3628 remote-endpoint =
3636 compatible = "arm,coresight-etm4x", "arm,primecell";
3642 clock-names = "apb_pclk";
3643 arm,coresight-loses-context-with-cpu;
3645 out-ports {
3648 remote-endpoint =
3656 compatible = "arm,coresight-etm4x", "arm,primecell";
3662 clock-names = "apb_pclk";
3663 arm,coresight-loses-context-with-cpu;
3665 out-ports {
3668 remote-endpoint =
3676 compatible = "arm,coresight-etm4x", "arm,primecell";
3682 clock-names = "apb_pclk";
3683 arm,coresight-loses-context-with-cpu;
3685 out-ports {
3688 remote-endpoint =
3696 compatible = "arm,coresight-etm4x", "arm,primecell";
3702 clock-names = "apb_pclk";
3703 arm,coresight-loses-context-with-cpu;
3705 out-ports {
3708 remote-endpoint =
3716 compatible = "arm,coresight-etm4x", "arm,primecell";
3722 clock-names = "apb_pclk";
3723 arm,coresight-loses-context-with-cpu;
3725 out-ports {
3728 remote-endpoint =
3736 compatible = "arm,coresight-etm4x", "arm,primecell";
3742 clock-names = "apb_pclk";
3743 arm,coresight-loses-context-with-cpu;
3745 out-ports {
3748 remote-endpoint =
3756 compatible = "arm,coresight-etm4x", "arm,primecell";
3762 clock-names = "apb_pclk";
3763 arm,coresight-loses-context-with-cpu;
3765 out-ports {
3768 remote-endpoint =
3776 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3780 clock-names = "apb_pclk";
3782 out-ports {
3785 remote-endpoint =
3791 in-ports {
3792 #address-cells = <1>;
3793 #size-cells = <0>;
3798 remote-endpoint =
3806 remote-endpoint =
3814 remote-endpoint =
3822 remote-endpoint =
3830 remote-endpoint =
3838 remote-endpoint =
3846 remote-endpoint =
3854 remote-endpoint =
3862 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3866 clock-names = "apb_pclk";
3868 out-ports {
3871 remote-endpoint =
3877 in-ports {
3880 remote-endpoint =
3888 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3893 interrupt-names = "hc_irq", "pwr_irq";
3898 clock-names = "iface", "core", "xo";
3900 power-domains = <&rpmhpd SDM845_CX>;
3901 operating-points-v2 = <&sdhc2_opp_table>;
3905 sdhc2_opp_table: opp-table {
3906 compatible = "operating-points-v2";
3908 opp-9600000 {
3909 opp-hz = /bits/ 64 <9600000>;
3910 required-opps = <&rpmhpd_opp_min_svs>;
3913 opp-19200000 {
3914 opp-hz = /bits/ 64 <19200000>;
3915 required-opps = <&rpmhpd_opp_low_svs>;
3918 opp-100000000 {
3919 opp-hz = /bits/ 64 <100000000>;
3920 required-opps = <&rpmhpd_opp_svs>;
3923 opp-201500000 {
3924 opp-hz = /bits/ 64 <201500000>;
3925 required-opps = <&rpmhpd_opp_svs_l1>;
3931 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3934 #address-cells = <1>;
3935 #size-cells = <0>;
3939 clock-names = "iface", "core";
3940 power-domains = <&rpmhpd SDM845_CX>;
3941 operating-points-v2 = <&qspi_opp_table>;
3945 slim: slim-ngd@171c0000 {
3946 compatible = "qcom,slim-ngd-v2.1.0";
3951 dma-names = "rx", "tx";
3954 #address-cells = <1>;
3955 #size-cells = <0>;
3960 compatible = "qcom,sdm845-lmh";
3964 qcom,lmh-temp-arm-millicelsius = <65000>;
3965 qcom,lmh-temp-low-millicelsius = <94500>;
3966 qcom,lmh-temp-high-millicelsius = <95000>;
3967 interrupt-controller;
3968 #interrupt-cells = <1>;
3972 compatible = "qcom,sdm845-lmh";
3976 qcom,lmh-temp-arm-millicelsius = <65000>;
3977 qcom,lmh-temp-low-millicelsius = <94500>;
3978 qcom,lmh-temp-high-millicelsius = <95000>;
3979 interrupt-controller;
3980 #interrupt-cells = <1>;
3984 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3987 #phy-cells = <0>;
3991 clock-names = "cfg_ahb", "ref";
3995 nvmem-cells = <&qusb2p_hstx_trim>;
3999 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
4002 #phy-cells = <0>;
4006 clock-names = "cfg_ahb", "ref";
4010 nvmem-cells = <&qusb2s_hstx_trim>;
4014 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
4023 clock-names = "aux",
4031 reset-names = "phy", "common";
4033 #clock-cells = <1>;
4034 #phy-cells = <1>;
4035 orientation-switch;
4038 #address-cells = <1>;
4039 #size-cells = <0>;
4052 remote-endpoint = <&usb_1_dwc3_ss>;
4060 remote-endpoint = <&dp_out>;
4067 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4075 clock-names = "aux",
4080 clock-output-names = "usb3_uni_phy_pipe_clk_src";
4081 #clock-cells = <0>;
4082 #phy-cells = <0>;
4086 reset-names = "phy",
4093 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4096 #address-cells = <2>;
4097 #size-cells = <2>;
4099 dma-ranges;
4106 clock-names = "cfg_noc",
4112 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4114 assigned-clock-rates = <19200000>, <150000000>;
4116 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4121 interrupt-names = "pwr_event",
4127 power-domains = <&gcc USB30_PRIM_GDSC>;
4133 interconnect-names = "usb-ddr", "apps-usb";
4142 snps,parkmode-disable-ss-quirk;
4143 snps,dis-u1-entry-quirk;
4144 snps,dis-u2-entry-quirk;
4146 phy-names = "usb2-phy", "usb3-phy";
4149 #address-cells = <1>;
4150 #size-cells = <0>;
4163 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
4171 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4174 #address-cells = <2>;
4175 #size-cells = <2>;
4177 dma-ranges;
4184 clock-names = "cfg_noc",
4190 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4192 assigned-clock-rates = <19200000>, <150000000>;
4194 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4199 interrupt-names = "pwr_event",
4205 power-domains = <&gcc USB30_SEC_GDSC>;
4211 interconnect-names = "usb-ddr", "apps-usb";
4220 snps,parkmode-disable-ss-quirk;
4221 snps,dis-u1-entry-quirk;
4222 snps,dis-u2-entry-quirk;
4224 phy-names = "usb2-phy", "usb3-phy";
4228 venus: video-codec@aa00000 {
4229 compatible = "qcom,sdm845-venus-v2";
4232 power-domains = <&videocc VENUS_GDSC>,
4236 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4237 operating-points-v2 = <&venus_opp_table>;
4245 clock-names = "core", "iface", "bus",
4250 memory-region = <&venus_mem>;
4253 interconnect-names = "video-mem", "cpu-cfg";
4257 video-core0 {
4258 compatible = "venus-decoder";
4261 video-core1 {
4262 compatible = "venus-encoder";
4265 venus_opp_table: opp-table {
4266 compatible = "operating-points-v2";
4268 opp-100000000 {
4269 opp-hz = /bits/ 64 <100000000>;
4270 required-opps = <&rpmhpd_opp_min_svs>;
4273 opp-200000000 {
4274 opp-hz = /bits/ 64 <200000000>;
4275 required-opps = <&rpmhpd_opp_low_svs>;
4278 opp-320000000 {
4279 opp-hz = /bits/ 64 <320000000>;
4280 required-opps = <&rpmhpd_opp_svs>;
4283 opp-380000000 {
4284 opp-hz = /bits/ 64 <380000000>;
4285 required-opps = <&rpmhpd_opp_svs_l1>;
4288 opp-444000000 {
4289 opp-hz = /bits/ 64 <444000000>;
4290 required-opps = <&rpmhpd_opp_nom>;
4293 opp-533000097 {
4294 opp-hz = /bits/ 64 <533000097>;
4295 required-opps = <&rpmhpd_opp_turbo>;
4300 videocc: clock-controller@ab00000 {
4301 compatible = "qcom,sdm845-videocc";
4304 clock-names = "bi_tcxo";
4305 #clock-cells = <1>;
4306 #power-domain-cells = <1>;
4307 #reset-cells = <1>;
4311 compatible = "qcom,sdm845-camss";
4323 reg-names = "csid0",
4344 interrupt-names = "csid0",
4355 power-domains = <&clock_camcc IFE_0_GDSC>,
4395 clock-names = "camnoc_axi",
4440 #address-cells = <1>;
4441 #size-cells = <0>;
4462 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
4463 #address-cells = <1>;
4464 #size-cells = <0>;
4468 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4476 clock-names = "camnoc_axi",
4483 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4485 assigned-clock-rates = <80000000>, <37500000>;
4487 pinctrl-names = "default", "sleep";
4488 pinctrl-0 = <&cci0_default &cci1_default>;
4489 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4493 cci_i2c0: i2c-bus@0 {
4495 clock-frequency = <1000000>;
4496 #address-cells = <1>;
4497 #size-cells = <0>;
4500 cci_i2c1: i2c-bus@1 {
4502 clock-frequency = <1000000>;
4503 #address-cells = <1>;
4504 #size-cells = <0>;
4508 clock_camcc: clock-controller@ad00000 {
4509 compatible = "qcom,sdm845-camcc";
4511 #clock-cells = <1>;
4512 #reset-cells = <1>;
4513 #power-domain-cells = <1>;
4515 clock-names = "bi_tcxo";
4518 mdss: display-subsystem@ae00000 {
4519 compatible = "qcom,sdm845-mdss";
4521 reg-names = "mdss";
4523 power-domains = <&dispcc MDSS_GDSC>;
4527 clock-names = "iface", "core";
4530 interrupt-controller;
4531 #interrupt-cells = <1>;
4535 interconnect-names = "mdp0-mem", "mdp1-mem";
4542 #address-cells = <2>;
4543 #size-cells = <2>;
4546 mdss_mdp: display-controller@ae01000 {
4547 compatible = "qcom,sdm845-dpu";
4550 reg-names = "mdp", "vbif";
4557 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4559 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4560 assigned-clock-rates = <19200000>;
4561 operating-points-v2 = <&mdp_opp_table>;
4562 power-domains = <&rpmhpd SDM845_CX>;
4564 interrupt-parent = <&mdss>;
4568 #address-cells = <1>;
4569 #size-cells = <0>;
4574 remote-endpoint = <&dp_in>;
4581 remote-endpoint = <&mdss_dsi0_in>;
4588 remote-endpoint = <&mdss_dsi1_in>;
4593 mdp_opp_table: opp-table {
4594 compatible = "operating-points-v2";
4596 opp-19200000 {
4597 opp-hz = /bits/ 64 <19200000>;
4598 required-opps = <&rpmhpd_opp_min_svs>;
4601 opp-171428571 {
4602 opp-hz = /bits/ 64 <171428571>;
4603 required-opps = <&rpmhpd_opp_low_svs>;
4606 opp-344000000 {
4607 opp-hz = /bits/ 64 <344000000>;
4608 required-opps = <&rpmhpd_opp_svs_l1>;
4611 opp-430000000 {
4612 opp-hz = /bits/ 64 <430000000>;
4613 required-opps = <&rpmhpd_opp_nom>;
4618 mdss_dp: displayport-controller@ae90000 {
4620 compatible = "qcom,sdm845-dp";
4628 interrupt-parent = <&mdss>;
4636 clock-names = "core_iface", "core_aux", "ctrl_link",
4638 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4640 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4643 phy-names = "dp";
4645 operating-points-v2 = <&dp_opp_table>;
4646 power-domains = <&rpmhpd SDM845_CX>;
4649 #address-cells = <1>;
4650 #size-cells = <0>;
4654 remote-endpoint = <&dpu_intf0_out>;
4661 remote-endpoint = <&usb_1_qmpphy_dp_in>;
4666 dp_opp_table: opp-table {
4667 compatible = "operating-points-v2";
4669 opp-162000000 {
4670 opp-hz = /bits/ 64 <162000000>;
4671 required-opps = <&rpmhpd_opp_low_svs>;
4674 opp-270000000 {
4675 opp-hz = /bits/ 64 <270000000>;
4676 required-opps = <&rpmhpd_opp_svs>;
4679 opp-540000000 {
4680 opp-hz = /bits/ 64 <540000000>;
4681 required-opps = <&rpmhpd_opp_svs_l1>;
4684 opp-810000000 {
4685 opp-hz = /bits/ 64 <810000000>;
4686 required-opps = <&rpmhpd_opp_nom>;
4692 compatible = "qcom,sdm845-dsi-ctrl",
4693 "qcom,mdss-dsi-ctrl";
4695 reg-names = "dsi_ctrl";
4697 interrupt-parent = <&mdss>;
4706 clock-names = "byte",
4712 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
4714 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
4717 operating-points-v2 = <&dsi_opp_table>;
4718 power-domains = <&rpmhpd SDM845_CX>;
4724 #address-cells = <1>;
4725 #size-cells = <0>;
4728 #address-cells = <1>;
4729 #size-cells = <0>;
4734 remote-endpoint = <&dpu_intf1_out>;
4747 compatible = "qcom,dsi-phy-10nm";
4751 reg-names = "dsi_phy",
4755 #clock-cells = <1>;
4756 #phy-cells = <0>;
4760 clock-names = "iface", "ref";
4766 compatible = "qcom,sdm845-dsi-ctrl",
4767 "qcom,mdss-dsi-ctrl";
4769 reg-names = "dsi_ctrl";
4771 interrupt-parent = <&mdss>;
4780 clock-names = "byte",
4786 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4788 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
4791 operating-points-v2 = <&dsi_opp_table>;
4792 power-domains = <&rpmhpd SDM845_CX>;
4798 #address-cells = <1>;
4799 #size-cells = <0>;
4802 #address-cells = <1>;
4803 #size-cells = <0>;
4808 remote-endpoint = <&dpu_intf2_out>;
4821 compatible = "qcom,dsi-phy-10nm";
4825 reg-names = "dsi_phy",
4829 #clock-cells = <1>;
4830 #phy-cells = <0>;
4834 clock-names = "iface", "ref";
4841 compatible = "qcom,adreno-630.2", "qcom,adreno";
4844 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4855 operating-points-v2 = <&gpu_opp_table>;
4858 #cooling-cells = <2>;
4861 interconnect-names = "gfx-mem";
4865 gpu_opp_table: opp-table {
4866 compatible = "operating-points-v2";
4868 opp-710000000 {
4869 opp-hz = /bits/ 64 <710000000>;
4870 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4871 opp-peak-kBps = <7216000>;
4874 opp-675000000 {
4875 opp-hz = /bits/ 64 <675000000>;
4876 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4877 opp-peak-kBps = <7216000>;
4880 opp-596000000 {
4881 opp-hz = /bits/ 64 <596000000>;
4882 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4883 opp-peak-kBps = <6220000>;
4886 opp-520000000 {
4887 opp-hz = /bits/ 64 <520000000>;
4888 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4889 opp-peak-kBps = <6220000>;
4892 opp-414000000 {
4893 opp-hz = /bits/ 64 <414000000>;
4894 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4895 opp-peak-kBps = <4068000>;
4898 opp-342000000 {
4899 opp-hz = /bits/ 64 <342000000>;
4900 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4901 opp-peak-kBps = <2724000>;
4904 opp-257000000 {
4905 opp-hz = /bits/ 64 <257000000>;
4906 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4907 opp-peak-kBps = <1648000>;
4913 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4915 #iommu-cells = <1>;
4916 #global-interrupts = <2>;
4929 clock-names = "bus", "iface";
4931 power-domains = <&gpucc GPU_CX_GDSC>;
4935 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4940 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4944 interrupt-names = "hfi", "gmu";
4950 clock-names = "gmu", "cxo", "axi", "memnoc";
4952 power-domains = <&gpucc GPU_CX_GDSC>,
4954 power-domain-names = "cx", "gx";
4958 operating-points-v2 = <&gmu_opp_table>;
4960 gmu_opp_table: opp-table {
4961 compatible = "operating-points-v2";
4963 opp-400000000 {
4964 opp-hz = /bits/ 64 <400000000>;
4965 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4968 opp-200000000 {
4969 opp-hz = /bits/ 64 <200000000>;
4970 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4975 dispcc: clock-controller@af00000 {
4976 compatible = "qcom,sdm845-dispcc";
4987 clock-names = "bi_tcxo",
4996 #clock-cells = <1>;
4997 #reset-cells = <1>;
4998 #power-domain-cells = <1>;
5001 pdc_intc: interrupt-controller@b220000 {
5002 compatible = "qcom,sdm845-pdc", "qcom,pdc";
5004 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
5005 #interrupt-cells = <2>;
5006 interrupt-parent = <&intc>;
5007 interrupt-controller;
5010 pdc_reset: reset-controller@b2e0000 {
5011 compatible = "qcom,sdm845-pdc-global";
5013 #reset-cells = <1>;
5016 tsens0: thermal-sensor@c263000 {
5017 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5023 interrupt-names = "uplow", "critical";
5024 #thermal-sensor-cells = <1>;
5027 tsens1: thermal-sensor@c265000 {
5028 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5034 interrupt-names = "uplow", "critical";
5035 #thermal-sensor-cells = <1>;
5038 aoss_reset: reset-controller@c2a0000 {
5039 compatible = "qcom,sdm845-aoss-cc";
5041 #reset-cells = <1>;
5044 aoss_qmp: power-management@c300000 {
5045 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
5050 #clock-cells = <0>;
5053 #cooling-cells = <2>;
5057 #cooling-cells = <2>;
5062 compatible = "qcom,sdm845-rpmh-stats";
5067 compatible = "qcom,spmi-pmic-arb";
5073 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5074 interrupt-names = "periph_irq";
5078 #address-cells = <2>;
5079 #size-cells = <0>;
5080 interrupt-controller;
5081 #interrupt-cells = <4>;
5085 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5088 #address-cells = <1>;
5089 #size-cells = <1>;
5093 pil-reloc@94c {
5094 compatible = "qcom,pil-reloc-info";
5100 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5102 #iommu-cells = <2>;
5103 #global-interrupts = <1>;
5172 compatible = "qcom,sdm845-tbu";
5176 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>;
5177 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
5181 compatible = "qcom,sdm845-tbu";
5185 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>;
5186 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
5190 compatible = "qcom,sdm845-tbu";
5194 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
5195 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
5199 compatible = "qcom,sdm845-tbu";
5203 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
5204 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
5208 compatible = "qcom,sdm845-tbu";
5212 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>;
5213 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
5217 compatible = "qcom,sdm845-tbu";
5221 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
5225 compatible = "qcom,sdm845-tbu";
5229 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>;
5230 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
5234 compatible = "qcom,sdm845-tbu";
5239 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
5240 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
5243 lpasscc: clock-controller@17014000 {
5244 compatible = "qcom,sdm845-lpasscc";
5246 reg-names = "cc", "qdsp6ss";
5247 #clock-cells = <1>;
5252 compatible = "qcom,sdm845-gladiator-noc";
5254 #interconnect-cells = <2>;
5255 qcom,bcm-voters = <&apps_bcm_voter>;
5259 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5266 compatible = "qcom,sdm845-apss-shared";
5268 #mbox-cells = <1>;
5272 compatible = "qcom,sdm845-rpmh-apps-rsc", "qcom,rpmh-rsc";
5277 reg-names = "drv-0", "drv-1", "drv-2";
5281 qcom,tcs-offset = <0xd00>;
5282 qcom,drv-id = <2>;
5283 qcom,tcs-config = <ACTIVE_TCS 2>,
5287 power-domains = <&cluster_pd>;
5289 apps_bcm_voter: bcm-voter {
5290 compatible = "qcom,bcm-voter";
5293 rpmhcc: clock-controller {
5294 compatible = "qcom,sdm845-rpmh-clk";
5295 #clock-cells = <1>;
5296 clock-names = "xo";
5300 rpmhpd: power-controller {
5301 compatible = "qcom,sdm845-rpmhpd";
5302 #power-domain-cells = <1>;
5303 operating-points-v2 = <&rpmhpd_opp_table>;
5305 rpmhpd_opp_table: opp-table {
5306 compatible = "operating-points-v2";
5309 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5313 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5317 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5321 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5325 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5329 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5333 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5337 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5341 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5345 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5351 intc: interrupt-controller@17a00000 {
5352 compatible = "arm,gic-v3";
5353 #address-cells = <2>;
5354 #size-cells = <2>;
5356 #interrupt-cells = <3>;
5357 interrupt-controller;
5362 msi-controller@17a40000 {
5363 compatible = "arm,gic-v3-its";
5364 msi-controller;
5365 #msi-cells = <1>;
5371 slimbam: dma-controller@17184000 {
5372 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5373 qcom,controlled-remotely;
5375 num-channels = <31>;
5377 #dma-cells = <1>;
5379 qcom,num-ees = <2>;
5384 #address-cells = <1>;
5385 #size-cells = <1>;
5387 compatible = "arm,armv7-timer-mem";
5391 frame-number = <0>;
5399 frame-number = <1>;
5406 frame-number = <2>;
5413 frame-number = <3>;
5420 frame-number = <4>;
5427 frame-number = <5>;
5434 frame-number = <6>;
5442 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5446 clock-names = "xo", "alternate";
5448 #interconnect-cells = <1>;
5452 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5454 reg-names = "freq-domain0", "freq-domain1";
5456 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5459 clock-names = "xo", "alternate";
5461 #freq-domain-cells = <1>;
5462 #clock-cells = <1>;
5466 compatible = "qcom,wcn3990-wifi";
5469 reg-names = "membase";
5470 memory-region = <&wlan_msa_mem>;
5471 clock-names = "cxo_ref_clk_pin";
5493 thermal-zones {
5494 cpu0-thermal {
5495 polling-delay-passive = <250>;
5497 thermal-sensors = <&tsens0 1>;
5500 cpu0_alert0: trip-point0 {
5506 cpu0_alert1: trip-point1 {
5512 cpu0_crit: cpu-crit {
5520 cpu1-thermal {
5521 polling-delay-passive = <250>;
5523 thermal-sensors = <&tsens0 2>;
5526 cpu1_alert0: trip-point0 {
5532 cpu1_alert1: trip-point1 {
5538 cpu1_crit: cpu-crit {
5546 cpu2-thermal {
5547 polling-delay-passive = <250>;
5549 thermal-sensors = <&tsens0 3>;
5552 cpu2_alert0: trip-point0 {
5558 cpu2_alert1: trip-point1 {
5564 cpu2_crit: cpu-crit {
5572 cpu3-thermal {
5573 polling-delay-passive = <250>;
5575 thermal-sensors = <&tsens0 4>;
5578 cpu3_alert0: trip-point0 {
5584 cpu3_alert1: trip-point1 {
5590 cpu3_crit: cpu-crit {
5598 cpu4-thermal {
5599 polling-delay-passive = <250>;
5601 thermal-sensors = <&tsens0 7>;
5604 cpu4_alert0: trip-point0 {
5610 cpu4_alert1: trip-point1 {
5616 cpu4_crit: cpu-crit {
5624 cpu5-thermal {
5625 polling-delay-passive = <250>;
5627 thermal-sensors = <&tsens0 8>;
5630 cpu5_alert0: trip-point0 {
5636 cpu5_alert1: trip-point1 {
5642 cpu5_crit: cpu-crit {
5650 cpu6-thermal {
5651 polling-delay-passive = <250>;
5653 thermal-sensors = <&tsens0 9>;
5656 cpu6_alert0: trip-point0 {
5662 cpu6_alert1: trip-point1 {
5668 cpu6_crit: cpu-crit {
5676 cpu7-thermal {
5677 polling-delay-passive = <250>;
5679 thermal-sensors = <&tsens0 10>;
5682 cpu7_alert0: trip-point0 {
5688 cpu7_alert1: trip-point1 {
5694 cpu7_crit: cpu-crit {
5702 aoss0-thermal {
5703 polling-delay-passive = <250>;
5705 thermal-sensors = <&tsens0 0>;
5708 aoss0_alert0: trip-point0 {
5716 cluster0-thermal {
5717 polling-delay-passive = <250>;
5719 thermal-sensors = <&tsens0 5>;
5722 cluster0_alert0: trip-point0 {
5727 cluster0_crit: cluster0-crit {
5735 cluster1-thermal {
5736 polling-delay-passive = <250>;
5738 thermal-sensors = <&tsens0 6>;
5741 cluster1_alert0: trip-point0 {
5746 cluster1_crit: cluster1-crit {
5754 gpu-top-thermal {
5755 polling-delay-passive = <250>;
5757 thermal-sensors = <&tsens0 11>;
5759 cooling-maps {
5762 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5767 gpu_top_alert0: trip-point0 {
5773 trip-point1 {
5779 trip-point2 {
5787 gpu-bottom-thermal {
5788 polling-delay-passive = <250>;
5790 thermal-sensors = <&tsens0 12>;
5792 cooling-maps {
5795 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5800 gpu_bottom_alert0: trip-point0 {
5806 trip-point1 {
5812 trip-point2 {
5820 aoss1-thermal {
5821 polling-delay-passive = <250>;
5823 thermal-sensors = <&tsens1 0>;
5826 aoss1_alert0: trip-point0 {
5834 q6-modem-thermal {
5835 polling-delay-passive = <250>;
5837 thermal-sensors = <&tsens1 1>;
5840 q6_modem_alert0: trip-point0 {
5848 mem-thermal {
5849 polling-delay-passive = <250>;
5851 thermal-sensors = <&tsens1 2>;
5854 mem_alert0: trip-point0 {
5862 wlan-thermal {
5863 polling-delay-passive = <250>;
5865 thermal-sensors = <&tsens1 3>;
5868 wlan_alert0: trip-point0 {
5876 q6-hvx-thermal {
5877 polling-delay-passive = <250>;
5879 thermal-sensors = <&tsens1 4>;
5882 q6_hvx_alert0: trip-point0 {
5890 camera-thermal {
5891 polling-delay-passive = <250>;
5893 thermal-sensors = <&tsens1 5>;
5896 camera_alert0: trip-point0 {
5904 video-thermal {
5905 polling-delay-passive = <250>;
5907 thermal-sensors = <&tsens1 6>;
5910 video_alert0: trip-point0 {
5918 modem-thermal {
5919 polling-delay-passive = <250>;
5921 thermal-sensors = <&tsens1 7>;
5924 modem_alert0: trip-point0 {
5934 compatible = "arm,armv8-timer";