Lines Matching +full:sdm845 +full:- +full:cpu +full:- +full:bwmon
1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h>
23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h>
33 interrupt-parent = <&intc>;
35 #address-cells = <2>;
36 #size-cells = <2>;
76 xo_board: xo-board {
77 compatible = "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <38400000>;
80 clock-output-names = "xo_board";
83 sleep_clk: sleep-clk {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <32764>;
91 #address-cells = <2>;
92 #size-cells = <0>;
94 CPU0: cpu@0 {
95 device_type = "cpu";
99 enable-method = "psci";
100 capacity-dmips-mhz = <611>;
101 dynamic-power-coefficient = <154>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = <&cpu0_opp_table>;
106 power-domains = <&CPU_PD0>;
107 power-domain-names = "psci";
108 #cooling-cells = <2>;
109 next-level-cache = <&L2_0>;
110 L2_0: l2-cache {
112 cache-level = <2>;
113 cache-unified;
114 next-level-cache = <&L3_0>;
115 L3_0: l3-cache {
117 cache-level = <3>;
118 cache-unified;
123 CPU1: cpu@100 {
124 device_type = "cpu";
128 enable-method = "psci";
129 capacity-dmips-mhz = <611>;
130 dynamic-power-coefficient = <154>;
131 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = <&cpu0_opp_table>;
135 power-domains = <&CPU_PD1>;
136 power-domain-names = "psci";
137 #cooling-cells = <2>;
138 next-level-cache = <&L2_100>;
139 L2_100: l2-cache {
141 cache-level = <2>;
142 cache-unified;
143 next-level-cache = <&L3_0>;
147 CPU2: cpu@200 {
148 device_type = "cpu";
152 enable-method = "psci";
153 capacity-dmips-mhz = <611>;
154 dynamic-power-coefficient = <154>;
155 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = <&cpu0_opp_table>;
159 power-domains = <&CPU_PD2>;
160 power-domain-names = "psci";
161 #cooling-cells = <2>;
162 next-level-cache = <&L2_200>;
163 L2_200: l2-cache {
165 cache-level = <2>;
166 cache-unified;
167 next-level-cache = <&L3_0>;
171 CPU3: cpu@300 {
172 device_type = "cpu";
176 enable-method = "psci";
177 capacity-dmips-mhz = <611>;
178 dynamic-power-coefficient = <154>;
179 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = <&cpu0_opp_table>;
183 #cooling-cells = <2>;
184 power-domains = <&CPU_PD3>;
185 power-domain-names = "psci";
186 next-level-cache = <&L2_300>;
187 L2_300: l2-cache {
189 cache-level = <2>;
190 cache-unified;
191 next-level-cache = <&L3_0>;
195 CPU4: cpu@400 {
196 device_type = "cpu";
200 enable-method = "psci";
201 capacity-dmips-mhz = <1024>;
202 dynamic-power-coefficient = <442>;
203 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = <&cpu4_opp_table>;
207 power-domains = <&CPU_PD4>;
208 power-domain-names = "psci";
209 #cooling-cells = <2>;
210 next-level-cache = <&L2_400>;
211 L2_400: l2-cache {
213 cache-level = <2>;
214 cache-unified;
215 next-level-cache = <&L3_0>;
219 CPU5: cpu@500 {
220 device_type = "cpu";
224 enable-method = "psci";
225 capacity-dmips-mhz = <1024>;
226 dynamic-power-coefficient = <442>;
227 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = <&cpu4_opp_table>;
231 power-domains = <&CPU_PD5>;
232 power-domain-names = "psci";
233 #cooling-cells = <2>;
234 next-level-cache = <&L2_500>;
235 L2_500: l2-cache {
237 cache-level = <2>;
238 cache-unified;
239 next-level-cache = <&L3_0>;
243 CPU6: cpu@600 {
244 device_type = "cpu";
248 enable-method = "psci";
249 capacity-dmips-mhz = <1024>;
250 dynamic-power-coefficient = <442>;
251 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = <&cpu4_opp_table>;
255 power-domains = <&CPU_PD6>;
256 power-domain-names = "psci";
257 #cooling-cells = <2>;
258 next-level-cache = <&L2_600>;
259 L2_600: l2-cache {
261 cache-level = <2>;
262 cache-unified;
263 next-level-cache = <&L3_0>;
267 CPU7: cpu@700 {
268 device_type = "cpu";
272 enable-method = "psci";
273 capacity-dmips-mhz = <1024>;
274 dynamic-power-coefficient = <442>;
275 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = <&cpu4_opp_table>;
279 power-domains = <&CPU_PD7>;
280 power-domain-names = "psci";
281 #cooling-cells = <2>;
282 next-level-cache = <&L2_700>;
283 L2_700: l2-cache {
285 cache-level = <2>;
286 cache-unified;
287 next-level-cache = <&L3_0>;
291 cpu-map {
294 cpu = <&CPU0>;
298 cpu = <&CPU1>;
302 cpu = <&CPU2>;
306 cpu = <&CPU3>;
310 cpu = <&CPU4>;
314 cpu = <&CPU5>;
318 cpu = <&CPU6>;
322 cpu = <&CPU7>;
327 cpu_idle_states: idle-states {
328 entry-method = "psci";
330 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = "arm,idle-state";
332 idle-state-name = "little-rail-power-collapse";
333 arm,psci-suspend-param = <0x40000004>;
334 entry-latency-us = <350>;
335 exit-latency-us = <461>;
336 min-residency-us = <1890>;
337 local-timer-stop;
340 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
341 compatible = "arm,idle-state";
342 idle-state-name = "big-rail-power-collapse";
343 arm,psci-suspend-param = <0x40000004>;
344 entry-latency-us = <264>;
345 exit-latency-us = <621>;
346 min-residency-us = <952>;
347 local-timer-stop;
351 domain-idle-states {
352 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = "domain-idle-state";
354 arm,psci-suspend-param = <0x4100c244>;
355 entry-latency-us = <3263>;
356 exit-latency-us = <6562>;
357 min-residency-us = <9987>;
364 compatible = "qcom,scm-sdm845", "qcom,scm";
374 cpu0_opp_table: opp-table-cpu0 {
375 compatible = "operating-points-v2";
376 opp-shared;
378 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <800000 4800000>;
383 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <800000 4800000>;
388 cpu0_opp3: opp-480000000 {
389 opp-hz = /bits/ 64 <480000000>;
390 opp-peak-kBps = <800000 6451200>;
393 cpu0_opp4: opp-576000000 {
394 opp-hz = /bits/ 64 <576000000>;
395 opp-peak-kBps = <800000 6451200>;
398 cpu0_opp5: opp-652800000 {
399 opp-hz = /bits/ 64 <652800000>;
400 opp-peak-kBps = <800000 7680000>;
403 cpu0_opp6: opp-748800000 {
404 opp-hz = /bits/ 64 <748800000>;
405 opp-peak-kBps = <1804000 9216000>;
408 cpu0_opp7: opp-825600000 {
409 opp-hz = /bits/ 64 <825600000>;
410 opp-peak-kBps = <1804000 9216000>;
413 cpu0_opp8: opp-902400000 {
414 opp-hz = /bits/ 64 <902400000>;
415 opp-peak-kBps = <1804000 10444800>;
418 cpu0_opp9: opp-979200000 {
419 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <1804000 11980800>;
423 cpu0_opp10: opp-1056000000 {
424 opp-hz = /bits/ 64 <1056000000>;
425 opp-peak-kBps = <1804000 11980800>;
428 cpu0_opp11: opp-1132800000 {
429 opp-hz = /bits/ 64 <1132800000>;
430 opp-peak-kBps = <2188000 13516800>;
433 cpu0_opp12: opp-1228800000 {
434 opp-hz = /bits/ 64 <1228800000>;
435 opp-peak-kBps = <2188000 15052800>;
438 cpu0_opp13: opp-1324800000 {
439 opp-hz = /bits/ 64 <1324800000>;
440 opp-peak-kBps = <2188000 16588800>;
443 cpu0_opp14: opp-1420800000 {
444 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <3072000 18124800>;
448 cpu0_opp15: opp-1516800000 {
449 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <3072000 19353600>;
453 cpu0_opp16: opp-1612800000 {
454 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <4068000 19353600>;
458 cpu0_opp17: opp-1689600000 {
459 opp-hz = /bits/ 64 <1689600000>;
460 opp-peak-kBps = <4068000 20889600>;
463 cpu0_opp18: opp-1766400000 {
464 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <4068000 22425600>;
469 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points-v2";
471 opp-shared;
473 cpu4_opp1: opp-300000000 {
474 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <800000 4800000>;
478 cpu4_opp2: opp-403200000 {
479 opp-hz = /bits/ 64 <403200000>;
480 opp-peak-kBps = <800000 4800000>;
483 cpu4_opp3: opp-480000000 {
484 opp-hz = /bits/ 64 <480000000>;
485 opp-peak-kBps = <1804000 4800000>;
488 cpu4_opp4: opp-576000000 {
489 opp-hz = /bits/ 64 <576000000>;
490 opp-peak-kBps = <1804000 4800000>;
493 cpu4_opp5: opp-652800000 {
494 opp-hz = /bits/ 64 <652800000>;
495 opp-peak-kBps = <1804000 4800000>;
498 cpu4_opp6: opp-748800000 {
499 opp-hz = /bits/ 64 <748800000>;
500 opp-peak-kBps = <1804000 4800000>;
503 cpu4_opp7: opp-825600000 {
504 opp-hz = /bits/ 64 <825600000>;
505 opp-peak-kBps = <2188000 9216000>;
508 cpu4_opp8: opp-902400000 {
509 opp-hz = /bits/ 64 <902400000>;
510 opp-peak-kBps = <2188000 9216000>;
513 cpu4_opp9: opp-979200000 {
514 opp-hz = /bits/ 64 <979200000>;
515 opp-peak-kBps = <2188000 9216000>;
518 cpu4_opp10: opp-1056000000 {
519 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <3072000 9216000>;
523 cpu4_opp11: opp-1132800000 {
524 opp-hz = /bits/ 64 <1132800000>;
525 opp-peak-kBps = <3072000 11980800>;
528 cpu4_opp12: opp-1209600000 {
529 opp-hz = /bits/ 64 <1209600000>;
530 opp-peak-kBps = <4068000 11980800>;
533 cpu4_opp13: opp-1286400000 {
534 opp-hz = /bits/ 64 <1286400000>;
535 opp-peak-kBps = <4068000 11980800>;
538 cpu4_opp14: opp-1363200000 {
539 opp-hz = /bits/ 64 <1363200000>;
540 opp-peak-kBps = <4068000 15052800>;
543 cpu4_opp15: opp-1459200000 {
544 opp-hz = /bits/ 64 <1459200000>;
545 opp-peak-kBps = <4068000 15052800>;
548 cpu4_opp16: opp-1536000000 {
549 opp-hz = /bits/ 64 <1536000000>;
550 opp-peak-kBps = <5412000 15052800>;
553 cpu4_opp17: opp-1612800000 {
554 opp-hz = /bits/ 64 <1612800000>;
555 opp-peak-kBps = <5412000 15052800>;
558 cpu4_opp18: opp-1689600000 {
559 opp-hz = /bits/ 64 <1689600000>;
560 opp-peak-kBps = <5412000 19353600>;
563 cpu4_opp19: opp-1766400000 {
564 opp-hz = /bits/ 64 <1766400000>;
565 opp-peak-kBps = <6220000 19353600>;
568 cpu4_opp20: opp-1843200000 {
569 opp-hz = /bits/ 64 <1843200000>;
570 opp-peak-kBps = <6220000 19353600>;
573 cpu4_opp21: opp-1920000000 {
574 opp-hz = /bits/ 64 <1920000000>;
575 opp-peak-kBps = <7216000 19353600>;
578 cpu4_opp22: opp-1996800000 {
579 opp-hz = /bits/ 64 <1996800000>;
580 opp-peak-kBps = <7216000 20889600>;
583 cpu4_opp23: opp-2092800000 {
584 opp-hz = /bits/ 64 <2092800000>;
585 opp-peak-kBps = <7216000 20889600>;
588 cpu4_opp24: opp-2169600000 {
589 opp-hz = /bits/ 64 <2169600000>;
590 opp-peak-kBps = <7216000 20889600>;
593 cpu4_opp25: opp-2246400000 {
594 opp-hz = /bits/ 64 <2246400000>;
595 opp-peak-kBps = <7216000 20889600>;
598 cpu4_opp26: opp-2323200000 {
599 opp-hz = /bits/ 64 <2323200000>;
600 opp-peak-kBps = <7216000 20889600>;
603 cpu4_opp27: opp-2400000000 {
604 opp-hz = /bits/ 64 <2400000000>;
605 opp-peak-kBps = <7216000 22425600>;
608 cpu4_opp28: opp-2476800000 {
609 opp-hz = /bits/ 64 <2476800000>;
610 opp-peak-kBps = <7216000 22425600>;
613 cpu4_opp29: opp-2553600000 {
614 opp-hz = /bits/ 64 <2553600000>;
615 opp-peak-kBps = <7216000 22425600>;
618 cpu4_opp30: opp-2649600000 {
619 opp-hz = /bits/ 64 <2649600000>;
620 opp-peak-kBps = <7216000 22425600>;
623 cpu4_opp31: opp-2745600000 {
624 opp-hz = /bits/ 64 <2745600000>;
625 opp-peak-kBps = <7216000 25497600>;
628 cpu4_opp32: opp-2803200000 {
629 opp-hz = /bits/ 64 <2803200000>;
630 opp-peak-kBps = <7216000 25497600>;
634 dsi_opp_table: opp-table-dsi {
635 compatible = "operating-points-v2";
637 opp-19200000 {
638 opp-hz = /bits/ 64 <19200000>;
639 required-opps = <&rpmhpd_opp_min_svs>;
642 opp-180000000 {
643 opp-hz = /bits/ 64 <180000000>;
644 required-opps = <&rpmhpd_opp_low_svs>;
647 opp-275000000 {
648 opp-hz = /bits/ 64 <275000000>;
649 required-opps = <&rpmhpd_opp_svs>;
652 opp-328580000 {
653 opp-hz = /bits/ 64 <328580000>;
654 required-opps = <&rpmhpd_opp_svs_l1>;
657 opp-358000000 {
658 opp-hz = /bits/ 64 <358000000>;
659 required-opps = <&rpmhpd_opp_nom>;
663 qspi_opp_table: opp-table-qspi {
664 compatible = "operating-points-v2";
666 opp-19200000 {
667 opp-hz = /bits/ 64 <19200000>;
668 required-opps = <&rpmhpd_opp_min_svs>;
671 opp-100000000 {
672 opp-hz = /bits/ 64 <100000000>;
673 required-opps = <&rpmhpd_opp_low_svs>;
676 opp-150000000 {
677 opp-hz = /bits/ 64 <150000000>;
678 required-opps = <&rpmhpd_opp_svs>;
681 opp-300000000 {
682 opp-hz = /bits/ 64 <300000000>;
683 required-opps = <&rpmhpd_opp_nom>;
687 qup_opp_table: opp-table-qup {
688 compatible = "operating-points-v2";
690 opp-50000000 {
691 opp-hz = /bits/ 64 <50000000>;
692 required-opps = <&rpmhpd_opp_min_svs>;
695 opp-75000000 {
696 opp-hz = /bits/ 64 <75000000>;
697 required-opps = <&rpmhpd_opp_low_svs>;
700 opp-100000000 {
701 opp-hz = /bits/ 64 <100000000>;
702 required-opps = <&rpmhpd_opp_svs>;
705 opp-128000000 {
706 opp-hz = /bits/ 64 <128000000>;
707 required-opps = <&rpmhpd_opp_nom>;
712 compatible = "arm,armv8-pmuv3";
717 compatible = "arm,psci-1.0";
720 CPU_PD0: power-domain-cpu0 {
721 #power-domain-cells = <0>;
722 power-domains = <&CLUSTER_PD>;
723 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
726 CPU_PD1: power-domain-cpu1 {
727 #power-domain-cells = <0>;
728 power-domains = <&CLUSTER_PD>;
729 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
732 CPU_PD2: power-domain-cpu2 {
733 #power-domain-cells = <0>;
734 power-domains = <&CLUSTER_PD>;
735 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
738 CPU_PD3: power-domain-cpu3 {
739 #power-domain-cells = <0>;
740 power-domains = <&CLUSTER_PD>;
741 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
744 CPU_PD4: power-domain-cpu4 {
745 #power-domain-cells = <0>;
746 power-domains = <&CLUSTER_PD>;
747 domain-idle-states = <&BIG_CPU_SLEEP_0>;
750 CPU_PD5: power-domain-cpu5 {
751 #power-domain-cells = <0>;
752 power-domains = <&CLUSTER_PD>;
753 domain-idle-states = <&BIG_CPU_SLEEP_0>;
756 CPU_PD6: power-domain-cpu6 {
757 #power-domain-cells = <0>;
758 power-domains = <&CLUSTER_PD>;
759 domain-idle-states = <&BIG_CPU_SLEEP_0>;
762 CPU_PD7: power-domain-cpu7 {
763 #power-domain-cells = <0>;
764 power-domains = <&CLUSTER_PD>;
765 domain-idle-states = <&BIG_CPU_SLEEP_0>;
768 CLUSTER_PD: power-domain-cluster {
769 #power-domain-cells = <0>;
770 domain-idle-states = <&CLUSTER_SLEEP_0>;
774 reserved-memory {
775 #address-cells = <2>;
776 #size-cells = <2>;
779 hyp_mem: hyp-mem@85700000 {
781 no-map;
784 xbl_mem: xbl-mem@85e00000 {
786 no-map;
789 aop_mem: aop-mem@85fc0000 {
791 no-map;
794 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
795 compatible = "qcom,cmd-db";
797 no-map;
803 no-map;
809 no-map;
813 compatible = "qcom,rmtfs-mem";
815 no-map;
817 qcom,client-id = <1>;
823 no-map;
826 camera_mem: camera-mem@8bf00000 {
828 no-map;
831 ipa_fw_mem: ipa-fw@8c400000 {
833 no-map;
836 ipa_gsi_mem: ipa-gsi@8c410000 {
838 no-map;
843 no-map;
848 no-map;
851 wlan_msa_mem: wlan-msa@8df00000 {
853 no-map;
858 no-map;
863 no-map;
868 no-map;
873 no-map;
878 no-map;
883 no-map;
886 mdata_mem: mpss-metadata {
887 alloc-ranges = <0 0xa0000000 0 0x20000000>;
889 no-map;
893 compatible = "shared-dma-pool";
894 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
901 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp-pas";
904 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
909 interrupt-names = "wdog", "fatal", "ready",
910 "handover", "stop-ack";
913 clock-names = "xo";
915 memory-region = <&adsp_mem>;
919 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop";
924 glink-edge {
927 qcom,remote-pid = <2>;
931 compatible = "qcom,apr-v2";
932 qcom,glink-channels = "apr_audio_svc";
934 #address-cells = <1>;
935 #size-cells = <0>;
941 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
947 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
949 compatible = "qcom,q6afe-dais";
950 #address-cells = <1>;
951 #size-cells = <0>;
952 #sound-dai-cells = <1>;
959 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
961 compatible = "qcom,q6asm-dais";
962 #address-cells = <1>;
963 #size-cells = <0>;
964 #sound-dai-cells = <1>;
972 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
974 compatible = "qcom,q6adm-routing";
975 #sound-dai-cells = <0>;
982 qcom,glink-channels = "fastrpcglink-apps-dsp";
984 qcom,non-secure-domain;
985 #address-cells = <1>;
986 #size-cells = <0>;
988 compute-cb@3 {
989 compatible = "qcom,fastrpc-compute-cb";
994 compute-cb@4 {
995 compatible = "qcom,fastrpc-compute-cb";
1003 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cdsp-pas";
1006 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1011 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", "stop-ack";
1015 clock-names = "xo";
1017 memory-region = <&cdsp_mem>;
1021 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop";
1026 glink-edge {
1029 qcom,remote-pid = <5>;
1033 qcom,glink-channels = "fastrpcglink-apps-dsp";
1035 qcom,non-secure-domain;
1036 #address-cells = <1>;
1037 #size-cells = <0>;
1039 compute-cb@1 {
1040 compatible = "qcom,fastrpc-compute-cb";
1045 compute-cb@2 {
1046 compatible = "qcom,fastrpc-compute-cb";
1051 compute-cb@3 {
1052 compatible = "qcom,fastrpc-compute-cb";
1057 compute-cb@4 {
1058 compatible = "qcom,fastrpc-compute-cb";
1063 compute-cb@5 {
1064 compatible = "qcom,fastrpc-compute-cb";
1069 compute-cb@6 {
1070 compatible = "qcom,fastrpc-compute-cb";
1075 compute-cb@7 {
1076 compatible = "qcom,fastrpc-compute-cb";
1081 compute-cb@8 {
1082 compatible = "qcom,fastrpc-compute-cb";
1090 smp2p-cdsp {
1098 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>;
1101 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cells = <1>;
1106 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "slave-kernel";
1109 interrupt-controller;
1110 #interrupt-cells = <2>;
1114 smp2p-lpass {
1122 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>;
1125 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cells = <1>;
1130 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "slave-kernel";
1133 interrupt-controller;
1134 #interrupt-cells = <2>;
1138 smp2p-mpss {
1143 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>;
1146 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cells = <1>;
1151 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "slave-kernel";
1153 interrupt-controller;
1154 #interrupt-cells = <2>;
1157 ipa_smp2p_out: ipa-ap-to-modem {
1158 qcom,entry-name = "ipa";
1159 #qcom,smem-state-cells = <1>;
1162 ipa_smp2p_in: ipa-modem-to-ap {
1163 qcom,entry-name = "ipa";
1164 interrupt-controller;
1165 #interrupt-cells = <2>;
1169 smp2p-slpi {
1174 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>;
1177 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cells = <1>;
1182 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "slave-kernel";
1184 interrupt-controller;
1185 #interrupt-cells = <2>;
1190 #address-cells = <2>;
1191 #size-cells = <2>;
1193 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus";
1196 gcc: clock-controller@100000 {
1197 compatible = "qcom,gcc-sdm845";
1204 clock-names = "bi_tcxo",
1209 #clock-cells = <1>;
1210 #reset-cells = <1>;
1211 #power-domain-cells = <1>;
1212 power-domains = <&rpmhpd SDM845_CX>;
1216 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1218 #address-cells = <1>;
1219 #size-cells = <1>;
1221 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1226 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1233 compatible = "qcom,prng-ee";
1236 clock-names = "core";
1239 gpi_dma0: dma-controller@800000 {
1240 #dma-cells = <3>;
1241 compatible = "qcom,sdm845-gpi-dma";
1256 dma-channels = <13>;
1257 dma-channel-mask = <0xfa>;
1263 compatible = "qcom,geni-se-qup";
1265 clock-names = "m-ahb", "s-ahb";
1269 #address-cells = <2>;
1270 #size-cells = <2>;
1273 interconnect-names = "qup-core";
1277 compatible = "qcom,geni-i2c";
1279 clock-names = "se";
1281 pinctrl-names = "default";
1282 pinctrl-0 = <&qup_i2c0_default>;
1284 #address-cells = <1>;
1285 #size-cells = <0>;
1286 power-domains = <&rpmhpd SDM845_CX>;
1287 operating-points-v2 = <&qup_opp_table>;
1291 interconnect-names = "qup-core", "qup-config", "qup-memory";
1294 dma-names = "tx", "rx";
1299 compatible = "qcom,geni-spi";
1301 clock-names = "se";
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_spi0_default>;
1306 #address-cells = <1>;
1307 #size-cells = <0>;
1310 interconnect-names = "qup-core", "qup-config";
1313 dma-names = "tx", "rx";
1318 compatible = "qcom,geni-uart";
1320 clock-names = "se";
1322 pinctrl-names = "default";
1323 pinctrl-0 = <&qup_uart0_default>;
1325 power-domains = <&rpmhpd SDM845_CX>;
1326 operating-points-v2 = <&qup_opp_table>;
1329 interconnect-names = "qup-core", "qup-config";
1334 compatible = "qcom,geni-i2c";
1336 clock-names = "se";
1338 pinctrl-names = "default";
1339 pinctrl-0 = <&qup_i2c1_default>;
1341 #address-cells = <1>;
1342 #size-cells = <0>;
1343 power-domains = <&rpmhpd SDM845_CX>;
1344 operating-points-v2 = <&qup_opp_table>;
1348 interconnect-names = "qup-core", "qup-config", "qup-memory";
1351 dma-names = "tx", "rx";
1356 compatible = "qcom,geni-spi";
1358 clock-names = "se";
1360 pinctrl-names = "default";
1361 pinctrl-0 = <&qup_spi1_default>;
1363 #address-cells = <1>;
1364 #size-cells = <0>;
1367 interconnect-names = "qup-core", "qup-config";
1370 dma-names = "tx", "rx";
1375 compatible = "qcom,geni-uart";
1377 clock-names = "se";
1379 pinctrl-names = "default";
1380 pinctrl-0 = <&qup_uart1_default>;
1382 power-domains = <&rpmhpd SDM845_CX>;
1383 operating-points-v2 = <&qup_opp_table>;
1386 interconnect-names = "qup-core", "qup-config";
1391 compatible = "qcom,geni-i2c";
1393 clock-names = "se";
1395 pinctrl-names = "default";
1396 pinctrl-0 = <&qup_i2c2_default>;
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1400 power-domains = <&rpmhpd SDM845_CX>;
1401 operating-points-v2 = <&qup_opp_table>;
1405 interconnect-names = "qup-core", "qup-config", "qup-memory";
1408 dma-names = "tx", "rx";
1413 compatible = "qcom,geni-spi";
1415 clock-names = "se";
1417 pinctrl-names = "default";
1418 pinctrl-0 = <&qup_spi2_default>;
1420 #address-cells = <1>;
1421 #size-cells = <0>;
1424 interconnect-names = "qup-core", "qup-config";
1427 dma-names = "tx", "rx";
1432 compatible = "qcom,geni-uart";
1434 clock-names = "se";
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&qup_uart2_default>;
1439 power-domains = <&rpmhpd SDM845_CX>;
1440 operating-points-v2 = <&qup_opp_table>;
1443 interconnect-names = "qup-core", "qup-config";
1448 compatible = "qcom,geni-i2c";
1450 clock-names = "se";
1452 pinctrl-names = "default";
1453 pinctrl-0 = <&qup_i2c3_default>;
1455 #address-cells = <1>;
1456 #size-cells = <0>;
1457 power-domains = <&rpmhpd SDM845_CX>;
1458 operating-points-v2 = <&qup_opp_table>;
1462 interconnect-names = "qup-core", "qup-config", "qup-memory";
1465 dma-names = "tx", "rx";
1470 compatible = "qcom,geni-spi";
1472 clock-names = "se";
1474 pinctrl-names = "default";
1475 pinctrl-0 = <&qup_spi3_default>;
1477 #address-cells = <1>;
1478 #size-cells = <0>;
1481 interconnect-names = "qup-core", "qup-config";
1484 dma-names = "tx", "rx";
1489 compatible = "qcom,geni-uart";
1491 clock-names = "se";
1493 pinctrl-names = "default";
1494 pinctrl-0 = <&qup_uart3_default>;
1496 power-domains = <&rpmhpd SDM845_CX>;
1497 operating-points-v2 = <&qup_opp_table>;
1500 interconnect-names = "qup-core", "qup-config";
1505 compatible = "qcom,geni-i2c";
1507 clock-names = "se";
1509 pinctrl-names = "default";
1510 pinctrl-0 = <&qup_i2c4_default>;
1512 #address-cells = <1>;
1513 #size-cells = <0>;
1514 power-domains = <&rpmhpd SDM845_CX>;
1515 operating-points-v2 = <&qup_opp_table>;
1519 interconnect-names = "qup-core", "qup-config", "qup-memory";
1522 dma-names = "tx", "rx";
1527 compatible = "qcom,geni-spi";
1529 clock-names = "se";
1531 pinctrl-names = "default";
1532 pinctrl-0 = <&qup_spi4_default>;
1534 #address-cells = <1>;
1535 #size-cells = <0>;
1538 interconnect-names = "qup-core", "qup-config";
1541 dma-names = "tx", "rx";
1546 compatible = "qcom,geni-uart";
1548 clock-names = "se";
1550 pinctrl-names = "default";
1551 pinctrl-0 = <&qup_uart4_default>;
1553 power-domains = <&rpmhpd SDM845_CX>;
1554 operating-points-v2 = <&qup_opp_table>;
1557 interconnect-names = "qup-core", "qup-config";
1562 compatible = "qcom,geni-i2c";
1564 clock-names = "se";
1566 pinctrl-names = "default";
1567 pinctrl-0 = <&qup_i2c5_default>;
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1571 power-domains = <&rpmhpd SDM845_CX>;
1572 operating-points-v2 = <&qup_opp_table>;
1576 interconnect-names = "qup-core", "qup-config", "qup-memory";
1579 dma-names = "tx", "rx";
1584 compatible = "qcom,geni-spi";
1586 clock-names = "se";
1588 pinctrl-names = "default";
1589 pinctrl-0 = <&qup_spi5_default>;
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1595 interconnect-names = "qup-core", "qup-config";
1598 dma-names = "tx", "rx";
1603 compatible = "qcom,geni-uart";
1605 clock-names = "se";
1607 pinctrl-names = "default";
1608 pinctrl-0 = <&qup_uart5_default>;
1610 power-domains = <&rpmhpd SDM845_CX>;
1611 operating-points-v2 = <&qup_opp_table>;
1614 interconnect-names = "qup-core", "qup-config";
1619 compatible = "qcom,geni-i2c";
1621 clock-names = "se";
1623 pinctrl-names = "default";
1624 pinctrl-0 = <&qup_i2c6_default>;
1626 #address-cells = <1>;
1627 #size-cells = <0>;
1628 power-domains = <&rpmhpd SDM845_CX>;
1629 operating-points-v2 = <&qup_opp_table>;
1633 interconnect-names = "qup-core", "qup-config", "qup-memory";
1636 dma-names = "tx", "rx";
1641 compatible = "qcom,geni-spi";
1643 clock-names = "se";
1645 pinctrl-names = "default";
1646 pinctrl-0 = <&qup_spi6_default>;
1648 #address-cells = <1>;
1649 #size-cells = <0>;
1652 interconnect-names = "qup-core", "qup-config";
1655 dma-names = "tx", "rx";
1660 compatible = "qcom,geni-uart";
1662 clock-names = "se";
1664 pinctrl-names = "default";
1665 pinctrl-0 = <&qup_uart6_default>;
1667 power-domains = <&rpmhpd SDM845_CX>;
1668 operating-points-v2 = <&qup_opp_table>;
1671 interconnect-names = "qup-core", "qup-config";
1676 compatible = "qcom,geni-i2c";
1678 clock-names = "se";
1680 pinctrl-names = "default";
1681 pinctrl-0 = <&qup_i2c7_default>;
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1685 power-domains = <&rpmhpd SDM845_CX>;
1686 operating-points-v2 = <&qup_opp_table>;
1691 compatible = "qcom,geni-spi";
1693 clock-names = "se";
1695 pinctrl-names = "default";
1696 pinctrl-0 = <&qup_spi7_default>;
1698 #address-cells = <1>;
1699 #size-cells = <0>;
1702 interconnect-names = "qup-core", "qup-config";
1705 dma-names = "tx", "rx";
1710 compatible = "qcom,geni-uart";
1712 clock-names = "se";
1714 pinctrl-names = "default";
1715 pinctrl-0 = <&qup_uart7_default>;
1717 power-domains = <&rpmhpd SDM845_CX>;
1718 operating-points-v2 = <&qup_opp_table>;
1721 interconnect-names = "qup-core", "qup-config";
1726 gpi_dma1: dma-controller@a00000 {
1727 #dma-cells = <3>;
1728 compatible = "qcom,sdm845-gpi-dma";
1743 dma-channels = <13>;
1744 dma-channel-mask = <0xfa>;
1750 compatible = "qcom,geni-se-qup";
1752 clock-names = "m-ahb", "s-ahb";
1756 #address-cells = <2>;
1757 #size-cells = <2>;
1760 interconnect-names = "qup-core";
1764 compatible = "qcom,geni-i2c";
1766 clock-names = "se";
1768 pinctrl-names = "default";
1769 pinctrl-0 = <&qup_i2c8_default>;
1771 #address-cells = <1>;
1772 #size-cells = <0>;
1773 power-domains = <&rpmhpd SDM845_CX>;
1774 operating-points-v2 = <&qup_opp_table>;
1778 interconnect-names = "qup-core", "qup-config", "qup-memory";
1781 dma-names = "tx", "rx";
1786 compatible = "qcom,geni-spi";
1788 clock-names = "se";
1790 pinctrl-names = "default";
1791 pinctrl-0 = <&qup_spi8_default>;
1793 #address-cells = <1>;
1794 #size-cells = <0>;
1797 interconnect-names = "qup-core", "qup-config";
1800 dma-names = "tx", "rx";
1805 compatible = "qcom,geni-uart";
1807 clock-names = "se";
1809 pinctrl-names = "default";
1810 pinctrl-0 = <&qup_uart8_default>;
1812 power-domains = <&rpmhpd SDM845_CX>;
1813 operating-points-v2 = <&qup_opp_table>;
1816 interconnect-names = "qup-core", "qup-config";
1821 compatible = "qcom,geni-i2c";
1823 clock-names = "se";
1825 pinctrl-names = "default";
1826 pinctrl-0 = <&qup_i2c9_default>;
1828 #address-cells = <1>;
1829 #size-cells = <0>;
1830 power-domains = <&rpmhpd SDM845_CX>;
1831 operating-points-v2 = <&qup_opp_table>;
1835 interconnect-names = "qup-core", "qup-config", "qup-memory";
1838 dma-names = "tx", "rx";
1843 compatible = "qcom,geni-spi";
1845 clock-names = "se";
1847 pinctrl-names = "default";
1848 pinctrl-0 = <&qup_spi9_default>;
1850 #address-cells = <1>;
1851 #size-cells = <0>;
1854 interconnect-names = "qup-core", "qup-config";
1857 dma-names = "tx", "rx";
1862 compatible = "qcom,geni-debug-uart";
1864 clock-names = "se";
1866 pinctrl-names = "default";
1867 pinctrl-0 = <&qup_uart9_default>;
1869 power-domains = <&rpmhpd SDM845_CX>;
1870 operating-points-v2 = <&qup_opp_table>;
1873 interconnect-names = "qup-core", "qup-config";
1878 compatible = "qcom,geni-i2c";
1880 clock-names = "se";
1882 pinctrl-names = "default";
1883 pinctrl-0 = <&qup_i2c10_default>;
1885 #address-cells = <1>;
1886 #size-cells = <0>;
1887 power-domains = <&rpmhpd SDM845_CX>;
1888 operating-points-v2 = <&qup_opp_table>;
1892 interconnect-names = "qup-core", "qup-config", "qup-memory";
1895 dma-names = "tx", "rx";
1900 compatible = "qcom,geni-spi";
1902 clock-names = "se";
1904 pinctrl-names = "default";
1905 pinctrl-0 = <&qup_spi10_default>;
1907 #address-cells = <1>;
1908 #size-cells = <0>;
1911 interconnect-names = "qup-core", "qup-config";
1914 dma-names = "tx", "rx";
1919 compatible = "qcom,geni-uart";
1921 clock-names = "se";
1923 pinctrl-names = "default";
1924 pinctrl-0 = <&qup_uart10_default>;
1926 power-domains = <&rpmhpd SDM845_CX>;
1927 operating-points-v2 = <&qup_opp_table>;
1930 interconnect-names = "qup-core", "qup-config";
1935 compatible = "qcom,geni-i2c";
1937 clock-names = "se";
1939 pinctrl-names = "default";
1940 pinctrl-0 = <&qup_i2c11_default>;
1942 #address-cells = <1>;
1943 #size-cells = <0>;
1944 power-domains = <&rpmhpd SDM845_CX>;
1945 operating-points-v2 = <&qup_opp_table>;
1949 interconnect-names = "qup-core", "qup-config", "qup-memory";
1952 dma-names = "tx", "rx";
1957 compatible = "qcom,geni-spi";
1959 clock-names = "se";
1961 pinctrl-names = "default";
1962 pinctrl-0 = <&qup_spi11_default>;
1964 #address-cells = <1>;
1965 #size-cells = <0>;
1968 interconnect-names = "qup-core", "qup-config";
1971 dma-names = "tx", "rx";
1976 compatible = "qcom,geni-uart";
1978 clock-names = "se";
1980 pinctrl-names = "default";
1981 pinctrl-0 = <&qup_uart11_default>;
1983 power-domains = <&rpmhpd SDM845_CX>;
1984 operating-points-v2 = <&qup_opp_table>;
1987 interconnect-names = "qup-core", "qup-config";
1992 compatible = "qcom,geni-i2c";
1994 clock-names = "se";
1996 pinctrl-names = "default";
1997 pinctrl-0 = <&qup_i2c12_default>;
1999 #address-cells = <1>;
2000 #size-cells = <0>;
2001 power-domains = <&rpmhpd SDM845_CX>;
2002 operating-points-v2 = <&qup_opp_table>;
2006 interconnect-names = "qup-core", "qup-config", "qup-memory";
2009 dma-names = "tx", "rx";
2014 compatible = "qcom,geni-spi";
2016 clock-names = "se";
2018 pinctrl-names = "default";
2019 pinctrl-0 = <&qup_spi12_default>;
2021 #address-cells = <1>;
2022 #size-cells = <0>;
2025 interconnect-names = "qup-core", "qup-config";
2028 dma-names = "tx", "rx";
2033 compatible = "qcom,geni-uart";
2035 clock-names = "se";
2037 pinctrl-names = "default";
2038 pinctrl-0 = <&qup_uart12_default>;
2040 power-domains = <&rpmhpd SDM845_CX>;
2041 operating-points-v2 = <&qup_opp_table>;
2044 interconnect-names = "qup-core", "qup-config";
2049 compatible = "qcom,geni-i2c";
2051 clock-names = "se";
2053 pinctrl-names = "default";
2054 pinctrl-0 = <&qup_i2c13_default>;
2056 #address-cells = <1>;
2057 #size-cells = <0>;
2058 power-domains = <&rpmhpd SDM845_CX>;
2059 operating-points-v2 = <&qup_opp_table>;
2063 interconnect-names = "qup-core", "qup-config", "qup-memory";
2066 dma-names = "tx", "rx";
2071 compatible = "qcom,geni-spi";
2073 clock-names = "se";
2075 pinctrl-names = "default";
2076 pinctrl-0 = <&qup_spi13_default>;
2078 #address-cells = <1>;
2079 #size-cells = <0>;
2082 interconnect-names = "qup-core", "qup-config";
2085 dma-names = "tx", "rx";
2090 compatible = "qcom,geni-uart";
2092 clock-names = "se";
2094 pinctrl-names = "default";
2095 pinctrl-0 = <&qup_uart13_default>;
2097 power-domains = <&rpmhpd SDM845_CX>;
2098 operating-points-v2 = <&qup_opp_table>;
2101 interconnect-names = "qup-core", "qup-config";
2106 compatible = "qcom,geni-i2c";
2108 clock-names = "se";
2110 pinctrl-names = "default";
2111 pinctrl-0 = <&qup_i2c14_default>;
2113 #address-cells = <1>;
2114 #size-cells = <0>;
2115 power-domains = <&rpmhpd SDM845_CX>;
2116 operating-points-v2 = <&qup_opp_table>;
2120 interconnect-names = "qup-core", "qup-config", "qup-memory";
2123 dma-names = "tx", "rx";
2128 compatible = "qcom,geni-spi";
2130 clock-names = "se";
2132 pinctrl-names = "default";
2133 pinctrl-0 = <&qup_spi14_default>;
2135 #address-cells = <1>;
2136 #size-cells = <0>;
2139 interconnect-names = "qup-core", "qup-config";
2142 dma-names = "tx", "rx";
2147 compatible = "qcom,geni-uart";
2149 clock-names = "se";
2151 pinctrl-names = "default";
2152 pinctrl-0 = <&qup_uart14_default>;
2154 power-domains = <&rpmhpd SDM845_CX>;
2155 operating-points-v2 = <&qup_opp_table>;
2158 interconnect-names = "qup-core", "qup-config";
2163 compatible = "qcom,geni-i2c";
2165 clock-names = "se";
2167 pinctrl-names = "default";
2168 pinctrl-0 = <&qup_i2c15_default>;
2170 #address-cells = <1>;
2171 #size-cells = <0>;
2172 power-domains = <&rpmhpd SDM845_CX>;
2173 operating-points-v2 = <&qup_opp_table>;
2178 interconnect-names = "qup-core", "qup-config", "qup-memory";
2181 dma-names = "tx", "rx";
2185 compatible = "qcom,geni-spi";
2187 clock-names = "se";
2189 pinctrl-names = "default";
2190 pinctrl-0 = <&qup_spi15_default>;
2192 #address-cells = <1>;
2193 #size-cells = <0>;
2196 interconnect-names = "qup-core", "qup-config";
2199 dma-names = "tx", "rx";
2204 compatible = "qcom,geni-uart";
2206 clock-names = "se";
2208 pinctrl-names = "default";
2209 pinctrl-0 = <&qup_uart15_default>;
2211 power-domains = <&rpmhpd SDM845_CX>;
2212 operating-points-v2 = <&qup_opp_table>;
2215 interconnect-names = "qup-core", "qup-config";
2220 llcc: system-cache-controller@1100000 {
2221 compatible = "qcom,sdm845-llcc";
2225 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2231 compatible = "qcom,sdm845-dcc", "qcom,dcc";
2237 compatible = "qcom,sdm845-llcc-bwmon";
2242 operating-points-v2 = <&llcc_bwmon_opp_table>;
2244 llcc_bwmon_opp_table: opp-table {
2245 compatible = "operating-points-v2";
2249 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2251 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2252 * bus width: 4 bytes) from msm-4.9 downstream
2255 opp-0 {
2256 opp-peak-kBps = <800000>;
2258 opp-1 {
2259 opp-peak-kBps = <1804000>;
2261 opp-2 {
2262 opp-peak-kBps = <3072000>;
2264 opp-3 {
2265 opp-peak-kBps = <5412000>;
2267 opp-4 {
2268 opp-peak-kBps = <7216000>;
2274 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2279 operating-points-v2 = <&cpu_bwmon_opp_table>;
2281 cpu_bwmon_opp_table: opp-table {
2282 compatible = "operating-points-v2";
2288 * from bandwidth table of qcom,cpu4-l3lat-mon
2289 * (qcom,core-dev-table, bus width: 16 bytes)
2290 * from msm-4.9 downstream kernel.
2292 opp-0 {
2293 opp-peak-kBps = <4800000>;
2295 opp-1 {
2296 opp-peak-kBps = <9216000>;
2298 opp-2 {
2299 opp-peak-kBps = <15052800>;
2301 opp-3 {
2302 opp-peak-kBps = <20889600>;
2304 opp-4 {
2305 opp-peak-kBps = <25497600>;
2311 compatible = "qcom,pcie-sdm845";
2317 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2319 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xff>;
2321 num-lanes = <1>;
2323 #address-cells = <3>;
2324 #size-cells = <2>;
2330 interrupt-names = "msi";
2331 #interrupt-cells = <1>;
2332 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2345 clock-names = "pipe",
2353 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2371 reset-names = "pci";
2373 power-domains = <&gcc PCIE_0_GDSC>;
2376 phy-names = "pciephy";
2383 bus-range = <0x01 0xff>;
2385 #address-cells = <3>;
2386 #size-cells = <2>;
2392 compatible = "qcom,sdm845-qmp-pcie-phy";
2399 clock-names = "aux",
2405 clock-output-names = "pcie_0_pipe_clk";
2406 #clock-cells = <0>;
2408 #phy-cells = <0>;
2411 reset-names = "phy";
2413 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414 assigned-clock-rates = <100000000>;
2420 compatible = "qcom,pcie-sdm845";
2426 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2428 linux,pci-domain = <1>;
2429 bus-range = <0x00 0xff>;
2430 num-lanes = <1>;
2432 #address-cells = <3>;
2433 #size-cells = <2>;
2439 interrupt-names = "msi";
2440 #interrupt-cells = <1>;
2441 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2455 clock-names = "pipe",
2464 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465 assigned-clock-rates = <19200000>;
2467 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2485 reset-names = "pci";
2487 power-domains = <&gcc PCIE_1_GDSC>;
2490 phy-names = "pciephy";
2497 bus-range = <0x01 0xff>;
2499 #address-cells = <3>;
2500 #size-cells = <2>;
2506 compatible = "qcom,sdm845-qhp-pcie-phy";
2513 clock-names = "aux",
2519 clock-output-names = "pcie_1_pipe_clk";
2520 #clock-cells = <0>;
2522 #phy-cells = <0>;
2525 reset-names = "phy";
2527 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528 assigned-clock-rates = <100000000>;
2534 compatible = "qcom,sdm845-mem-noc";
2536 #interconnect-cells = <2>;
2537 qcom,bcm-voters = <&apps_bcm_voter>;
2541 compatible = "qcom,sdm845-dc-noc";
2543 #interconnect-cells = <2>;
2544 qcom,bcm-voters = <&apps_bcm_voter>;
2548 compatible = "qcom,sdm845-config-noc";
2550 #interconnect-cells = <2>;
2551 qcom,bcm-voters = <&apps_bcm_voter>;
2555 compatible = "qcom,sdm845-system-noc";
2557 #interconnect-cells = <2>;
2558 qcom,bcm-voters = <&apps_bcm_voter>;
2562 compatible = "qcom,sdm845-aggre1-noc";
2564 #interconnect-cells = <2>;
2565 qcom,bcm-voters = <&apps_bcm_voter>;
2569 compatible = "qcom,sdm845-aggre2-noc";
2571 #interconnect-cells = <2>;
2572 qcom,bcm-voters = <&apps_bcm_voter>;
2576 compatible = "qcom,sdm845-mmss-noc";
2578 #interconnect-cells = <2>;
2579 qcom,bcm-voters = <&apps_bcm_voter>;
2583 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,ufs-2.0";
2587 reg-names = "std", "ice";
2590 phy-names = "ufsphy";
2591 lanes-per-direction = <2>;
2592 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>;
2595 reset-names = "rst";
2599 clock-names =
2620 operating-points-v2 = <&ufs_opp_table>;
2624 interconnect-names = "ufs-ddr", "cpu-ufs";
2628 ufs_opp_table: opp-table {
2629 compatible = "operating-points-v2";
2631 opp-50000000 {
2632 opp-hz = /bits/ 64 <50000000>,
2641 required-opps = <&rpmhpd_opp_low_svs>;
2644 opp-200000000 {
2645 opp-hz = /bits/ 64 <200000000>,
2654 required-opps = <&rpmhpd_opp_nom>;
2660 compatible = "qcom,sdm845-qmp-ufs-phy";
2666 clock-names = "ref",
2670 power-domains = <&gcc UFS_PHY_GDSC>;
2673 reset-names = "ufsphy";
2675 #phy-cells = <0>;
2679 cryptobam: dma-controller@1dc4000 {
2680 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2684 clock-names = "bam_clk";
2685 #dma-cells = <1>;
2687 qcom,controlled-remotely;
2695 compatible = "qcom,crypto-v5.4";
2700 clock-names = "iface", "bus", "core";
2702 dma-names = "rx", "tx";
2710 compatible = "qcom,sdm845-ipa";
2717 reg-names = "ipa-reg",
2718 "ipa-shared",
2721 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2725 interrupt-names = "ipa",
2727 "ipa-clock-query",
2728 "ipa-setup-ready";
2731 clock-names = "core";
2736 interconnect-names = "memory",
2740 qcom,smem-states = <&ipa_smp2p_out 0>,
2742 qcom,smem-state-names = "ipa-clock-enabled-valid",
2743 "ipa-clock-enabled";
2749 compatible = "qcom,tcsr-mutex";
2751 #hwlock-cells = <1>;
2755 compatible = "qcom,sdm845-tcsr", "syscon";
2760 compatible = "qcom,sdm845-pinctrl";
2763 gpio-controller;
2764 #gpio-cells = <2>;
2765 interrupt-controller;
2766 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm 0 0 151>;
2768 wakeup-parent = <&pdc_intc>;
2770 cci0_default: cci0-default-state {
2775 bias-pull-up;
2776 drive-strength = <2>; /* 2 mA */
2779 cci0_sleep: cci0-sleep-state {
2784 drive-strength = <2>; /* 2 mA */
2785 bias-pull-down;
2788 cci1_default: cci1-default-state {
2793 bias-pull-up;
2794 drive-strength = <2>; /* 2 mA */
2797 cci1_sleep: cci1-sleep-state {
2802 drive-strength = <2>; /* 2 mA */
2803 bias-pull-down;
2806 qspi_clk: qspi-clk-state {
2811 qspi_cs0: qspi-cs0-state {
2816 qspi_cs1: qspi-cs1-state {
2821 qspi_data0: qspi-data0-state {
2826 qspi_data1: qspi-data1-state {
2831 qspi_data23: qspi-data23-state {
2836 qup_i2c0_default: qup-i2c0-default-state {
2841 qup_i2c1_default: qup-i2c1-default-state {
2846 qup_i2c2_default: qup-i2c2-default-state {
2851 qup_i2c3_default: qup-i2c3-default-state {
2856 qup_i2c4_default: qup-i2c4-default-state {
2861 qup_i2c5_default: qup-i2c5-default-state {
2866 qup_i2c6_default: qup-i2c6-default-state {
2871 qup_i2c7_default: qup-i2c7-default-state {
2876 qup_i2c8_default: qup-i2c8-default-state {
2881 qup_i2c9_default: qup-i2c9-default-state {
2886 qup_i2c10_default: qup-i2c10-default-state {
2891 qup_i2c11_default: qup-i2c11-default-state {
2896 qup_i2c12_default: qup-i2c12-default-state {
2901 qup_i2c13_default: qup-i2c13-default-state {
2906 qup_i2c14_default: qup-i2c14-default-state {
2911 qup_i2c15_default: qup-i2c15-default-state {
2916 qup_spi0_default: qup-spi0-default-state {
2921 qup_spi1_default: qup-spi1-default-state {
2926 qup_spi2_default: qup-spi2-default-state {
2931 qup_spi3_default: qup-spi3-default-state {
2936 qup_spi4_default: qup-spi4-default-state {
2941 qup_spi5_default: qup-spi5-default-state {
2946 qup_spi6_default: qup-spi6-default-state {
2951 qup_spi7_default: qup-spi7-default-state {
2956 qup_spi8_default: qup-spi8-default-state {
2961 qup_spi9_default: qup-spi9-default-state {
2966 qup_spi10_default: qup-spi10-default-state {
2971 qup_spi11_default: qup-spi11-default-state {
2976 qup_spi12_default: qup-spi12-default-state {
2981 qup_spi13_default: qup-spi13-default-state {
2986 qup_spi14_default: qup-spi14-default-state {
2991 qup_spi15_default: qup-spi15-default-state {
2996 qup_uart0_default: qup-uart0-default-state {
2997 qup_uart0_tx: tx-pins {
3002 qup_uart0_rx: rx-pins {
3008 qup_uart1_default: qup-uart1-default-state {
3009 qup_uart1_tx: tx-pins {
3014 qup_uart1_rx: rx-pins {
3020 qup_uart2_default: qup-uart2-default-state {
3021 qup_uart2_tx: tx-pins {
3026 qup_uart2_rx: rx-pins {
3032 qup_uart3_default: qup-uart3-default-state {
3033 qup_uart3_tx: tx-pins {
3038 qup_uart3_rx: rx-pins {
3044 qup_uart3_4pin: qup-uart3-4pin-state {
3045 qup_uart3_4pin_cts: cts-pins {
3050 qup_uart3_4pin_rts_tx: rts-tx-pins {
3055 qup_uart3_4pin_rx: rx-pins {
3061 qup_uart4_default: qup-uart4-default-state {
3062 qup_uart4_tx: tx-pins {
3067 qup_uart4_rx: rx-pins {
3073 qup_uart5_default: qup-uart5-default-state {
3074 qup_uart5_tx: tx-pins {
3079 qup_uart5_rx: rx-pins {
3085 qup_uart6_default: qup-uart6-default-state {
3086 qup_uart6_tx: tx-pins {
3091 qup_uart6_rx: rx-pins {
3097 qup_uart6_4pin: qup-uart6-4pin-state {
3098 qup_uart6_4pin_cts: cts-pins {
3101 bias-pull-down;
3104 qup_uart6_4pin_rts_tx: rts-tx-pins {
3107 drive-strength = <2>;
3108 bias-disable;
3111 qup_uart6_4pin_rx: rx-pins {
3114 bias-pull-up;
3118 qup_uart7_default: qup-uart7-default-state {
3119 qup_uart7_tx: tx-pins {
3124 qup_uart7_rx: rx-pins {
3130 qup_uart8_default: qup-uart8-default-state {
3131 qup_uart8_tx: tx-pins {
3136 qup_uart8_rx: rx-pins {
3142 qup_uart9_default: qup-uart9-default-state {
3143 qup_uart9_tx: tx-pins {
3148 qup_uart9_rx: rx-pins {
3154 qup_uart10_default: qup-uart10-default-state {
3155 qup_uart10_tx: tx-pins {
3160 qup_uart10_rx: rx-pins {
3166 qup_uart11_default: qup-uart11-default-state {
3167 qup_uart11_tx: tx-pins {
3172 qup_uart11_rx: rx-pins {
3178 qup_uart12_default: qup-uart12-default-state {
3179 qup_uart12_tx: tx-pins {
3184 qup_uart12_rx: rx-pins {
3190 qup_uart13_default: qup-uart13-default-state {
3191 qup_uart13_tx: tx-pins {
3196 qup_uart13_rx: rx-pins {
3202 qup_uart14_default: qup-uart14-default-state {
3203 qup_uart14_tx: tx-pins {
3208 qup_uart14_rx: rx-pins {
3214 qup_uart15_default: qup-uart15-default-state {
3215 qup_uart15_tx: tx-pins {
3220 qup_uart15_rx: rx-pins {
3226 quat_mi2s_sleep: quat-mi2s-sleep-state {
3229 drive-strength = <2>;
3230 bias-pull-down;
3233 quat_mi2s_active: quat-mi2s-active-state {
3236 drive-strength = <8>;
3237 bias-disable;
3238 output-high;
3241 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3244 drive-strength = <2>;
3245 bias-pull-down;
3248 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3251 drive-strength = <8>;
3252 bias-disable;
3255 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3258 drive-strength = <2>;
3259 bias-pull-down;
3262 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3265 drive-strength = <8>;
3266 bias-disable;
3269 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3272 drive-strength = <2>;
3273 bias-pull-down;
3276 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3279 drive-strength = <8>;
3280 bias-disable;
3283 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3286 drive-strength = <2>;
3287 bias-pull-down;
3290 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3293 drive-strength = <8>;
3294 bias-disable;
3299 compatible = "qcom,sdm845-mss-pil";
3301 reg-names = "qdsp6", "rmb";
3303 interrupts-extended =
3310 interrupt-names = "wdog", "fatal", "ready",
3311 "handover", "stop-ack",
3312 "shutdown-ack";
3322 clock-names = "iface", "bus", "mem", "gpll0_mss",
3327 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names = "stop";
3332 reset-names = "mss_restart", "pdc_reset";
3334 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3336 power-domains = <&rpmhpd SDM845_CX>,
3339 power-domain-names = "cx", "mx", "mss";
3344 memory-region = <&mba_region>;
3348 memory-region = <&mpss_region>;
3352 memory-region = <&mdata_mem>;
3355 glink-edge {
3358 qcom,remote-pid = <1>;
3363 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sdm845-gpucc";
3366 #clock-cells = <1>;
3367 #reset-cells = <1>;
3368 #power-domain-cells = <1>;
3372 clock-names = "bi_tcxo",
3378 compatible = "qcom,sdm845-slpi-pas";
3381 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
3386 interrupt-names = "wdog", "fatal", "ready",
3387 "handover", "stop-ack";
3390 clock-names = "xo";
3394 power-domains = <&rpmhpd SDM845_LCX>,
3396 power-domain-names = "lcx", "lmx";
3398 memory-region = <&slpi_mem>;
3400 qcom,smem-states = <&slpi_smp2p_out 0>;
3401 qcom,smem-state-names = "stop";
3405 glink-edge {
3408 qcom,remote-pid = <3>;
3413 qcom,glink-channels = "fastrpcglink-apps-dsp";
3415 qcom,non-secure-domain;
3418 memory-region = <&fastrpc_mem>;
3419 #address-cells = <1>;
3420 #size-cells = <0>;
3422 compute-cb@0 {
3423 compatible = "qcom,fastrpc-compute-cb";
3431 compatible = "arm,coresight-stm", "arm,primecell";
3434 reg-names = "stm-base", "stm-stimulus-base";
3437 clock-names = "apb_pclk";
3439 out-ports {
3442 remote-endpoint =
3450 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3454 clock-names = "apb_pclk";
3456 out-ports {
3459 remote-endpoint =
3465 in-ports {
3466 #address-cells = <1>;
3467 #size-cells = <0>;
3472 remote-endpoint = <&stm_out>;
3479 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3483 clock-names = "apb_pclk";
3485 out-ports {
3488 remote-endpoint =
3494 in-ports {
3495 #address-cells = <1>;
3496 #size-cells = <0>;
3501 remote-endpoint =
3509 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3513 clock-names = "apb_pclk";
3515 out-ports {
3518 remote-endpoint = <&etf_in>;
3523 in-ports {
3524 #address-cells = <1>;
3525 #size-cells = <0>;
3530 remote-endpoint =
3538 remote-endpoint =
3546 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3550 clock-names = "apb_pclk";
3552 out-ports {
3555 remote-endpoint = <&etr_in>;
3560 in-ports {
3563 remote-endpoint = <&etf_out>;
3570 compatible = "arm,coresight-tmc", "arm,primecell";
3574 clock-names = "apb_pclk";
3576 out-ports {
3579 remote-endpoint =
3585 in-ports {
3589 remote-endpoint =
3597 compatible = "arm,coresight-tmc", "arm,primecell";
3601 clock-names = "apb_pclk";
3602 arm,scatter-gather;
3604 in-ports {
3607 remote-endpoint =
3615 compatible = "arm,coresight-etm4x", "arm,primecell";
3618 cpu = <&CPU0>;
3621 clock-names = "apb_pclk";
3622 arm,coresight-loses-context-with-cpu;
3624 out-ports {
3627 remote-endpoint =
3635 compatible = "arm,coresight-etm4x", "arm,primecell";
3638 cpu = <&CPU1>;
3641 clock-names = "apb_pclk";
3642 arm,coresight-loses-context-with-cpu;
3644 out-ports {
3647 remote-endpoint =
3655 compatible = "arm,coresight-etm4x", "arm,primecell";
3658 cpu = <&CPU2>;
3661 clock-names = "apb_pclk";
3662 arm,coresight-loses-context-with-cpu;
3664 out-ports {
3667 remote-endpoint =
3675 compatible = "arm,coresight-etm4x", "arm,primecell";
3678 cpu = <&CPU3>;
3681 clock-names = "apb_pclk";
3682 arm,coresight-loses-context-with-cpu;
3684 out-ports {
3687 remote-endpoint =
3695 compatible = "arm,coresight-etm4x", "arm,primecell";
3698 cpu = <&CPU4>;
3701 clock-names = "apb_pclk";
3702 arm,coresight-loses-context-with-cpu;
3704 out-ports {
3707 remote-endpoint =
3715 compatible = "arm,coresight-etm4x", "arm,primecell";
3718 cpu = <&CPU5>;
3721 clock-names = "apb_pclk";
3722 arm,coresight-loses-context-with-cpu;
3724 out-ports {
3727 remote-endpoint =
3735 compatible = "arm,coresight-etm4x", "arm,primecell";
3738 cpu = <&CPU6>;
3741 clock-names = "apb_pclk";
3742 arm,coresight-loses-context-with-cpu;
3744 out-ports {
3747 remote-endpoint =
3755 compatible = "arm,coresight-etm4x", "arm,primecell";
3758 cpu = <&CPU7>;
3761 clock-names = "apb_pclk";
3762 arm,coresight-loses-context-with-cpu;
3764 out-ports {
3767 remote-endpoint =
3775 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3779 clock-names = "apb_pclk";
3781 out-ports {
3784 remote-endpoint =
3790 in-ports {
3791 #address-cells = <1>;
3792 #size-cells = <0>;
3797 remote-endpoint =
3805 remote-endpoint =
3813 remote-endpoint =
3821 remote-endpoint =
3829 remote-endpoint =
3837 remote-endpoint =
3845 remote-endpoint =
3853 remote-endpoint =
3861 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3865 clock-names = "apb_pclk";
3867 out-ports {
3870 remote-endpoint =
3876 in-ports {
3879 remote-endpoint =
3887 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3892 interrupt-names = "hc_irq", "pwr_irq";
3897 clock-names = "iface", "core", "xo";
3899 power-domains = <&rpmhpd SDM845_CX>;
3900 operating-points-v2 = <&sdhc2_opp_table>;
3904 sdhc2_opp_table: opp-table {
3905 compatible = "operating-points-v2";
3907 opp-9600000 {
3908 opp-hz = /bits/ 64 <9600000>;
3909 required-opps = <&rpmhpd_opp_min_svs>;
3912 opp-19200000 {
3913 opp-hz = /bits/ 64 <19200000>;
3914 required-opps = <&rpmhpd_opp_low_svs>;
3917 opp-100000000 {
3918 opp-hz = /bits/ 64 <100000000>;
3919 required-opps = <&rpmhpd_opp_svs>;
3922 opp-201500000 {
3923 opp-hz = /bits/ 64 <201500000>;
3924 required-opps = <&rpmhpd_opp_svs_l1>;
3930 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3933 #address-cells = <1>;
3934 #size-cells = <0>;
3938 clock-names = "iface", "core";
3939 power-domains = <&rpmhpd SDM845_CX>;
3940 operating-points-v2 = <&qspi_opp_table>;
3944 slim: slim-ngd@171c0000 {
3945 compatible = "qcom,slim-ngd-v2.1.0";
3950 dma-names = "rx", "tx";
3953 #address-cells = <1>;
3954 #size-cells = <0>;
3959 compatible = "qcom,sdm845-lmh";
3963 qcom,lmh-temp-arm-millicelsius = <65000>;
3964 qcom,lmh-temp-low-millicelsius = <94500>;
3965 qcom,lmh-temp-high-millicelsius = <95000>;
3966 interrupt-controller;
3967 #interrupt-cells = <1>;
3971 compatible = "qcom,sdm845-lmh";
3975 qcom,lmh-temp-arm-millicelsius = <65000>;
3976 qcom,lmh-temp-low-millicelsius = <94500>;
3977 qcom,lmh-temp-high-millicelsius = <95000>;
3978 interrupt-controller;
3979 #interrupt-cells = <1>;
3983 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3986 #phy-cells = <0>;
3990 clock-names = "cfg_ahb", "ref";
3994 nvmem-cells = <&qusb2p_hstx_trim>;
3998 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
4001 #phy-cells = <0>;
4005 clock-names = "cfg_ahb", "ref";
4009 nvmem-cells = <&qusb2s_hstx_trim>;
4013 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
4022 clock-names = "aux",
4030 reset-names = "phy", "common";
4032 #clock-cells = <1>;
4033 #phy-cells = <1>;
4034 orientation-switch;
4037 #address-cells = <1>;
4038 #size-cells = <0>;
4051 remote-endpoint = <&usb_1_dwc3_ss>;
4059 remote-endpoint = <&dp_out>;
4066 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4074 clock-names = "aux",
4079 clock-output-names = "usb3_uni_phy_pipe_clk_src";
4080 #clock-cells = <0>;
4081 #phy-cells = <0>;
4085 reset-names = "phy",
4092 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4095 #address-cells = <2>;
4096 #size-cells = <2>;
4098 dma-ranges;
4105 clock-names = "cfg_noc",
4111 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4113 assigned-clock-rates = <19200000>, <150000000>;
4115 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4120 interrupt-names = "pwr_event",
4126 power-domains = <&gcc USB30_PRIM_GDSC>;
4132 interconnect-names = "usb-ddr", "apps-usb";
4141 snps,parkmode-disable-ss-quirk;
4143 phy-names = "usb2-phy", "usb3-phy";
4146 #address-cells = <1>;
4147 #size-cells = <0>;
4160 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
4168 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4171 #address-cells = <2>;
4172 #size-cells = <2>;
4174 dma-ranges;
4181 clock-names = "cfg_noc",
4187 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4189 assigned-clock-rates = <19200000>, <150000000>;
4191 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4196 interrupt-names = "pwr_event",
4202 power-domains = <&gcc USB30_SEC_GDSC>;
4208 interconnect-names = "usb-ddr", "apps-usb";
4217 snps,parkmode-disable-ss-quirk;
4219 phy-names = "usb2-phy", "usb3-phy";
4223 venus: video-codec@aa00000 {
4224 compatible = "qcom,sdm845-venus-v2";
4227 power-domains = <&videocc VENUS_GDSC>,
4231 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4232 operating-points-v2 = <&venus_opp_table>;
4240 clock-names = "core", "iface", "bus",
4245 memory-region = <&venus_mem>;
4248 interconnect-names = "video-mem", "cpu-cfg";
4252 video-core0 {
4253 compatible = "venus-decoder";
4256 video-core1 {
4257 compatible = "venus-encoder";
4260 venus_opp_table: opp-table {
4261 compatible = "operating-points-v2";
4263 opp-100000000 {
4264 opp-hz = /bits/ 64 <100000000>;
4265 required-opps = <&rpmhpd_opp_min_svs>;
4268 opp-200000000 {
4269 opp-hz = /bits/ 64 <200000000>;
4270 required-opps = <&rpmhpd_opp_low_svs>;
4273 opp-320000000 {
4274 opp-hz = /bits/ 64 <320000000>;
4275 required-opps = <&rpmhpd_opp_svs>;
4278 opp-380000000 {
4279 opp-hz = /bits/ 64 <380000000>;
4280 required-opps = <&rpmhpd_opp_svs_l1>;
4283 opp-444000000 {
4284 opp-hz = /bits/ 64 <444000000>;
4285 required-opps = <&rpmhpd_opp_nom>;
4288 opp-533000097 {
4289 opp-hz = /bits/ 64 <533000097>;
4290 required-opps = <&rpmhpd_opp_turbo>;
4295 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sdm845-videocc";
4299 clock-names = "bi_tcxo";
4300 #clock-cells = <1>;
4301 #power-domain-cells = <1>;
4302 #reset-cells = <1>;
4306 compatible = "qcom,sdm845-camss";
4318 reg-names = "csid0",
4339 interrupt-names = "csid0",
4350 power-domains = <&clock_camcc IFE_0_GDSC>,
4390 clock-names = "camnoc_axi",
4435 #address-cells = <1>;
4436 #size-cells = <0>;
4457 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
4458 #address-cells = <1>;
4459 #size-cells = <0>;
4463 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4471 clock-names = "camnoc_axi",
4478 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4480 assigned-clock-rates = <80000000>, <37500000>;
4482 pinctrl-names = "default", "sleep";
4483 pinctrl-0 = <&cci0_default &cci1_default>;
4484 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4488 cci_i2c0: i2c-bus@0 {
4490 clock-frequency = <1000000>;
4491 #address-cells = <1>;
4492 #size-cells = <0>;
4495 cci_i2c1: i2c-bus@1 {
4497 clock-frequency = <1000000>;
4498 #address-cells = <1>;
4499 #size-cells = <0>;
4503 clock_camcc: clock-controller@ad00000 {
4504 compatible = "qcom,sdm845-camcc";
4506 #clock-cells = <1>;
4507 #reset-cells = <1>;
4508 #power-domain-cells = <1>;
4510 clock-names = "bi_tcxo";
4513 mdss: display-subsystem@ae00000 {
4514 compatible = "qcom,sdm845-mdss";
4516 reg-names = "mdss";
4518 power-domains = <&dispcc MDSS_GDSC>;
4522 clock-names = "iface", "core";
4525 interrupt-controller;
4526 #interrupt-cells = <1>;
4530 interconnect-names = "mdp0-mem", "mdp1-mem";
4537 #address-cells = <2>;
4538 #size-cells = <2>;
4541 mdss_mdp: display-controller@ae01000 {
4542 compatible = "qcom,sdm845-dpu";
4545 reg-names = "mdp", "vbif";
4552 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4554 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4555 assigned-clock-rates = <19200000>;
4556 operating-points-v2 = <&mdp_opp_table>;
4557 power-domains = <&rpmhpd SDM845_CX>;
4559 interrupt-parent = <&mdss>;
4563 #address-cells = <1>;
4564 #size-cells = <0>;
4569 remote-endpoint = <&dp_in>;
4576 remote-endpoint = <&mdss_dsi0_in>;
4583 remote-endpoint = <&mdss_dsi1_in>;
4588 mdp_opp_table: opp-table {
4589 compatible = "operating-points-v2";
4591 opp-19200000 {
4592 opp-hz = /bits/ 64 <19200000>;
4593 required-opps = <&rpmhpd_opp_min_svs>;
4596 opp-171428571 {
4597 opp-hz = /bits/ 64 <171428571>;
4598 required-opps = <&rpmhpd_opp_low_svs>;
4601 opp-344000000 {
4602 opp-hz = /bits/ 64 <344000000>;
4603 required-opps = <&rpmhpd_opp_svs_l1>;
4606 opp-430000000 {
4607 opp-hz = /bits/ 64 <430000000>;
4608 required-opps = <&rpmhpd_opp_nom>;
4613 mdss_dp: displayport-controller@ae90000 {
4615 compatible = "qcom,sdm845-dp";
4623 interrupt-parent = <&mdss>;
4631 clock-names = "core_iface", "core_aux", "ctrl_link",
4633 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4635 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4638 phy-names = "dp";
4640 operating-points-v2 = <&dp_opp_table>;
4641 power-domains = <&rpmhpd SDM845_CX>;
4644 #address-cells = <1>;
4645 #size-cells = <0>;
4649 remote-endpoint = <&dpu_intf0_out>;
4656 remote-endpoint = <&usb_1_qmpphy_dp_in>;
4661 dp_opp_table: opp-table {
4662 compatible = "operating-points-v2";
4664 opp-162000000 {
4665 opp-hz = /bits/ 64 <162000000>;
4666 required-opps = <&rpmhpd_opp_low_svs>;
4669 opp-270000000 {
4670 opp-hz = /bits/ 64 <270000000>;
4671 required-opps = <&rpmhpd_opp_svs>;
4674 opp-540000000 {
4675 opp-hz = /bits/ 64 <540000000>;
4676 required-opps = <&rpmhpd_opp_svs_l1>;
4679 opp-810000000 {
4680 opp-hz = /bits/ 64 <810000000>;
4681 required-opps = <&rpmhpd_opp_nom>;
4687 compatible = "qcom,sdm845-dsi-ctrl",
4688 "qcom,mdss-dsi-ctrl";
4690 reg-names = "dsi_ctrl";
4692 interrupt-parent = <&mdss>;
4701 clock-names = "byte",
4707 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4708 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4710 operating-points-v2 = <&dsi_opp_table>;
4711 power-domains = <&rpmhpd SDM845_CX>;
4717 #address-cells = <1>;
4718 #size-cells = <0>;
4721 #address-cells = <1>;
4722 #size-cells = <0>;
4727 remote-endpoint = <&dpu_intf1_out>;
4740 compatible = "qcom,dsi-phy-10nm";
4744 reg-names = "dsi_phy",
4748 #clock-cells = <1>;
4749 #phy-cells = <0>;
4753 clock-names = "iface", "ref";
4759 compatible = "qcom,sdm845-dsi-ctrl",
4760 "qcom,mdss-dsi-ctrl";
4762 reg-names = "dsi_ctrl";
4764 interrupt-parent = <&mdss>;
4773 clock-names = "byte",
4779 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4780 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4782 operating-points-v2 = <&dsi_opp_table>;
4783 power-domains = <&rpmhpd SDM845_CX>;
4789 #address-cells = <1>;
4790 #size-cells = <0>;
4793 #address-cells = <1>;
4794 #size-cells = <0>;
4799 remote-endpoint = <&dpu_intf2_out>;
4812 compatible = "qcom,dsi-phy-10nm";
4816 reg-names = "dsi_phy",
4820 #clock-cells = <1>;
4821 #phy-cells = <0>;
4825 clock-names = "iface", "ref";
4832 compatible = "qcom,adreno-630.2", "qcom,adreno";
4835 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4846 operating-points-v2 = <&gpu_opp_table>;
4849 #cooling-cells = <2>;
4852 interconnect-names = "gfx-mem";
4856 gpu_opp_table: opp-table {
4857 compatible = "operating-points-v2";
4859 opp-710000000 {
4860 opp-hz = /bits/ 64 <710000000>;
4861 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-peak-kBps = <7216000>;
4865 opp-675000000 {
4866 opp-hz = /bits/ 64 <675000000>;
4867 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-peak-kBps = <7216000>;
4871 opp-596000000 {
4872 opp-hz = /bits/ 64 <596000000>;
4873 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-peak-kBps = <6220000>;
4877 opp-520000000 {
4878 opp-hz = /bits/ 64 <520000000>;
4879 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-peak-kBps = <6220000>;
4883 opp-414000000 {
4884 opp-hz = /bits/ 64 <414000000>;
4885 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-peak-kBps = <4068000>;
4889 opp-342000000 {
4890 opp-hz = /bits/ 64 <342000000>;
4891 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-peak-kBps = <2724000>;
4895 opp-257000000 {
4896 opp-hz = /bits/ 64 <257000000>;
4897 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-peak-kBps = <1648000>;
4904 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4906 #iommu-cells = <1>;
4907 #global-interrupts = <2>;
4920 clock-names = "bus", "iface";
4922 power-domains = <&gpucc GPU_CX_GDSC>;
4926 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4931 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4935 interrupt-names = "hfi", "gmu";
4941 clock-names = "gmu", "cxo", "axi", "memnoc";
4943 power-domains = <&gpucc GPU_CX_GDSC>,
4945 power-domain-names = "cx", "gx";
4949 operating-points-v2 = <&gmu_opp_table>;
4953 gmu_opp_table: opp-table {
4954 compatible = "operating-points-v2";
4956 opp-400000000 {
4957 opp-hz = /bits/ 64 <400000000>;
4958 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4961 opp-200000000 {
4962 opp-hz = /bits/ 64 <200000000>;
4963 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4968 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sdm845-dispcc";
4980 clock-names = "bi_tcxo",
4989 #clock-cells = <1>;
4990 #reset-cells = <1>;
4991 #power-domain-cells = <1>;
4994 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4997 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2>;
4999 interrupt-parent = <&intc>;
5000 interrupt-controller;
5003 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sdm845-pdc-global";
5006 #reset-cells = <1>;
5009 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5016 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells = <1>;
5020 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5027 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells = <1>;
5031 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sdm845-aoss-cc";
5034 #reset-cells = <1>;
5037 aoss_qmp: power-management@c300000 {
5038 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
5043 #clock-cells = <0>;
5046 #cooling-cells = <2>;
5050 #cooling-cells = <2>;
5055 compatible = "qcom,sdm845-rpmh-stats";
5060 compatible = "qcom,spmi-pmic-arb";
5066 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "periph_irq";
5071 #address-cells = <2>;
5072 #size-cells = <0>;
5073 interrupt-controller;
5074 #interrupt-cells = <4>;
5078 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5081 #address-cells = <1>;
5082 #size-cells = <1>;
5086 pil-reloc@94c {
5087 compatible = "qcom,pil-reloc-info";
5093 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5095 #iommu-cells = <2>;
5096 #global-interrupts = <1>;
5165 compatible = "qcom,sdm845-tbu";
5169 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>;
5170 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
5174 compatible = "qcom,sdm845-tbu";
5178 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>;
5179 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
5183 compatible = "qcom,sdm845-tbu";
5187 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
5188 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
5192 compatible = "qcom,sdm845-tbu";
5196 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
5197 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
5201 compatible = "qcom,sdm845-tbu";
5205 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>;
5206 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
5210 compatible = "qcom,sdm845-tbu";
5214 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
5218 compatible = "qcom,sdm845-tbu";
5222 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>;
5223 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
5227 compatible = "qcom,sdm845-tbu";
5232 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
5233 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
5236 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sdm845-lpasscc";
5239 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>;
5245 compatible = "qcom,sdm845-gladiator-noc";
5247 #interconnect-cells = <2>;
5248 qcom,bcm-voters = <&apps_bcm_voter>;
5252 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5259 compatible = "qcom,sdm845-apss-shared";
5261 #mbox-cells = <1>;
5266 compatible = "qcom,rpmh-rsc";
5270 reg-names = "drv-0", "drv-1", "drv-2";
5274 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>;
5276 qcom,tcs-config = <ACTIVE_TCS 2>,
5280 power-domains = <&CLUSTER_PD>;
5282 apps_bcm_voter: bcm-voter {
5283 compatible = "qcom,bcm-voter";
5286 rpmhcc: clock-controller {
5287 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells = <1>;
5289 clock-names = "xo";
5293 rpmhpd: power-controller {
5294 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain-cells = <1>;
5296 operating-points-v2 = <&rpmhpd_opp_table>;
5298 rpmhpd_opp_table: opp-table {
5299 compatible = "operating-points-v2";
5302 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5306 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5310 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5314 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5318 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5322 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5326 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5330 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5334 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5338 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5344 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic-v3";
5346 #address-cells = <2>;
5347 #size-cells = <2>;
5349 #interrupt-cells = <3>;
5350 interrupt-controller;
5355 msi-controller@17a40000 {
5356 compatible = "arm,gic-v3-its";
5357 msi-controller;
5358 #msi-cells = <1>;
5364 slimbam: dma-controller@17184000 {
5365 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5366 qcom,controlled-remotely;
5368 num-channels = <31>;
5370 #dma-cells = <1>;
5372 qcom,num-ees = <2>;
5377 #address-cells = <1>;
5378 #size-cells = <1>;
5380 compatible = "arm,armv7-timer-mem";
5384 frame-number = <0>;
5392 frame-number = <1>;
5399 frame-number = <2>;
5406 frame-number = <3>;
5413 frame-number = <4>;
5420 frame-number = <5>;
5427 frame-number = <6>;
5435 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5439 clock-names = "xo", "alternate";
5441 #interconnect-cells = <1>;
5445 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5447 reg-names = "freq-domain0", "freq-domain1";
5449 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5452 clock-names = "xo", "alternate";
5454 #freq-domain-cells = <1>;
5455 #clock-cells = <1>;
5459 compatible = "qcom,wcn3990-wifi";
5462 reg-names = "membase";
5463 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_ref_clk_pin";
5486 thermal-zones {
5487 cpu0-thermal {
5488 polling-delay-passive = <250>;
5490 thermal-sensors = <&tsens0 1>;
5493 cpu0_alert0: trip-point0 {
5499 cpu0_alert1: trip-point1 {
5505 cpu0_crit: cpu-crit {
5513 cpu1-thermal {
5514 polling-delay-passive = <250>;
5516 thermal-sensors = <&tsens0 2>;
5519 cpu1_alert0: trip-point0 {
5525 cpu1_alert1: trip-point1 {
5531 cpu1_crit: cpu-crit {
5539 cpu2-thermal {
5540 polling-delay-passive = <250>;
5542 thermal-sensors = <&tsens0 3>;
5545 cpu2_alert0: trip-point0 {
5551 cpu2_alert1: trip-point1 {
5557 cpu2_crit: cpu-crit {
5565 cpu3-thermal {
5566 polling-delay-passive = <250>;
5568 thermal-sensors = <&tsens0 4>;
5571 cpu3_alert0: trip-point0 {
5577 cpu3_alert1: trip-point1 {
5583 cpu3_crit: cpu-crit {
5591 cpu4-thermal {
5592 polling-delay-passive = <250>;
5594 thermal-sensors = <&tsens0 7>;
5597 cpu4_alert0: trip-point0 {
5603 cpu4_alert1: trip-point1 {
5609 cpu4_crit: cpu-crit {
5617 cpu5-thermal {
5618 polling-delay-passive = <250>;
5620 thermal-sensors = <&tsens0 8>;
5623 cpu5_alert0: trip-point0 {
5629 cpu5_alert1: trip-point1 {
5635 cpu5_crit: cpu-crit {
5643 cpu6-thermal {
5644 polling-delay-passive = <250>;
5646 thermal-sensors = <&tsens0 9>;
5649 cpu6_alert0: trip-point0 {
5655 cpu6_alert1: trip-point1 {
5661 cpu6_crit: cpu-crit {
5669 cpu7-thermal {
5670 polling-delay-passive = <250>;
5672 thermal-sensors = <&tsens0 10>;
5675 cpu7_alert0: trip-point0 {
5681 cpu7_alert1: trip-point1 {
5687 cpu7_crit: cpu-crit {
5695 aoss0-thermal {
5696 polling-delay-passive = <250>;
5698 thermal-sensors = <&tsens0 0>;
5701 aoss0_alert0: trip-point0 {
5709 cluster0-thermal {
5710 polling-delay-passive = <250>;
5712 thermal-sensors = <&tsens0 5>;
5715 cluster0_alert0: trip-point0 {
5720 cluster0_crit: cluster0-crit {
5728 cluster1-thermal {
5729 polling-delay-passive = <250>;
5731 thermal-sensors = <&tsens0 6>;
5734 cluster1_alert0: trip-point0 {
5739 cluster1_crit: cluster1-crit {
5747 gpu-top-thermal {
5748 polling-delay-passive = <250>;
5750 thermal-sensors = <&tsens0 11>;
5752 cooling-maps {
5755 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5760 gpu_top_alert0: trip-point0 {
5766 trip-point1 {
5772 trip-point2 {
5780 gpu-bottom-thermal {
5781 polling-delay-passive = <250>;
5783 thermal-sensors = <&tsens0 12>;
5785 cooling-maps {
5788 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5793 gpu_bottom_alert0: trip-point0 {
5799 trip-point1 {
5805 trip-point2 {
5813 aoss1-thermal {
5814 polling-delay-passive = <250>;
5816 thermal-sensors = <&tsens1 0>;
5819 aoss1_alert0: trip-point0 {
5827 q6-modem-thermal {
5828 polling-delay-passive = <250>;
5830 thermal-sensors = <&tsens1 1>;
5833 q6_modem_alert0: trip-point0 {
5841 mem-thermal {
5842 polling-delay-passive = <250>;
5844 thermal-sensors = <&tsens1 2>;
5847 mem_alert0: trip-point0 {
5855 wlan-thermal {
5856 polling-delay-passive = <250>;
5858 thermal-sensors = <&tsens1 3>;
5861 wlan_alert0: trip-point0 {
5869 q6-hvx-thermal {
5870 polling-delay-passive = <250>;
5872 thermal-sensors = <&tsens1 4>;
5875 q6_hvx_alert0: trip-point0 {
5883 camera-thermal {
5884 polling-delay-passive = <250>;
5886 thermal-sensors = <&tsens1 5>;
5889 camera_alert0: trip-point0 {
5897 video-thermal {
5898 polling-delay-passive = <250>;
5900 thermal-sensors = <&tsens1 6>;
5903 video_alert0: trip-point0 {
5911 modem-thermal {
5912 polling-delay-passive = <250>;
5914 thermal-sensors = <&tsens1 7>;
5917 modem_alert0: trip-point0 {
5927 compatible = "arm,armv8-timer";