Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
9 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11 #include <dt-bindings/clock/qcom,sa8775p-videocc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/power/qcom,rpmhpd.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/soc/qcom,gpr.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
31 xo_board_clk: xo-board-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <38400000>;
37 sleep_clk: sleep-clk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <32000>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a78c";
52 enable-method = "psci";
53 next-level-cache = <&l2_0>;
54 power-domains = <&cpu_pd0>;
55 power-domain-names = "psci";
56 capacity-dmips-mhz = <1946>;
57 dynamic-power-coefficient = <472>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
59 operating-points-v2 = <&cpu0_opp_table>;
65 l2_0: l2-cache {
67 cache-level = <2>;
68 cache-unified;
69 next-level-cache = <&l3_0>;
75 compatible = "arm,cortex-a78c";
77 enable-method = "psci";
78 next-level-cache = <&l2_1>;
79 power-domains = <&cpu_pd1>;
80 power-domain-names = "psci";
81 capacity-dmips-mhz = <1946>;
82 dynamic-power-coefficient = <472>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 operating-points-v2 = <&cpu0_opp_table>;
90 l2_1: l2-cache {
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&l3_0>;
100 compatible = "arm,cortex-a78c";
102 enable-method = "psci";
103 next-level-cache = <&l2_2>;
104 power-domains = <&cpu_pd2>;
105 power-domain-names = "psci";
106 capacity-dmips-mhz = <1946>;
107 dynamic-power-coefficient = <507>;
108 qcom,freq-domain = <&cpufreq_hw 2>;
109 operating-points-v2 = <&cpu2_opp_table>;
115 l2_2: l2-cache {
117 cache-level = <2>;
118 cache-unified;
119 next-level-cache = <&l3_0>;
125 compatible = "arm,cortex-a78c";
127 enable-method = "psci";
128 next-level-cache = <&l2_3>;
129 power-domains = <&cpu_pd3>;
130 power-domain-names = "psci";
131 capacity-dmips-mhz = <1946>;
132 dynamic-power-coefficient = <507>;
133 qcom,freq-domain = <&cpufreq_hw 2>;
134 operating-points-v2 = <&cpu2_opp_table>;
140 l2_3: l2-cache {
142 cache-level = <2>;
143 cache-unified;
144 next-level-cache = <&l3_0>;
150 compatible = "arm,cortex-a55";
152 enable-method = "psci";
153 next-level-cache = <&l2_4>;
154 power-domains = <&cpu_pd4>;
155 power-domain-names = "psci";
156 capacity-dmips-mhz = <1024>;
157 dynamic-power-coefficient = <100>;
158 qcom,freq-domain = <&cpufreq_hw 1>;
159 operating-points-v2 = <&cpu4_opp_table>;
165 l2_4: l2-cache {
167 cache-level = <2>;
168 cache-unified;
169 next-level-cache = <&l3_1>;
175 compatible = "arm,cortex-a55";
177 enable-method = "psci";
178 next-level-cache = <&l2_5>;
179 power-domains = <&cpu_pd5>;
180 power-domain-names = "psci";
181 capacity-dmips-mhz = <1024>;
182 dynamic-power-coefficient = <100>;
183 qcom,freq-domain = <&cpufreq_hw 1>;
184 operating-points-v2 = <&cpu4_opp_table>;
190 l2_5: l2-cache {
192 cache-level = <2>;
193 cache-unified;
194 next-level-cache = <&l3_1>;
200 compatible = "arm,cortex-a55";
202 enable-method = "psci";
203 next-level-cache = <&l2_6>;
204 power-domains = <&cpu_pd6>;
205 power-domain-names = "psci";
206 capacity-dmips-mhz = <1024>;
207 dynamic-power-coefficient = <100>;
208 qcom,freq-domain = <&cpufreq_hw 1>;
209 operating-points-v2 = <&cpu4_opp_table>;
215 l2_6: l2-cache {
217 cache-level = <2>;
218 cache-unified;
219 next-level-cache = <&l3_1>;
225 compatible = "arm,cortex-a55";
227 enable-method = "psci";
228 next-level-cache = <&l2_7>;
229 power-domains = <&cpu_pd7>;
230 power-domain-names = "psci";
231 capacity-dmips-mhz = <1024>;
232 dynamic-power-coefficient = <100>;
233 qcom,freq-domain = <&cpufreq_hw 1>;
234 operating-points-v2 = <&cpu4_opp_table>;
240 l2_7: l2-cache {
242 cache-level = <2>;
243 cache-unified;
244 next-level-cache = <&l3_1>;
248 cpu-map {
286 l3_0: l3-cache-0 {
288 cache-level = <3>;
289 cache-unified;
292 l3_1: l3-cache-1 {
294 cache-level = <3>;
295 cache-unified;
298 idle-states {
299 entry-method = "psci";
301 little_cpu_sleep_0: cpu-sleep-0-0 {
302 compatible = "arm,idle-state";
303 idle-state-name = "silver-power-collapse";
304 arm,psci-suspend-param = <0x40000003>;
305 entry-latency-us = <449>;
306 exit-latency-us = <801>;
307 min-residency-us = <1574>;
308 local-timer-stop;
311 little_cpu_sleep_1: cpu-sleep-0-1 {
312 compatible = "arm,idle-state";
313 idle-state-name = "silver-rail-power-collapse";
314 arm,psci-suspend-param = <0x40000004>;
315 entry-latency-us = <602>;
316 exit-latency-us = <961>;
317 min-residency-us = <4288>;
318 local-timer-stop;
321 big_cpu_sleep_0: cpu-sleep-1-0 {
322 compatible = "arm,idle-state";
323 idle-state-name = "gold-power-collapse";
324 arm,psci-suspend-param = <0x40000003>;
325 entry-latency-us = <549>;
326 exit-latency-us = <901>;
327 min-residency-us = <1774>;
328 local-timer-stop;
331 big_cpu_sleep_1: cpu-sleep-1-1 {
332 compatible = "arm,idle-state";
333 idle-state-name = "gold-rail-power-collapse";
334 arm,psci-suspend-param = <0x40000004>;
335 entry-latency-us = <702>;
336 exit-latency-us = <1061>;
337 min-residency-us = <4488>;
338 local-timer-stop;
342 domain-idle-states {
343 silver_cluster_sleep: cluster-sleep-0 {
344 compatible = "domain-idle-state";
345 arm,psci-suspend-param = <0x41000044>;
346 entry-latency-us = <2552>;
347 exit-latency-us = <2848>;
348 min-residency-us = <5908>;
351 gold_cluster_sleep: cluster-sleep-1 {
352 compatible = "domain-idle-state";
353 arm,psci-suspend-param = <0x41000044>;
354 entry-latency-us = <2752>;
355 exit-latency-us = <3048>;
356 min-residency-us = <6118>;
359 system_sleep: domain-sleep {
360 compatible = "domain-idle-state";
361 arm,psci-suspend-param = <0x42000144>;
362 entry-latency-us = <3263>;
363 exit-latency-us = <6562>;
364 min-residency-us = <9987>;
369 cpu0_opp_table: opp-table-cpu0 {
370 compatible = "operating-points-v2";
371 opp-shared;
373 opp-902400000 {
374 opp-hz = /bits/ 64 <902400000>;
375 opp-peak-kBps = <(681600 * 4) (921600 * 32)>;
378 opp-1017600000 {
379 opp-hz = /bits/ 64 <1017600000>;
380 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>;
383 opp-1190400000 {
384 opp-hz = /bits/ 64 <1190400000>;
385 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>;
388 opp-1267200000 {
389 opp-hz = /bits/ 64 <1267200000>;
390 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>;
393 opp-1344000000 {
394 opp-hz = /bits/ 64 <1344000000>;
395 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>;
398 opp-1420800000 {
399 opp-hz = /bits/ 64 <1420800000>;
400 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>;
403 opp-1497600000 {
404 opp-hz = /bits/ 64 <1497600000>;
405 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>;
408 opp-1574400000 {
409 opp-hz = /bits/ 64 <1574400000>;
410 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
413 opp-1670400000 {
414 opp-hz = /bits/ 64 <1670400000>;
415 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>;
418 opp-1747200000 {
419 opp-hz = /bits/ 64 <1747200000>;
420 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>;
423 opp-1824000000 {
424 opp-hz = /bits/ 64 <1824000000>;
425 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>;
428 opp-1900800000 {
429 opp-hz = /bits/ 64 <1900800000>;
430 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>;
433 opp-1977600000 {
434 opp-hz = /bits/ 64 <1977600000>;
435 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>;
438 opp-2054400000 {
439 opp-hz = /bits/ 64 <2054400000>;
440 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>;
443 opp-2112000000 {
444 opp-hz = /bits/ 64 <2112000000>;
445 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
450 cpu2_opp_table: opp-table-cpu2 {
451 compatible = "operating-points-v2";
452 opp-shared;
454 opp-940800000 {
455 opp-hz = /bits/ 64 <940800000>;
456 opp-peak-kBps = <(681600 * 4) (921600 * 32)>;
459 opp-1094400000 {
460 opp-hz = /bits/ 64 <1094400000>;
461 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>;
464 opp-1267200000 {
465 opp-hz = /bits/ 64 <1267200000>;
466 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>;
469 opp-1344000000 {
470 opp-hz = /bits/ 64 <1344000000>;
471 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>;
474 opp-1420800000 {
475 opp-hz = /bits/ 64 <1420800000>;
476 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>;
479 opp-1497600000 {
480 opp-hz = /bits/ 64 <1497600000>;
481 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>;
484 opp-1574400000 {
485 opp-hz = /bits/ 64 <1574400000>;
486 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>;
489 opp-1632000000 {
490 opp-hz = /bits/ 64 <1632000000>;
491 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>;
494 opp-1708800000 {
495 opp-hz = /bits/ 64 <1708800000>;
496 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
499 opp-1804800000 {
500 opp-hz = /bits/ 64 <1804800000>;
501 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
504 opp-1900800000 {
505 opp-hz = /bits/ 64 <1900800000>;
506 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
509 opp-1977600000 {
510 opp-hz = /bits/ 64 <1977600000>;
511 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>;
514 opp-2054400000 {
515 opp-hz = /bits/ 64 <2054400000>;
516 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>;
519 opp-2131200000 {
520 opp-hz = /bits/ 64 <2131200000>;
521 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>;
524 opp-2208000000 {
525 opp-hz = /bits/ 64 <2208000000>;
526 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>;
529 opp-2284800000 {
530 opp-hz = /bits/ 64 <2284800000>;
531 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
534 opp-2361600000 {
535 opp-hz = /bits/ 64 <2361600000>;
536 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
541 cpu4_opp_table: opp-table-cpu4 {
542 compatible = "operating-points-v2";
543 opp-shared;
545 opp-844800000 {
546 opp-hz = /bits/ 64 <844800000>;
547 opp-peak-kBps = <(681600 * 4) (921600 * 32)>;
550 opp-1113600000 {
551 opp-hz = /bits/ 64 <1113600000>;
552 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>;
555 opp-1209600000 {
556 opp-hz = /bits/ 64 <1209600000>;
557 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>;
560 opp-1305600000 {
561 opp-hz = /bits/ 64 <1305600000>;
562 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>;
565 opp-1382400000 {
566 opp-hz = /bits/ 64 <1382400000>;
567 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>;
570 opp-1459200000 {
571 opp-hz = /bits/ 64 <1459200000>;
572 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>;
575 opp-1497600000 {
576 opp-hz = /bits/ 64 <1497600000>;
577 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
580 opp-1574400000 {
581 opp-hz = /bits/ 64 <1574400000>;
582 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
585 opp-1651200000 {
586 opp-hz = /bits/ 64 <1651200000>;
587 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>;
590 opp-1728000000 {
591 opp-hz = /bits/ 64 <1728000000>;
592 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>;
595 opp-1804800000 {
596 opp-hz = /bits/ 64 <1804800000>;
597 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>;
600 opp-1881600000 {
601 opp-hz = /bits/ 64 <1881600000>;
602 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>;
605 opp-1958400000 {
606 opp-hz = /bits/ 64 <1958400000>;
607 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>;
611 dummy_eud: dummy-sink {
612 compatible = "arm,coresight-dummy-sink";
614 in-ports {
617 remote-endpoint = <&swao_rep_out1>;
625 compatible = "qcom,scm-qcs8300", "qcom,scm";
626 qcom,dload-mode = <&tcsr 0x13000>;
636 clk_virt: interconnect-0 {
637 compatible = "qcom,qcs8300-clk-virt";
638 #interconnect-cells = <2>;
639 qcom,bcm-voters = <&apps_bcm_voter>;
642 mc_virt: interconnect-1 {
643 compatible = "qcom,qcs8300-mc-virt";
644 #interconnect-cells = <2>;
645 qcom,bcm-voters = <&apps_bcm_voter>;
648 qup_opp_table: opp-table-qup {
649 compatible = "operating-points-v2";
651 opp-120000000 {
652 opp-hz = /bits/ 64 <120000000>;
653 required-opps = <&rpmhpd_opp_svs_l1>;
657 pmu-a55 {
658 compatible = "arm,cortex-a55-pmu";
662 pmu-a78 {
663 compatible = "arm,cortex-a78-pmu";
668 compatible = "arm,psci-1.0";
671 cpu_pd0: power-domain-cpu0 {
672 #power-domain-cells = <0>;
673 power-domains = <&cluster_pd0>;
674 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
677 cpu_pd1: power-domain-cpu1 {
678 #power-domain-cells = <0>;
679 power-domains = <&cluster_pd0>;
680 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
683 cpu_pd2: power-domain-cpu2 {
684 #power-domain-cells = <0>;
685 power-domains = <&cluster_pd0>;
686 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
689 cpu_pd3: power-domain-cpu3 {
690 #power-domain-cells = <0>;
691 power-domains = <&cluster_pd0>;
692 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
695 cpu_pd4: power-domain-cpu4 {
696 #power-domain-cells = <0>;
697 power-domains = <&cluster_pd1>;
698 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
701 cpu_pd5: power-domain-cpu5 {
702 #power-domain-cells = <0>;
703 power-domains = <&cluster_pd1>;
704 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
707 cpu_pd6: power-domain-cpu6 {
708 #power-domain-cells = <0>;
709 power-domains = <&cluster_pd1>;
710 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
713 cpu_pd7: power-domain-cpu7 {
714 #power-domain-cells = <0>;
715 power-domains = <&cluster_pd1>;
716 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
719 cluster_pd0: power-domain-cluster0 {
720 #power-domain-cells = <0>;
721 power-domains = <&system_pd>;
722 domain-idle-states = <&gold_cluster_sleep>;
725 cluster_pd1: power-domain-cluster1 {
726 #power-domain-cells = <0>;
727 power-domains = <&system_pd>;
728 domain-idle-states = <&silver_cluster_sleep>;
731 system_pd: power-domain-system {
732 #power-domain-cells = <0>;
733 domain-idle-states = <&system_sleep>;
737 reserved-memory {
738 #address-cells = <2>;
739 #size-cells = <2>;
742 aop_image_mem: aop-image-region@90800000 {
744 no-map;
747 aop_cmd_db_mem: aop-cmd-db-region@90860000 {
748 compatible = "qcom,cmd-db";
750 no-map;
756 no-map;
760 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {
762 no-map;
765 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 {
767 no-map;
770 camera_mem: camera-region@95200000 {
772 no-map;
775 adsp_mem: adsp-region@95c00000 {
776 no-map;
780 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 {
782 no-map;
785 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 {
787 no-map;
790 gpdsp_mem: gpdsp-region@97b00000 {
792 no-map;
795 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 {
797 no-map;
800 cdsp_mem: cdsp-region@99980000 {
802 no-map;
805 gpu_microcode_mem: gpu-microcode-region@9b780000 {
807 no-map;
810 cvp_mem: cvp-region@9b782000 {
812 no-map;
815 video_mem: video-region@9be82000 {
817 no-map;
821 smp2p-adsp {
823 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
830 qcom,local-pid = <0>;
831 qcom,remote-pid = <2>;
833 smp2p_adsp_in: slave-kernel {
834 qcom,entry-name = "slave-kernel";
835 interrupt-controller;
836 #interrupt-cells = <2>;
839 smp2p_adsp_out: master-kernel {
840 qcom,entry-name = "master-kernel";
841 #qcom,smem-state-cells = <1>;
845 smp2p-cdsp {
847 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
854 qcom,local-pid = <0>;
855 qcom,remote-pid = <5>;
857 smp2p_cdsp_in: slave-kernel {
858 qcom,entry-name = "slave-kernel";
859 interrupt-controller;
860 #interrupt-cells = <2>;
863 smp2p_cdsp_out: master-kernel {
864 qcom,entry-name = "master-kernel";
865 #qcom,smem-state-cells = <1>;
869 smp2p-gpdsp {
871 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
878 qcom,local-pid = <0>;
879 qcom,remote-pid = <17>;
881 smp2p_gpdsp_in: slave-kernel {
882 qcom,entry-name = "slave-kernel";
883 interrupt-controller;
884 #interrupt-cells = <2>;
887 smp2p_gpdsp_out: master-kernel {
888 qcom,entry-name = "master-kernel";
889 #qcom,smem-state-cells = <1>;
894 compatible = "simple-bus";
896 #address-cells = <2>;
897 #size-cells = <2>;
899 gcc: clock-controller@100000 {
900 compatible = "qcom,qcs8300-gcc";
902 #clock-cells = <1>;
903 #reset-cells = <1>;
904 #power-domain-cells = <1>;
918 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
921 interrupt-controller;
922 #interrupt-cells = <3>;
923 #mbox-cells = <2>;
927 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom";
929 #address-cells = <1>;
930 #size-cells = <1>;
938 gpi_dma0: dma-controller@900000 {
939 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma";
941 #dma-cells = <3>;
955 dma-channels = <12>;
956 dma-channel-mask = <0xfff>;
957 dma-coherent;
962 compatible = "qcom,geni-se-qup";
967 clock-names = "m-ahb",
968 "s-ahb";
969 #address-cells = <2>;
970 #size-cells = <2>;
972 dma-coherent;
976 compatible = "qcom,geni-i2c";
979 clock-names = "se";
980 pinctrl-0 = <&qup_i2c0_data_clk>;
981 pinctrl-names = "default";
983 #address-cells = <1>;
984 #size-cells = <0>;
991 interconnect-names = "qup-core",
992 "qup-config",
993 "qup-memory";
994 power-domains = <&rpmhpd RPMHPD_CX>;
995 required-opps = <&rpmhpd_opp_low_svs>;
998 dma-names = "tx",
1004 compatible = "qcom,geni-spi";
1007 clock-names = "se";
1008 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1009 pinctrl-names = "default";
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1017 interconnect-names = "qup-core",
1018 "qup-config";
1019 power-domains = <&rpmhpd RPMHPD_CX>;
1020 operating-points-v2 = <&qup_opp_table>;
1023 dma-names = "tx",
1029 compatible = "qcom,geni-uart";
1032 clock-names = "se";
1033 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>,
1035 pinctrl-names = "default";
1041 interconnect-names = "qup-core",
1042 "qup-config";
1043 power-domains = <&rpmhpd RPMHPD_CX>;
1044 operating-points-v2 = <&qup_opp_table>;
1049 compatible = "qcom,geni-i2c";
1052 clock-names = "se";
1053 pinctrl-0 = <&qup_i2c1_data_clk>;
1054 pinctrl-names = "default";
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1064 interconnect-names = "qup-core",
1065 "qup-config",
1066 "qup-memory";
1067 power-domains = <&rpmhpd RPMHPD_CX>;
1068 required-opps = <&rpmhpd_opp_low_svs>;
1071 dma-names = "tx",
1077 compatible = "qcom,geni-spi";
1080 clock-names = "se";
1081 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1082 pinctrl-names = "default";
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1090 interconnect-names = "qup-core",
1091 "qup-config";
1092 power-domains = <&rpmhpd RPMHPD_CX>;
1093 operating-points-v2 = <&qup_opp_table>;
1096 dma-names = "tx",
1102 compatible = "qcom,geni-uart";
1105 clock-names = "se";
1106 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>,
1108 pinctrl-names = "default";
1114 interconnect-names = "qup-core",
1115 "qup-config";
1116 power-domains = <&rpmhpd RPMHPD_CX>;
1117 operating-points-v2 = <&qup_opp_table>;
1122 compatible = "qcom,geni-i2c";
1125 clock-names = "se";
1126 pinctrl-0 = <&qup_i2c2_data_clk>;
1127 pinctrl-names = "default";
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1137 interconnect-names = "qup-core",
1138 "qup-config",
1139 "qup-memory";
1140 power-domains = <&rpmhpd RPMHPD_CX>;
1141 required-opps = <&rpmhpd_opp_low_svs>;
1144 dma-names = "tx",
1150 compatible = "qcom,geni-spi";
1153 clock-names = "se";
1154 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1155 pinctrl-names = "default";
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1163 interconnect-names = "qup-core",
1164 "qup-config";
1165 power-domains = <&rpmhpd RPMHPD_CX>;
1166 operating-points-v2 = <&qup_opp_table>;
1169 dma-names = "tx",
1175 compatible = "qcom,geni-uart";
1178 clock-names = "se";
1179 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
1181 pinctrl-names = "default";
1187 interconnect-names = "qup-core",
1188 "qup-config";
1189 power-domains = <&rpmhpd RPMHPD_CX>;
1190 operating-points-v2 = <&qup_opp_table>;
1195 compatible = "qcom,geni-i2c";
1198 clock-names = "se";
1199 pinctrl-0 = <&qup_i2c3_data_clk>;
1200 pinctrl-names = "default";
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1210 interconnect-names = "qup-core",
1211 "qup-config",
1212 "qup-memory";
1213 power-domains = <&rpmhpd RPMHPD_CX>;
1214 required-opps = <&rpmhpd_opp_low_svs>;
1217 dma-names = "tx",
1223 compatible = "qcom,geni-spi";
1226 clock-names = "se";
1227 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1228 pinctrl-names = "default";
1230 #address-cells = <1>;
1231 #size-cells = <0>;
1236 interconnect-names = "qup-core",
1237 "qup-config";
1238 power-domains = <&rpmhpd RPMHPD_CX>;
1239 operating-points-v2 = <&qup_opp_table>;
1242 dma-names = "tx",
1248 compatible = "qcom,geni-uart";
1251 clock-names = "se";
1252 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>,
1254 pinctrl-names = "default";
1260 interconnect-names = "qup-core",
1261 "qup-config";
1262 power-domains = <&rpmhpd RPMHPD_CX>;
1263 operating-points-v2 = <&qup_opp_table>;
1268 compatible = "qcom,geni-i2c";
1271 clock-names = "se";
1272 pinctrl-0 = <&qup_i2c4_data_clk>;
1273 pinctrl-names = "default";
1275 #address-cells = <1>;
1276 #size-cells = <0>;
1283 interconnect-names = "qup-core",
1284 "qup-config",
1285 "qup-memory";
1286 power-domains = <&rpmhpd RPMHPD_CX>;
1287 required-opps = <&rpmhpd_opp_low_svs>;
1290 dma-names = "tx",
1296 compatible = "qcom,geni-spi";
1299 clock-names = "se";
1300 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1301 pinctrl-names = "default";
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1309 interconnect-names = "qup-core",
1310 "qup-config";
1311 power-domains = <&rpmhpd RPMHPD_CX>;
1312 operating-points-v2 = <&qup_opp_table>;
1315 dma-names = "tx",
1321 compatible = "qcom,geni-uart";
1324 clock-names = "se";
1325 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
1327 pinctrl-names = "default";
1333 interconnect-names = "qup-core",
1334 "qup-config";
1335 power-domains = <&rpmhpd RPMHPD_CX>;
1336 operating-points-v2 = <&qup_opp_table>;
1341 compatible = "qcom,geni-i2c";
1344 clock-names = "se";
1345 pinctrl-0 = <&qup_i2c5_data_clk>;
1346 pinctrl-names = "default";
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1356 interconnect-names = "qup-core",
1357 "qup-config",
1358 "qup-memory";
1359 power-domains = <&rpmhpd RPMHPD_CX>;
1360 required-opps = <&rpmhpd_opp_low_svs>;
1363 dma-names = "tx",
1369 compatible = "qcom,geni-spi";
1372 clock-names = "se";
1373 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1374 pinctrl-names = "default";
1376 #address-cells = <1>;
1377 #size-cells = <0>;
1382 interconnect-names = "qup-core",
1383 "qup-config";
1384 power-domains = <&rpmhpd RPMHPD_CX>;
1385 operating-points-v2 = <&qup_opp_table>;
1388 dma-names = "tx",
1394 compatible = "qcom,geni-uart";
1397 clock-names = "se";
1398 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>,
1400 pinctrl-names = "default";
1406 interconnect-names = "qup-core",
1407 "qup-config";
1408 power-domains = <&rpmhpd RPMHPD_CX>;
1409 operating-points-v2 = <&qup_opp_table>;
1414 compatible = "qcom,geni-i2c";
1417 clock-names = "se";
1418 pinctrl-0 = <&qup_i2c6_data_clk>;
1419 pinctrl-names = "default";
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1429 interconnect-names = "qup-core",
1430 "qup-config",
1431 "qup-memory";
1432 power-domains = <&rpmhpd RPMHPD_CX>;
1433 required-opps = <&rpmhpd_opp_low_svs>;
1436 dma-names = "tx",
1442 compatible = "qcom,geni-spi";
1445 clock-names = "se";
1446 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1447 pinctrl-names = "default";
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1455 interconnect-names = "qup-core",
1456 "qup-config";
1457 power-domains = <&rpmhpd RPMHPD_CX>;
1458 operating-points-v2 = <&qup_opp_table>;
1461 dma-names = "tx",
1467 compatible = "qcom,geni-uart";
1470 clock-names = "se";
1471 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
1473 pinctrl-names = "default";
1479 interconnect-names = "qup-core",
1480 "qup-config";
1481 power-domains = <&rpmhpd RPMHPD_CX>;
1482 operating-points-v2 = <&qup_opp_table>;
1487 compatible = "qcom,geni-debug-uart";
1490 clock-names = "se";
1491 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1492 pinctrl-names = "default";
1498 interconnect-names = "qup-core",
1499 "qup-config";
1500 power-domains = <&rpmhpd RPMHPD_CX>;
1501 operating-points-v2 = <&qup_opp_table>;
1506 gpi_dma1: dma-controller@a00000 {
1507 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma";
1509 #dma-cells = <3>;
1523 dma-channels = <12>;
1524 dma-channel-mask = <0xfff>;
1525 dma-coherent;
1530 compatible = "qcom,geni-se-qup";
1535 clock-names = "m-ahb",
1536 "s-ahb";
1537 #address-cells = <2>;
1538 #size-cells = <2>;
1540 dma-coherent;
1544 compatible = "qcom,geni-i2c";
1547 clock-names = "se";
1548 pinctrl-0 = <&qup_i2c8_data_clk>;
1549 pinctrl-names = "default";
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1559 interconnect-names = "qup-core",
1560 "qup-config",
1561 "qup-memory";
1562 power-domains = <&rpmhpd RPMHPD_CX>;
1563 required-opps = <&rpmhpd_opp_low_svs>;
1566 dma-names = "tx",
1572 compatible = "qcom,geni-spi";
1575 clock-names = "se";
1576 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1577 pinctrl-names = "default";
1579 #address-cells = <1>;
1580 #size-cells = <0>;
1585 interconnect-names = "qup-core",
1586 "qup-config";
1587 power-domains = <&rpmhpd RPMHPD_CX>;
1588 operating-points-v2 = <&qup_opp_table>;
1591 dma-names = "tx",
1597 compatible = "qcom,geni-uart";
1600 clock-names = "se";
1601 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>,
1603 pinctrl-names = "default";
1609 interconnect-names = "qup-core",
1610 "qup-config";
1611 power-domains = <&rpmhpd RPMHPD_CX>;
1612 operating-points-v2 = <&qup_opp_table>;
1617 compatible = "qcom,geni-i2c";
1620 clock-names = "se";
1621 pinctrl-0 = <&qup_i2c9_data_clk>;
1622 pinctrl-names = "default";
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1632 interconnect-names = "qup-core",
1633 "qup-config",
1634 "qup-memory";
1635 power-domains = <&rpmhpd RPMHPD_CX>;
1636 required-opps = <&rpmhpd_opp_low_svs>;
1639 dma-names = "tx",
1645 compatible = "qcom,geni-spi";
1648 clock-names = "se";
1649 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1650 pinctrl-names = "default";
1652 #address-cells = <1>;
1653 #size-cells = <0>;
1658 interconnect-names = "qup-core",
1659 "qup-config";
1660 power-domains = <&rpmhpd RPMHPD_CX>;
1661 operating-points-v2 = <&qup_opp_table>;
1664 dma-names = "tx",
1670 compatible = "qcom,geni-uart";
1673 clock-names = "se";
1674 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>,
1676 pinctrl-names = "default";
1682 interconnect-names = "qup-core",
1683 "qup-config";
1684 power-domains = <&rpmhpd RPMHPD_CX>;
1685 operating-points-v2 = <&qup_opp_table>;
1690 compatible = "qcom,geni-i2c";
1693 clock-names = "se";
1694 pinctrl-0 = <&qup_i2c10_data_clk>;
1695 pinctrl-names = "default";
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1705 interconnect-names = "qup-core",
1706 "qup-config",
1707 "qup-memory";
1708 power-domains = <&rpmhpd RPMHPD_CX>;
1709 required-opps = <&rpmhpd_opp_low_svs>;
1712 dma-names = "tx",
1718 compatible = "qcom,geni-spi";
1721 clock-names = "se";
1722 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1723 pinctrl-names = "default";
1725 #address-cells = <1>;
1726 #size-cells = <0>;
1731 interconnect-names = "qup-core",
1732 "qup-config";
1733 power-domains = <&rpmhpd RPMHPD_CX>;
1734 operating-points-v2 = <&qup_opp_table>;
1737 dma-names = "tx",
1743 compatible = "qcom,geni-uart";
1746 clock-names = "se";
1747 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>,
1749 pinctrl-names = "default";
1755 interconnect-names = "qup-core",
1756 "qup-config";
1757 power-domains = <&rpmhpd RPMHPD_CX>;
1758 operating-points-v2 = <&qup_opp_table>;
1763 compatible = "qcom,geni-i2c";
1766 clock-names = "se";
1767 pinctrl-0 = <&qup_i2c11_data_clk>;
1768 pinctrl-names = "default";
1770 #address-cells = <1>;
1771 #size-cells = <0>;
1778 interconnect-names = "qup-core",
1779 "qup-config",
1780 "qup-memory";
1781 power-domains = <&rpmhpd RPMHPD_CX>;
1782 required-opps = <&rpmhpd_opp_low_svs>;
1785 dma-names = "tx",
1791 compatible = "qcom,geni-uart";
1794 clock-names = "se";
1795 pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>;
1796 pinctrl-names = "default";
1802 interconnect-names = "qup-core",
1803 "qup-config";
1804 power-domains = <&rpmhpd RPMHPD_CX>;
1805 operating-points-v2 = <&qup_opp_table>;
1810 compatible = "qcom,geni-i2c";
1813 clock-names = "se";
1814 pinctrl-0 = <&qup_i2c12_data_clk>;
1815 pinctrl-names = "default";
1817 #address-cells = <1>;
1818 #size-cells = <0>;
1825 interconnect-names = "qup-core",
1826 "qup-config",
1827 "qup-memory";
1828 power-domains = <&rpmhpd RPMHPD_CX>;
1829 required-opps = <&rpmhpd_opp_low_svs>;
1832 dma-names = "tx",
1838 compatible = "qcom,geni-spi";
1841 clock-names = "se";
1842 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1843 pinctrl-names = "default";
1845 #address-cells = <1>;
1846 #size-cells = <0>;
1851 interconnect-names = "qup-core",
1852 "qup-config";
1853 power-domains = <&rpmhpd RPMHPD_CX>;
1854 operating-points-v2 = <&qup_opp_table>;
1857 dma-names = "tx",
1863 compatible = "qcom,geni-uart";
1866 clock-names = "se";
1867 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>,
1869 pinctrl-names = "default";
1875 interconnect-names = "qup-core",
1876 "qup-config";
1877 power-domains = <&rpmhpd RPMHPD_CX>;
1878 operating-points-v2 = <&qup_opp_table>;
1883 compatible = "qcom,geni-i2c";
1886 clock-names = "se";
1887 pinctrl-0 = <&qup_i2c13_data_clk>;
1888 pinctrl-names = "default";
1890 #address-cells = <1>;
1891 #size-cells = <0>;
1898 interconnect-names = "qup-core",
1899 "qup-config",
1900 "qup-memory";
1901 power-domains = <&rpmhpd RPMHPD_CX>;
1902 required-opps = <&rpmhpd_opp_low_svs>;
1905 dma-names = "tx",
1911 compatible = "qcom,geni-spi";
1914 clock-names = "se";
1915 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1916 pinctrl-names = "default";
1918 #address-cells = <1>;
1919 #size-cells = <0>;
1924 interconnect-names = "qup-core",
1925 "qup-config";
1926 power-domains = <&rpmhpd RPMHPD_CX>;
1927 operating-points-v2 = <&qup_opp_table>;
1930 dma-names = "tx",
1936 compatible = "qcom,geni-uart";
1939 clock-names = "se";
1940 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>,
1942 pinctrl-names = "default";
1948 interconnect-names = "qup-core",
1949 "qup-config";
1950 power-domains = <&rpmhpd RPMHPD_CX>;
1951 operating-points-v2 = <&qup_opp_table>;
1956 compatible = "qcom,geni-i2c";
1959 clock-names = "se";
1960 pinctrl-0 = <&qup_i2c14_data_clk>;
1961 pinctrl-names = "default";
1963 #address-cells = <1>;
1964 #size-cells = <0>;
1971 interconnect-names = "qup-core",
1972 "qup-config",
1973 "qup-memory";
1974 power-domains = <&rpmhpd RPMHPD_CX>;
1975 required-opps = <&rpmhpd_opp_low_svs>;
1978 dma-names = "tx",
1984 compatible = "qcom,geni-spi";
1987 clock-names = "se";
1988 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1989 pinctrl-names = "default";
1991 #address-cells = <1>;
1992 #size-cells = <0>;
1997 interconnect-names = "qup-core",
1998 "qup-config";
1999 power-domains = <&rpmhpd RPMHPD_CX>;
2000 operating-points-v2 = <&qup_opp_table>;
2003 dma-names = "tx",
2009 compatible = "qcom,geni-uart";
2012 clock-names = "se";
2013 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>,
2015 pinctrl-names = "default";
2021 interconnect-names = "qup-core",
2022 "qup-config";
2023 power-domains = <&rpmhpd RPMHPD_CX>;
2024 operating-points-v2 = <&qup_opp_table>;
2029 compatible = "qcom,geni-i2c";
2032 clock-names = "se";
2033 pinctrl-0 = <&qup_i2c15_data_clk>;
2034 pinctrl-names = "default";
2036 #address-cells = <1>;
2037 #size-cells = <0>;
2044 interconnect-names = "qup-core",
2045 "qup-config",
2046 "qup-memory";
2047 power-domains = <&rpmhpd RPMHPD_CX>;
2048 required-opps = <&rpmhpd_opp_low_svs>;
2051 dma-names = "tx",
2057 compatible = "qcom,geni-spi";
2060 clock-names = "se";
2061 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2062 pinctrl-names = "default";
2064 #address-cells = <1>;
2065 #size-cells = <0>;
2070 interconnect-names = "qup-core",
2071 "qup-config";
2072 power-domains = <&rpmhpd RPMHPD_CX>;
2073 operating-points-v2 = <&qup_opp_table>;
2076 dma-names = "tx",
2082 compatible = "qcom,geni-uart";
2085 clock-names = "se";
2086 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>,
2088 pinctrl-names = "default";
2094 interconnect-names = "qup-core",
2095 "qup-config";
2096 power-domains = <&rpmhpd RPMHPD_CX>;
2097 operating-points-v2 = <&qup_opp_table>;
2102 gpi_dma3: dma-controller@b00000 {
2103 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma";
2105 #dma-cells = <3>;
2111 dma-channels = <4>;
2112 dma-channel-mask = <0xf>;
2113 dma-coherent;
2118 compatible = "qcom,geni-se-qup";
2123 clock-names = "m-ahb",
2124 "s-ahb";
2125 #address-cells = <2>;
2126 #size-cells = <2>;
2128 dma-coherent;
2132 compatible = "qcom,geni-i2c";
2135 clock-names = "se";
2136 pinctrl-0 = <&qup_i2c16_data_clk>;
2137 pinctrl-names = "default";
2139 #address-cells = <1>;
2140 #size-cells = <0>;
2147 interconnect-names = "qup-core",
2148 "qup-config",
2149 "qup-memory";
2150 power-domains = <&rpmhpd RPMHPD_CX>;
2151 required-opps = <&rpmhpd_opp_low_svs>;
2154 dma-names = "tx",
2160 compatible = "qcom,geni-spi";
2163 clock-names = "se";
2164 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
2165 pinctrl-names = "default";
2167 #address-cells = <1>;
2168 #size-cells = <0>;
2173 interconnect-names = "qup-core",
2174 "qup-config";
2175 power-domains = <&rpmhpd RPMHPD_CX>;
2176 operating-points-v2 = <&qup_opp_table>;
2179 dma-names = "tx",
2185 compatible = "qcom,geni-uart";
2188 clock-names = "se";
2189 pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>,
2191 pinctrl-names = "default";
2197 interconnect-names = "qup-core",
2198 "qup-config";
2199 power-domains = <&rpmhpd RPMHPD_CX>;
2200 operating-points-v2 = <&qup_opp_table>;
2206 compatible = "qcom,qcs8300-trng", "qcom,trng";
2211 compatible = "qcom,qcs8300-config-noc";
2213 #interconnect-cells = <2>;
2214 qcom,bcm-voters = <&apps_bcm_voter>;
2218 compatible = "qcom,qcs8300-system-noc";
2220 #interconnect-cells = <2>;
2221 qcom,bcm-voters = <&apps_bcm_voter>;
2225 compatible = "qcom,qcs8300-aggre1-noc";
2227 #interconnect-cells = <2>;
2228 qcom,bcm-voters = <&apps_bcm_voter>;
2232 compatible = "qcom,qcs8300-aggre2-noc";
2234 #interconnect-cells = <2>;
2235 qcom,bcm-voters = <&apps_bcm_voter>;
2239 compatible = "qcom,qcs8300-pcie-anoc";
2241 #interconnect-cells = <2>;
2242 qcom,bcm-voters = <&apps_bcm_voter>;
2246 compatible = "qcom,qcs8300-gpdsp-anoc";
2248 #interconnect-cells = <2>;
2249 qcom,bcm-voters = <&apps_bcm_voter>;
2253 compatible = "qcom,qcs8300-mmss-noc";
2255 #interconnect-cells = <2>;
2256 qcom,bcm-voters = <&apps_bcm_voter>;
2259 ufs_mem_hc: ufs@1d84000 {
2260 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
2264 phy-names = "ufsphy";
2265 lanes-per-direction = <2>;
2266 #reset-cells = <1>;
2268 reset-names = "rst";
2270 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
2271 required-opps = <&rpmhpd_opp_nom>;
2274 dma-coherent;
2280 interconnect-names = "ufs-ddr",
2281 "cpu-ufs";
2291 clock-names = "core_clk",
2299 freq-table-hz = <75000000 300000000>,
2312 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy";
2316 * enables the CXO clock to eDP *and* UFS PHY.
2321 clock-names = "ref",
2324 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
2327 reset-names = "ufsphy";
2329 #phy-cells = <0>;
2333 cryptobam: dma-controller@1dc4000 {
2334 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2337 #dma-cells = <1>;
2339 qcom,controlled-remotely;
2340 num-channels = <20>;
2341 qcom,num-ees = <4>;
2347 compatible = "qcom,qcs8300-inline-crypto-engine",
2348 "qcom,inline-crypto-engine";
2354 compatible = "qcom,tcsr-mutex";
2356 #hwlock-cells = <1>;
2360 compatible = "qcom,qcs8300-tcsr", "syscon";
2365 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas";
2368 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2373 interrupt-names = "wdog",
2377 "stop-ack";
2380 clock-names = "xo";
2382 power-domains = <&rpmhpd RPMHPD_LCX>,
2384 power-domain-names = "lcx",
2387 memory-region = <&adsp_mem>;
2391 qcom,smem-states = <&smp2p_adsp_out 0>;
2392 qcom,smem-state-names = "stop";
2396 remoteproc_adsp_glink: glink-edge {
2397 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2404 qcom,remote-pid = <2>;
2408 qcom,glink-channels = "fastrpcglink-apps-dsp";
2410 memory-region = <&adsp_rpc_remote_heap_mem>;
2413 #address-cells = <1>;
2414 #size-cells = <0>;
2416 compute-cb@3 {
2417 compatible = "qcom,fastrpc-compute-cb";
2420 dma-coherent;
2423 compute-cb@4 {
2424 compatible = "qcom,fastrpc-compute-cb";
2427 dma-coherent;
2430 compute-cb@5 {
2431 compatible = "qcom,fastrpc-compute-cb";
2434 dma-coherent;
2440 qcom,glink-channels = "adsp_apps";
2443 #address-cells = <1>;
2444 #size-cells = <0>;
2449 #sound-dai-cells = <0>;
2450 qcom,protection-domain = "avs/audio",
2454 compatible = "qcom,q6apm-lpass-dais";
2455 #sound-dai-cells = <1>;
2459 compatible = "qcom,q6apm-dais";
2467 qcom,protection-domain = "avs/audio",
2470 q6prmcc: clock-controller {
2471 compatible = "qcom,q6prm-lpass-clocks";
2472 #clock-cells = <2>;
2480 compatible = "qcom,qcs8300-lpass-ag-noc";
2482 #interconnect-cells = <2>;
2483 qcom,bcm-voters = <&apps_bcm_voter>;
2487 compatible = "arm,coresight-stm", "arm,primecell";
2490 reg-names = "stm-base",
2491 "stm-stimulus-base";
2494 clock-names = "apb_pclk";
2496 out-ports {
2499 remote-endpoint = <&funnel0_in7>;
2506 compatible = "qcom,coresight-tpda", "arm,primecell";
2510 clock-names = "apb_pclk";
2512 in-ports {
2513 #address-cells = <1>;
2514 #size-cells = <0>;
2520 remote-endpoint = <&qdss_tpdm1_out>;
2525 out-ports {
2528 remote-endpoint = <&funnel0_in6>;
2535 compatible = "qcom,coresight-tpdm", "arm,primecell";
2539 clock-names = "apb_pclk";
2541 qcom,cmb-element-bits = <32>;
2542 qcom,cmb-msrs-num = <32>;
2544 out-ports {
2547 remote-endpoint = <&qdss_tpda_in1>;
2554 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2558 clock-names = "apb_pclk";
2560 in-ports {
2561 #address-cells = <1>;
2562 #size-cells = <0>;
2568 remote-endpoint = <&qdss_tpda_out>;
2576 remote-endpoint = <&stm_out>;
2581 out-ports {
2584 remote-endpoint = <&qdss_funnel_in0>;
2591 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2595 clock-names = "apb_pclk";
2597 in-ports {
2598 #address-cells = <1>;
2599 #size-cells = <0>;
2605 remote-endpoint = <&apss_funnel1_out>;
2613 remote-endpoint = <&dlct0_funnel_out>;
2621 remote-endpoint = <&dlmm_funnel_out>;
2629 remote-endpoint = <&dlst_ch_funnel_out>;
2634 out-ports {
2637 remote-endpoint = <&qdss_funnel_in1>;
2644 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2648 clock-names = "apb_pclk";
2650 in-ports {
2651 #address-cells = <1>;
2652 #size-cells = <0>;
2658 remote-endpoint = <&funnel0_out>;
2666 remote-endpoint = <&funnel1_out>;
2671 out-ports {
2674 remote-endpoint = <&aoss_funnel_in7>;
2681 compatible = "qcom,coresight-tpdm", "arm,primecell";
2685 clock-names = "apb_pclk";
2687 qcom,cmb-element-bits = <32>;
2688 qcom,cmb-msrs-num = <32>;
2690 out-ports {
2693 remote-endpoint = <&dlct0_tpda_in19>;
2700 compatible = "qcom,coresight-tpdm", "arm,primecell";
2704 clock-names = "apb_pclk";
2706 qcom,cmb-element-bits = <64>;
2707 qcom,cmb-msrs-num = <32>;
2708 qcom,dsb-element-bits = <32>;
2709 qcom,dsb-msrs-num = <32>;
2711 out-ports {
2714 remote-endpoint = <&dlct0_tpda_in25>;
2721 compatible = "qcom,coresight-tpdm", "arm,primecell";
2725 clock-names = "apb_pclk";
2727 qcom,dsb-element-bits = <32>;
2728 qcom,dsb-msrs-num = <32>;
2730 out-ports {
2733 remote-endpoint = <&dlst_ch_tpda_in8>;
2740 compatible = "qcom,coresight-tpda", "arm,primecell";
2744 clock-names = "apb_pclk";
2746 in-ports {
2747 #address-cells = <1>;
2748 #size-cells = <0>;
2754 remote-endpoint = <&dlst_ch_tpdm0_out>;
2759 out-ports {
2762 remote-endpoint = <&dlst_ch_funnel_in0>;
2769 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2773 clock-names = "apb_pclk";
2775 in-ports {
2776 #address-cells = <1>;
2777 #size-cells = <0>;
2783 remote-endpoint = <&dlst_ch_tpda_out>;
2791 remote-endpoint = <&dlst_funnel_out>;
2799 remote-endpoint = <&gdsp_funnel_out>;
2804 out-ports {
2807 remote-endpoint = <&funnel1_in7>;
2814 compatible = "qcom,coresight-tpdm", "arm,primecell";
2818 clock-names = "apb_pclk";
2820 qcom,dsb-element-bits = <32>;
2821 qcom,dsb-msrs-num = <32>;
2823 out-ports {
2826 remote-endpoint = <&turing2_funnel_in0>;
2833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2837 clock-names = "apb_pclk";
2839 in-ports {
2842 remote-endpoint = <&turing2_tpdm_out>;
2847 out-ports {
2850 remote-endpoint = <&gdsp_tpda_in5>;
2857 compatible = "qcom,coresight-tpdm", "arm,primecell";
2861 clock-names = "apb_pclk";
2863 qcom,dsb-element-bits = <32>;
2864 qcom,dsb-msrs-num = <32>;
2866 out-ports {
2869 remote-endpoint = <&dlmm_tpda_in27>;
2876 compatible = "qcom,coresight-tpda", "arm,primecell";
2880 clock-names = "apb_pclk";
2882 in-ports {
2883 #address-cells = <1>;
2884 #size-cells = <0>;
2890 remote-endpoint = <&dlmm_tpdm0_out>;
2895 out-ports {
2898 remote-endpoint = <&dlmm_funnel_in0>;
2905 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2909 clock-names = "apb_pclk";
2911 in-ports {
2914 remote-endpoint = <&dlmm_tpda_out>;
2919 out-ports {
2922 remote-endpoint = <&funnel1_in6>;
2929 compatible = "qcom,coresight-tpdm", "arm,primecell";
2933 clock-names = "apb_pclk";
2935 qcom,dsb-element-bits = <32>;
2936 qcom,dsb-msrs-num = <32>;
2938 out-ports {
2941 remote-endpoint = <&dlct0_tpda_in26>;
2948 compatible = "qcom,coresight-tpda", "arm,primecell";
2952 clock-names = "apb_pclk";
2954 in-ports {
2955 #address-cells = <1>;
2956 #size-cells = <0>;
2962 remote-endpoint = <&prng_tpdm_out>;
2970 remote-endpoint = <&pimem_tpdm_out>;
2978 remote-endpoint = <&dlct0_tpdm0_out>;
2983 out-ports {
2986 remote-endpoint = <&dlct0_funnel_in0>;
2993 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2997 clock-names = "apb_pclk";
2999 in-ports {
3000 #address-cells = <1>;
3001 #size-cells = <0>;
3007 remote-endpoint = <&dlct0_tpda_out>;
3015 remote-endpoint = <&ddr_funnel5_out>;
3020 out-ports {
3023 remote-endpoint = <&funnel1_in5>;
3030 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3034 clock-names = "apb_pclk";
3036 in-ports {
3037 #address-cells = <1>;
3038 #size-cells = <0>;
3044 remote-endpoint = <&aoss_tpda_out>;
3052 remote-endpoint = <&qdss_funnel_out>;
3057 out-ports {
3060 remote-endpoint = <&etf0_in>;
3067 compatible = "arm,coresight-tmc", "arm,primecell";
3071 clock-names = "apb_pclk";
3073 in-ports {
3076 remote-endpoint = <&aoss_funnel_out>;
3081 out-ports {
3084 remote-endpoint = <&swao_rep_in>;
3091 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3095 clock-names = "apb_pclk";
3097 in-ports {
3100 remote-endpoint = <&etf0_out>;
3105 out-ports {
3106 #address-cells = <1>;
3107 #size-cells = <0>;
3113 remote-endpoint = <&eud_in>;
3120 compatible = "qcom,coresight-tpda", "arm,primecell";
3124 clock-names = "apb_pclk";
3126 in-ports {
3127 #address-cells = <1>;
3128 #size-cells = <0>;
3134 remote-endpoint = <&aoss_tpdm0_out>;
3142 remote-endpoint = <&aoss_tpdm1_out>;
3150 remote-endpoint = <&aoss_tpdm2_out>;
3158 remote-endpoint = <&aoss_tpdm3_out>;
3166 remote-endpoint = <&aoss_tpdm4_out>;
3171 out-ports {
3174 remote-endpoint = <&aoss_funnel_in6>;
3181 compatible = "qcom,coresight-tpdm", "arm,primecell";
3185 clock-names = "apb_pclk";
3187 qcom,cmb-element-bits = <64>;
3188 qcom,cmb-msrs-num = <32>;
3190 out-ports {
3193 remote-endpoint = <&aoss_tpda_in0>;
3200 compatible = "qcom,coresight-tpdm", "arm,primecell";
3204 clock-names = "apb_pclk";
3206 qcom,cmb-element-bits = <64>;
3207 qcom,cmb-msrs-num = <32>;
3209 out-ports {
3212 remote-endpoint = <&aoss_tpda_in1>;
3219 compatible = "qcom,coresight-tpdm", "arm,primecell";
3223 clock-names = "apb_pclk";
3225 qcom,cmb-element-bits = <64>;
3226 qcom,cmb-msrs-num = <32>;
3228 out-ports {
3231 remote-endpoint = <&aoss_tpda_in2>;
3238 compatible = "qcom,coresight-tpdm", "arm,primecell";
3242 clock-names = "apb_pclk";
3244 qcom,cmb-element-bits = <64>;
3245 qcom,cmb-msrs-num = <32>;
3247 out-ports {
3250 remote-endpoint = <&aoss_tpda_in3>;
3257 compatible = "qcom,coresight-tpdm", "arm,primecell";
3261 clock-names = "apb_pclk";
3263 qcom,dsb-element-bits = <32>;
3264 qcom,dsb-msrs-num = <32>;
3266 out-ports {
3269 remote-endpoint = <&aoss_tpda_in4>;
3276 compatible = "arm,coresight-cti", "arm,primecell";
3280 clock-names = "apb_pclk";
3284 compatible = "qcom,coresight-tpdm", "arm,primecell";
3288 clock-names = "apb_pclk";
3290 qcom,dsb-element-bits = <32>;
3291 qcom,dsb-msrs-num = <32>;
3293 out-ports {
3296 remote-endpoint = <&turing0_tpda_in0>;
3303 compatible = "qcom,coresight-tpda", "arm,primecell";
3307 clock-names = "apb_pclk";
3309 in-ports {
3312 remote-endpoint = <&turing0_tpdm0_out>;
3317 out-ports {
3320 remote-endpoint = <&turing0_funnel_in0>;
3327 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3331 clock-names = "apb_pclk";
3333 in-ports {
3336 remote-endpoint = <&turing0_tpda_out>;
3341 out-ports {
3344 remote-endpoint = <&gdsp_funnel_in4>;
3351 compatible = "arm,coresight-cti", "arm,primecell";
3355 clock-names = "apb_pclk";
3359 compatible = "qcom,coresight-tpdm", "arm,primecell";
3363 clock-names = "apb_pclk";
3365 qcom,dsb-element-bits = <32>;
3366 qcom,dsb-msrs-num = <32>;
3368 out-ports {
3371 remote-endpoint = <&gdsp_tpda_in8>;
3378 compatible = "qcom,coresight-tpda", "arm,primecell";
3382 clock-names = "apb_pclk";
3384 in-ports {
3385 #address-cells = <1>;
3386 #size-cells = <0>;
3392 remote-endpoint = <&turing2_funnel_out0>;
3400 remote-endpoint = <&gdsp_tpdm0_out>;
3405 out-ports {
3408 remote-endpoint = <&gdsp_funnel_in0>;
3415 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3419 clock-names = "apb_pclk";
3421 in-ports {
3422 #address-cells = <1>;
3423 #size-cells = <0>;
3429 remote-endpoint = <&gdsp_tpda_out>;
3437 remote-endpoint = <&turing0_funnel_out>;
3442 out-ports {
3445 remote-endpoint = <&dlst_ch_funnel_in6>;
3452 compatible = "qcom,coresight-tpdm", "arm,primecell";
3456 clock-names = "apb_pclk";
3458 qcom,dsb-element-bits = <32>;
3459 qcom,dsb-msrs-num = <32>;
3461 out-ports {
3464 remote-endpoint = <&dlst_tpda_in8>;
3471 compatible = "qcom,coresight-tpda", "arm,primecell";
3475 clock-names = "apb_pclk";
3477 in-ports {
3478 #address-cells = <1>;
3479 #size-cells = <0>;
3485 remote-endpoint = <&dlst_tpdm0_out>;
3490 out-ports {
3493 remote-endpoint = <&dlst_funnel_in0>;
3500 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3504 clock-names = "apb_pclk";
3506 in-ports {
3509 remote-endpoint = <&dlst_tpda_out>;
3514 out-ports {
3517 remote-endpoint = <&dlst_ch_funnel_in4>;
3524 compatible = "qcom,coresight-tpdm", "arm,primecell";
3528 clock-names = "apb_pclk";
3530 qcom,dsb-element-bits = <32>;
3531 qcom,dsb-msrs-num = <32>;
3532 qcom,cmb-element-bits = <32>;
3533 qcom,cmb-msrs-num = <32>;
3535 out-ports {
3538 remote-endpoint = <&ddr_tpda_in4>;
3545 compatible = "qcom,coresight-tpda", "arm,primecell";
3549 clock-names = "apb_pclk";
3551 in-ports {
3552 #address-cells = <1>;
3553 #size-cells = <0>;
3559 remote-endpoint = <&ddr_funnel0_out0>;
3567 remote-endpoint = <&ddr_funnel1_out0>;
3575 remote-endpoint = <&ddr_tpdm3_out>;
3580 out-ports {
3583 remote-endpoint = <&ddr_funnel5_in0>;
3590 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3594 clock-names = "apb_pclk";
3596 in-ports {
3599 remote-endpoint = <&ddr_tpda_out>;
3604 out-ports {
3607 remote-endpoint = <&dlct0_funnel_in4>;
3614 compatible = "qcom,coresight-tpdm", "arm,primecell";
3618 clock-names = "apb_pclk";
3620 qcom,dsb-element-bits = <32>;
3621 qcom,dsb-msrs-num = <32>;
3623 out-ports {
3626 remote-endpoint = <&ddr_funnel0_in0>;
3633 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3637 clock-names = "apb_pclk";
3639 in-ports {
3642 remote-endpoint = <&ddr_tpdm0_out>;
3647 out-ports {
3650 remote-endpoint = <&ddr_tpda_in0>;
3657 compatible = "qcom,coresight-tpdm", "arm,primecell";
3661 clock-names = "apb_pclk";
3663 qcom,dsb-element-bits = <32>;
3664 qcom,dsb-msrs-num = <32>;
3666 out-ports {
3669 remote-endpoint = <&ddr_funnel1_in0>;
3676 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3680 clock-names = "apb_pclk";
3682 in-ports {
3685 remote-endpoint = <&ddr_tpdm1_out>;
3690 out-ports {
3693 remote-endpoint = <&ddr_tpda_in1>;
3705 clock-names = "apb_pclk";
3707 arm,coresight-loses-context-with-cpu;
3708 qcom,skip-power-up;
3710 out-ports {
3713 remote-endpoint = <&apss_funnel0_in0>;
3725 clock-names = "apb_pclk";
3727 arm,coresight-loses-context-with-cpu;
3728 qcom,skip-power-up;
3730 out-ports {
3733 remote-endpoint = <&apss_funnel0_in1>;
3745 clock-names = "apb_pclk";
3747 arm,coresight-loses-context-with-cpu;
3748 qcom,skip-power-up;
3750 out-ports {
3753 remote-endpoint = <&apss_funnel0_in2>;
3765 clock-names = "apb_pclk";
3767 arm,coresight-loses-context-with-cpu;
3768 qcom,skip-power-up;
3770 out-ports {
3773 remote-endpoint = <&apss_funnel0_in3>;
3785 clock-names = "apb_pclk";
3787 arm,coresight-loses-context-with-cpu;
3788 qcom,skip-power-up;
3790 out-ports {
3793 remote-endpoint = <&apss_funnel0_in4>;
3805 clock-names = "apb_pclk";
3807 arm,coresight-loses-context-with-cpu;
3808 qcom,skip-power-up;
3810 out-ports {
3813 remote-endpoint = <&apss_funnel0_in5>;
3825 clock-names = "apb_pclk";
3827 arm,coresight-loses-context-with-cpu;
3828 qcom,skip-power-up;
3830 out-ports {
3833 remote-endpoint = <&apss_funnel0_in6>;
3845 clock-names = "apb_pclk";
3847 arm,coresight-loses-context-with-cpu;
3848 qcom,skip-power-up;
3850 out-ports {
3853 remote-endpoint = <&apss_funnel0_in7>;
3860 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3864 clock-names = "apb_pclk";
3866 in-ports {
3867 #address-cells = <1>;
3868 #size-cells = <0>;
3874 remote-endpoint = <&etm0_out>;
3882 remote-endpoint = <&etm1_out>;
3890 remote-endpoint = <&etm2_out>;
3898 remote-endpoint = <&etm3_out>;
3906 remote-endpoint = <&etm4_out>;
3914 remote-endpoint = <&etm5_out>;
3922 remote-endpoint = <&etm6_out>;
3930 remote-endpoint = <&etm7_out>;
3935 out-ports {
3938 remote-endpoint = <&apss_funnel1_in0>;
3945 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3949 clock-names = "apb_pclk";
3951 in-ports {
3952 #address-cells = <1>;
3953 #size-cells = <0>;
3959 remote-endpoint = <&apss_funnel0_out>;
3967 remote-endpoint = <&apss_tpda_out>;
3972 out-ports {
3975 remote-endpoint = <&funnel1_in4>;
3982 compatible = "arm,coresight-cti", "arm,primecell";
3986 clock-names = "apb_pclk";
3990 compatible = "qcom,coresight-tpdm", "arm,primecell";
3994 clock-names = "apb_pclk";
3996 qcom,cmb-element-bits = <64>;
3997 qcom,cmb-msrs-num = <32>;
3999 out-ports {
4002 remote-endpoint = <&apss_tpda_in3>;
4009 compatible = "qcom,coresight-tpdm", "arm,primecell";
4013 clock-names = "apb_pclk";
4015 qcom,dsb-element-bits = <32>;
4016 qcom,dsb-msrs-num = <32>;
4018 out-ports {
4021 remote-endpoint = <&apss_tpda_in4>;
4028 compatible = "qcom,coresight-tpda", "arm,primecell";
4032 clock-names = "apb_pclk";
4034 in-ports {
4035 #address-cells = <1>;
4036 #size-cells = <0>;
4042 remote-endpoint = <&apss_tpdm0_out>;
4050 remote-endpoint = <&apss_tpdm1_out>;
4058 remote-endpoint = <&apss_tpdm2_out>;
4066 remote-endpoint = <&apss_tpdm3_out>;
4074 remote-endpoint = <&apss_tpdm4_out>;
4079 out-ports {
4082 remote-endpoint = <&apss_funnel1_in3>;
4089 compatible = "qcom,coresight-tpdm", "arm,primecell";
4093 clock-names = "apb_pclk";
4095 qcom,cmb-element-bits = <32>;
4096 qcom,cmb-msrs-num = <32>;
4098 out-ports {
4101 remote-endpoint = <&apss_tpda_in1>;
4108 compatible = "qcom,coresight-tpdm", "arm,primecell";
4112 clock-names = "apb_pclk";
4114 qcom,cmb-element-bits = <32>;
4115 qcom,cmb-msrs-num = <32>;
4117 out-ports {
4120 remote-endpoint = <&apss_tpda_in0>;
4127 compatible = "qcom,coresight-tpdm", "arm,primecell";
4131 clock-names = "apb_pclk";
4133 qcom,dsb-element-bits = <32>;
4134 qcom,dsb-msrs-num = <32>;
4136 out-ports {
4139 remote-endpoint = <&apss_tpda_in2>;
4146 compatible = "arm,coresight-cti", "arm,primecell";
4150 clock-names = "apb_pclk";
4154 compatible = "arm,coresight-cti", "arm,primecell";
4158 clock-names = "apb_pclk";
4162 compatible = "arm,coresight-cti", "arm,primecell";
4166 clock-names = "apb_pclk";
4170 compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5";
4173 reg-names = "hc",
4178 interrupt-names = "hc_irq",
4184 clock-names = "iface",
4190 power-domains = <&rpmhpd RPMHPD_CX>;
4191 operating-points-v2 = <&sdhc1_opp_table>;
4197 interconnect-names = "sdhc-ddr",
4198 "cpu-sdhc";
4200 qcom,dll-config = <0x000f64ee>;
4201 qcom,ddr-config = <0x80040868>;
4202 supports-cqe;
4203 dma-coherent;
4207 sdhc1_opp_table: opp-table {
4208 compatible = "operating-points-v2";
4210 opp-50000000 {
4211 opp-hz = /bits/ 64 <50000000>;
4212 required-opps = <&rpmhpd_opp_low_svs>;
4215 opp-100000000 {
4216 opp-hz = /bits/ 64 <100000000>;
4217 required-opps = <&rpmhpd_opp_svs>;
4220 opp-200000000 {
4221 opp-hz = /bits/ 64 <200000000>;
4222 required-opps = <&rpmhpd_opp_svs_l1>;
4225 opp-384000000 {
4226 opp-hz = /bits/ 64 <384000000>;
4227 required-opps = <&rpmhpd_opp_nom>;
4233 compatible = "qcom,qcs8300-usb-hs-phy",
4234 "qcom,usb-snps-hs-7nm-phy";
4238 clock-names = "ref";
4242 #phy-cells = <0>;
4248 compatible = "qcom,qcs8300-usb-hs-phy",
4249 "qcom,usb-snps-hs-7nm-phy";
4253 clock-names = "ref";
4257 #phy-cells = <0>;
4263 compatible = "qcom,qcs8300-qmp-usb3-uni-phy";
4270 clock-names = "aux",
4277 reset-names = "phy", "phy_phy";
4279 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4281 #clock-cells = <0>;
4282 clock-output-names = "usb3_prim_phy_pipe_clk_src";
4284 #phy-cells = <0>;
4290 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy";
4293 clock-names = "sgmi_ref";
4294 #phy-cells = <0>;
4299 compatible = "qcom,qcs8300-refgen-regulator",
4300 "qcom,sm8250-refgen-regulator";
4305 compatible = "qcom,adreno-623.0", "qcom,adreno";
4309 reg-names = "kgsl_3d0_reg_memory",
4315 operating-points-v2 = <&gpu_opp_table>;
4319 interconnect-names = "gfx-mem";
4320 #cooling-cells = <2>;
4322 nvmem-cells = <&gpu_speed_bin>;
4323 nvmem-cell-names = "speed_bin";
4327 gpu_zap_shader: zap-shader {
4328 memory-region = <&gpu_microcode_mem>;
4331 gpu_opp_table: opp-table {
4332 compatible = "operating-points-v2";
4334 opp-877000000 {
4335 opp-hz = /bits/ 64 <877000000>;
4336 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4337 opp-peak-kBps = <12484375>;
4338 opp-supported-hw = <0x1>;
4341 opp-780000000 {
4342 opp-hz = /bits/ 64 <780000000>;
4343 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4344 opp-peak-kBps = <10687500>;
4345 opp-supported-hw = <0x1>;
4348 opp-599000000 {
4349 opp-hz = /bits/ 64 <599000000>;
4350 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4351 opp-peak-kBps = <8171875>;
4352 opp-supported-hw = <0x3>;
4355 opp-479000000 {
4356 opp-hz = /bits/ 64 <479000000>;
4357 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4358 opp-peak-kBps = <5285156>;
4359 opp-supported-hw = <0x3>;
4365 compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu";
4369 reg-names = "gmu", "rscc", "gmu_pdc";
4372 interrupt-names = "hfi", "gmu";
4379 clock-names = "gmu",
4385 power-domains = <&gpucc GPU_CC_CX_GDSC>,
4387 power-domain-names = "cx",
4390 operating-points-v2 = <&gmu_opp_table>;
4392 gmu_opp_table: opp-table {
4393 compatible = "operating-points-v2";
4395 opp-500000000 {
4396 opp-hz = /bits/ 64 <500000000>;
4397 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4402 gpucc: clock-controller@3d90000 {
4403 compatible = "qcom,qcs8300-gpucc";
4408 clock-names = "bi_tcxo",
4411 #clock-cells = <1>;
4412 #reset-cells = <1>;
4413 #power-domain-cells = <1>;
4417 compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
4418 "qcom,smmu-500", "arm,mmu-500";
4420 #iommu-cells = <2>;
4421 #global-interrupts = <2>;
4444 clock-names = "gcc_gpu_memnoc_gfx_clk",
4451 power-domains = <&gpucc GPU_CC_CX_GDSC>;
4452 dma-coherent;
4456 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4464 operating-points-v2 = <&llcc_bwmon_opp_table>;
4466 llcc_bwmon_opp_table: opp-table {
4467 compatible = "operating-points-v2";
4469 opp-0 {
4470 opp-peak-kBps = <762000>;
4473 opp-1 {
4474 opp-peak-kBps = <1720000>;
4477 opp-2 {
4478 opp-peak-kBps = <2086000>;
4481 opp-3 {
4482 opp-peak-kBps = <2601000>;
4485 opp-4 {
4486 opp-peak-kBps = <2929000>;
4489 opp-5 {
4490 opp-peak-kBps = <5931000>;
4493 opp-6 {
4494 opp-peak-kBps = <6515000>;
4497 opp-7 {
4498 opp-peak-kBps = <7984000>;
4501 opp-8 {
4502 opp-peak-kBps = <10437000>;
4505 opp-9 {
4506 opp-peak-kBps = <12195000>;
4512 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
4518 operating-points-v2 = <&cpu_bwmon_opp_table>;
4520 cpu_bwmon_opp_table: opp-table {
4521 compatible = "operating-points-v2";
4523 opp-0 {
4524 opp-peak-kBps = <9155000>;
4527 opp-1 {
4528 opp-peak-kBps = <12298000>;
4531 opp-2 {
4532 opp-peak-kBps = <14236000>;
4535 opp-3 {
4536 opp-peak-kBps = <16265000>;
4542 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
4548 operating-points-v2 = <&cpu_bwmon_opp_table>;
4552 compatible = "qcom,qcs8300-dc-noc";
4554 #interconnect-cells = <2>;
4555 qcom,bcm-voters = <&apps_bcm_voter>;
4559 compatible = "qcom,qcs8300-gem-noc";
4561 #interconnect-cells = <2>;
4562 qcom,bcm-voters = <&apps_bcm_voter>;
4565 llcc: system-cache-controller@9200000 {
4566 compatible = "qcom,qcs8300-llcc";
4572 reg-names = "llcc0_base",
4581 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3";
4589 clock-names = "cfg_noc",
4595 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4597 assigned-clock-rates = <19200000>, <200000000>;
4599 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
4605 interrupt-names = "dwc_usb3",
4612 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4613 required-opps = <&rpmhpd_opp_nom>;
4620 interconnect-names = "usb-ddr", "apps-usb";
4624 phy-names = "usb2-phy", "usb3-phy";
4626 snps,dis-u1-entry-quirk;
4627 snps,dis-u2-entry-quirk;
4631 wakeup-source;
4637 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3";
4645 clock-names = "cfg_noc",
4651 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4653 assigned-clock-rates = <19200000>, <120000000>;
4655 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
4660 interrupt-names = "dwc_usb3",
4666 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4667 required-opps = <&rpmhpd_opp_nom>;
4675 interconnect-names = "usb-ddr", "apps-usb";
4680 phy-names = "usb2-phy";
4681 maximum-speed = "high-speed";
4683 snps,dis-u1-entry-quirk;
4684 snps,dis-u2-entry-quirk;
4689 qcom,select-utmi-as-pipe-clk;
4690 wakeup-source;
4695 iris: video-codec@aa00000 {
4696 compatible = "qcom,qcs8300-iris";
4701 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
4705 power-domain-names = "venus",
4710 operating-points-v2 = <&iris_opp_table>;
4715 clock-names = "iface",
4723 interconnect-names = "cpu-cfg",
4724 "video-mem";
4726 memory-region = <&video_mem>;
4729 reset-names = "bus";
4733 dma-coherent;
4737 iris_opp_table: opp-table {
4738 compatible = "operating-points-v2";
4740 opp-366000000 {
4741 opp-hz = /bits/ 64 <366000000>;
4742 required-opps = <&rpmhpd_opp_svs_l1>,
4746 opp-444000000 {
4747 opp-hz = /bits/ 64 <444000000>;
4748 required-opps = <&rpmhpd_opp_nom>,
4752 opp-533000000 {
4753 opp-hz = /bits/ 64 <533000000>;
4754 required-opps = <&rpmhpd_opp_turbo>,
4758 opp-560000000 {
4759 opp-hz = /bits/ 64 <560000000>;
4760 required-opps = <&rpmhpd_opp_turbo_l1>,
4766 videocc: clock-controller@abf0000 {
4767 compatible = "qcom,qcs8300-videocc";
4773 power-domains = <&rpmhpd RPMHPD_MMCX>;
4774 #clock-cells = <1>;
4775 #reset-cells = <1>;
4776 #power-domain-cells = <1>;
4779 camcc: clock-controller@ade0000 {
4780 compatible = "qcom,qcs8300-camcc";
4786 power-domains = <&rpmhpd RPMHPD_MMCX>;
4787 #clock-cells = <1>;
4788 #reset-cells = <1>;
4789 #power-domain-cells = <1>;
4792 dispcc: clock-controller@af00000 {
4793 compatible = "qcom,sa8775p-dispcc0";
4801 power-domains = <&rpmhpd RPMHPD_MMCX>;
4802 #clock-cells = <1>;
4803 #reset-cells = <1>;
4804 #power-domain-cells = <1>;
4807 pdc: interrupt-controller@b220000 {
4808 compatible = "qcom,qcs8300-pdc", "qcom,pdc";
4811 interrupt-parent = <&intc>;
4812 #interrupt-cells = <2>;
4813 interrupt-controller;
4814 qcom,pdc-ranges = <0 480 40>,
4854 aoss_qmp: power-management@c300000 {
4855 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp";
4857 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4861 #clock-cells = <0>;
4865 compatible = "qcom,rpmh-stats";
4870 compatible = "qcom,spmi-pmic-arb";
4876 reg-names = "core",
4883 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4884 interrupt-names = "periph_irq";
4885 interrupt-controller;
4886 #interrupt-cells = <4>;
4887 #address-cells = <2>;
4888 #size-cells = <0>;
4892 compatible = "qcom,qcs8300-tlmm";
4895 gpio-controller;
4896 #gpio-cells = <2>;
4897 gpio-ranges = <&tlmm 0 0 134>;
4898 interrupt-controller;
4899 #interrupt-cells = <2>;
4900 wakeup-parent = <&pdc>;
4902 hs0_mi2s_active: hs0-mi2s-active-state {
4905 drive-strength = <8>;
4906 bias-disable;
4909 mi2s1_active: mi2s1-active-state {
4910 data0-pins {
4913 drive-strength = <8>;
4914 bias-disable;
4917 data1-pins {
4920 drive-strength = <8>;
4921 bias-disable;
4924 sclk-pins {
4927 drive-strength = <8>;
4928 bias-disable;
4931 ws-pins {
4934 drive-strength = <8>;
4935 bias-disable;
4939 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4944 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4949 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4954 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4959 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4964 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4969 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4974 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4979 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4984 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4989 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4994 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4999 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5004 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5009 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5014 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
5019 qup_spi0_data_clk: qup-spi0-data-clk-state {
5024 qup_spi0_cs: qup-spi0-cs-state {
5029 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5034 qup_spi1_data_clk: qup-spi1-data-clk-state {
5039 qup_spi1_cs: qup-spi1-cs-state {
5044 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5049 qup_spi2_data_clk: qup-spi2-data-clk-state {
5054 qup_spi2_cs: qup-spi2-cs-state {
5059 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5064 qup_spi3_data_clk: qup-spi3-data-clk-state {
5069 qup_spi3_cs: qup-spi3-cs-state {
5074 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5079 qup_spi4_data_clk: qup-spi4-data-clk-state {
5084 qup_spi4_cs: qup-spi4-cs-state {
5089 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5094 qup_spi5_data_clk: qup-spi5-data-clk-state {
5099 qup_spi5_cs: qup-spi5-cs-state {
5104 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5109 qup_spi6_data_clk: qup-spi6-data-clk-state {
5114 qup_spi6_cs: qup-spi6-cs-state {
5119 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5124 qup_spi8_data_clk: qup-spi8-data-clk-state {
5129 qup_spi8_cs: qup-spi8-cs-state {
5134 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5139 qup_spi9_data_clk: qup-spi9-data-clk-state {
5144 qup_spi9_cs: qup-spi9-cs-state {
5149 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5154 qup_spi10_data_clk: qup-spi10-data-clk-state {
5159 qup_spi10_cs: qup-spi10-cs-state {
5164 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5169 qup_spi12_data_clk: qup-spi12-data-clk-state {
5174 qup_spi12_cs: qup-spi12-cs-state {
5179 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5184 qup_spi13_data_clk: qup-spi13-data-clk-state {
5189 qup_spi13_cs: qup-spi13-cs-state {
5194 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5199 qup_spi14_data_clk: qup-spi14-data-clk-state {
5204 qup_spi14_cs: qup-spi14-cs-state {
5209 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5214 qup_spi15_data_clk: qup-spi15-data-clk-state {
5219 qup_spi15_cs: qup-spi15-cs-state {
5224 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5229 qup_spi16_data_clk: qup-spi16-data-clk-state {
5234 qup_spi16_cs: qup-spi16-cs-state {
5239 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5244 qup_uart0_cts: qup-uart0-cts-state {
5249 qup_uart0_rts: qup-uart0-rts-state {
5254 qup_uart0_tx: qup-uart0-tx-state {
5259 qup_uart0_rx: qup-uart0-rx-state {
5264 qup_uart1_cts: qup-uart1-cts-state {
5269 qup_uart1_rts: qup-uart1-rts-state {
5274 qup_uart1_tx: qup-uart1-tx-state {
5279 qup_uart1_rx: qup-uart1-rx-state {
5284 qup_uart2_cts: qup-uart2-cts-state {
5289 qup_uart2_rts: qup-uart2-rts-state {
5294 qup_uart2_tx: qup-uart2-tx-state {
5299 qup_uart2_rx: qup-uart2-rx-state {
5304 qup_uart3_cts: qup-uart3-cts-state {
5309 qup_uart3_rts: qup-uart3-rts-state {
5314 qup_uart3_tx: qup-uart3-tx-state {
5319 qup_uart3_rx: qup-uart3-rx-state {
5324 qup_uart4_cts: qup-uart4-cts-state {
5329 qup_uart4_rts: qup-uart4-rts-state {
5334 qup_uart4_tx: qup-uart4-tx-state {
5339 qup_uart4_rx: qup-uart4-rx-state {
5344 qup_uart5_cts: qup-uart5-cts-state {
5349 qup_uart5_rts: qup-uart5-rts-state {
5354 qup_uart5_tx: qup-uart5-tx-state {
5359 qup_uart5_rx: qup-uart5-rx-state {
5364 qup_uart6_cts: qup-uart6-cts-state {
5369 qup_uart6_rts: qup-uart6-rts-state {
5374 qup_uart6_tx: qup-uart6-tx-state {
5379 qup_uart6_rx: qup-uart6-rx-state {
5384 qup_uart7_tx: qup-uart7-tx-state {
5389 qup_uart7_rx: qup-uart7-rx-state {
5394 qup_uart8_cts: qup-uart8-cts-state {
5399 qup_uart8_rts: qup-uart8-rts-state {
5404 qup_uart8_tx: qup-uart8-tx-state {
5409 qup_uart8_rx: qup-uart8-rx-state {
5414 qup_uart9_cts: qup-uart9-cts-state {
5419 qup_uart9_rts: qup-uart9-rts-state {
5424 qup_uart9_tx: qup-uart9-tx-state {
5429 qup_uart9_rx: qup-uart9-rx-state {
5434 qup_uart10_cts: qup-uart10-cts-state {
5439 qup_uart10_rts: qup-uart10-rts-state {
5444 qup_uart10_tx: qup-uart10-tx-state {
5449 qup_uart10_rx: qup-uart10-rx-state {
5454 qup_uart11_tx: qup-uart11-tx-state {
5459 qup_uart11_rx: qup-uart11-rx-state {
5464 qup_uart12_cts: qup-uart12-cts-state {
5469 qup_uart12_rts: qup-uart12-rts-state {
5474 qup_uart12_tx: qup-uart12-tx-state {
5479 qup_uart12_rx: qup-uart12-rx-state {
5484 qup_uart13_cts: qup-uart13-cts-state {
5489 qup_uart13_rts: qup-uart13-rts-state {
5494 qup_uart13_tx: qup-uart13-tx-state {
5499 qup_uart13_rx: qup-uart13-rx-state {
5504 qup_uart14_cts: qup-uart14-cts-state {
5509 qup_uart14_rts: qup-uart14-rts-state {
5514 qup_uart14_tx: qup-uart14-tx-state {
5519 qup_uart14_rx: qup-uart14-rx-state {
5524 qup_uart15_cts: qup-uart15-cts-state {
5529 qup_uart15_rts: qup-uart15-rts-state {
5534 qup_uart15_tx: qup-uart15-tx-state {
5539 qup_uart15_rx: qup-uart15-rx-state {
5544 qup_uart16_cts: qup-uart16-cts-state {
5549 qup_uart16_rts: qup-uart16-rts-state {
5554 qup_uart16_tx: qup-uart16-tx-state {
5559 qup_uart16_rx: qup-uart16-rx-state {
5564 sdc1_state_on: sdc1-on-state {
5565 clk-pins {
5567 drive-strength = <16>;
5568 bias-disable;
5571 cmd-pins {
5573 drive-strength = <10>;
5574 bias-pull-up;
5577 data-pins {
5579 drive-strength = <10>;
5580 bias-pull-up;
5583 rclk-pins {
5585 bias-pull-down;
5589 sdc1_state_off: sdc1-off-state {
5590 clk-pins {
5592 drive-strength = <2>;
5593 bias-bus-hold;
5596 cmd-pins {
5598 drive-strength = <2>;
5599 bias-bus-hold;
5602 data-pins {
5604 drive-strength = <2>;
5605 bias-bus-hold;
5608 rclk-pins {
5610 bias-bus-hold;
5616 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd";
5620 #address-cells = <1>;
5621 #size-cells = <1>;
5623 pil-reloc@94c {
5624 compatible = "qcom,pil-reloc-info";
5630 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5633 #iommu-cells = <2>;
5634 #global-interrupts = <2>;
5635 dma-coherent;
5770 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5772 #iommu-cells = <2>;
5773 #global-interrupts = <2>;
5774 dma-coherent;
5844 intc: interrupt-controller@17a00000 {
5845 compatible = "arm,gic-v3";
5849 #interrupt-cells = <3>;
5850 interrupt-controller;
5851 #redistributor-regions = <1>;
5852 redistributor-stride = <0x0 0x20000>;
5856 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt";
5863 compatible = "arm,armv7-timer-mem";
5866 #address-cells = <1>;
5867 #size-cells = <1>;
5872 frame-number = <0>;
5879 frame-number = <1>;
5886 frame-number = <2>;
5893 frame-number = <3>;
5900 frame-number = <4>;
5907 frame-number = <5>;
5914 frame-number = <6>;
5921 compatible = "qcom,rpmh-rsc";
5925 reg-names = "drv-0",
5926 "drv-1",
5927 "drv-2";
5932 power-domains = <&system_pd>;
5935 qcom,tcs-offset = <0xd00>;
5936 qcom,drv-id = <2>;
5937 qcom,tcs-config = <ACTIVE_TCS 2>,
5942 apps_bcm_voter: bcm-voter {
5943 compatible = "qcom,bcm-voter";
5946 rpmhcc: clock-controller {
5947 compatible = "qcom,sa8775p-rpmh-clk";
5948 #clock-cells = <1>;
5950 clock-names = "xo";
5953 rpmhpd: power-controller {
5954 compatible = "qcom,qcs8300-rpmhpd";
5955 #power-domain-cells = <1>;
5956 operating-points-v2 = <&rpmhpd_opp_table>;
5958 rpmhpd_opp_table: opp-table {
5959 compatible = "operating-points-v2";
5961 rpmhpd_opp_ret: opp-0 {
5962 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5965 rpmhpd_opp_min_svs: opp-1 {
5966 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5969 rpmhpd_opp_low_svs: opp-2 {
5970 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5973 rpmhpd_opp_svs: opp-3 {
5974 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5977 rpmhpd_opp_svs_l1: opp-4 {
5978 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5981 rpmhpd_opp_nom: opp-5 {
5982 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5985 rpmhpd_opp_nom_l1: opp-6 {
5986 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5989 rpmhpd_opp_nom_l2: opp-7 {
5990 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5993 rpmhpd_opp_turbo: opp-8 {
5994 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5997 rpmhpd_opp_turbo_l1: opp-9 {
5998 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6005 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3",
6006 "qcom,epss-l3";
6009 clock-names = "xo", "alternate";
6010 #interconnect-cells = <1>;
6014 compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss";
6018 reg-names = "freq-domain0",
6019 "freq-domain1",
6020 "freq-domain2";
6025 interrupt-names = "dcvsh-irq-0",
6026 "dcvsh-irq-1",
6027 "dcvsh-irq-2";
6030 clock-names = "xo", "alternate";
6032 #freq-domain-cells = <1>;
6036 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3",
6037 "qcom,epss-l3";
6040 clock-names = "xo", "alternate";
6041 #interconnect-cells = <1>;
6045 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas";
6048 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
6053 interrupt-names = "wdog",
6057 "stop-ack";
6060 clock-names = "xo";
6062 power-domains = <&rpmhpd RPMHPD_CX>,
6064 power-domain-names = "cx",
6070 memory-region = <&gpdsp_mem>;
6074 qcom,smem-states = <&smp2p_gpdsp_out 0>;
6075 qcom,smem-state-names = "stop";
6079 glink-edge {
6080 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
6087 qcom,remote-pid = <17>;
6092 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos";
6095 reg-names = "stmmaceth", "rgmii";
6099 interrupt-names = "macirq", "sfty";
6105 clock-names = "stmmaceth",
6109 power-domains = <&gcc GCC_EMAC0_GDSC>;
6112 phy-names = "serdes";
6115 dma-coherent;
6119 rx-fifo-depth = <16384>;
6120 tx-fifo-depth = <20480>;
6126 compatible = "qcom,qcs8300-nspa-noc";
6128 #interconnect-cells = <2>;
6129 qcom,bcm-voters = <&apps_bcm_voter>;
6133 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas";
6136 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
6141 interrupt-names = "wdog",
6145 "stop-ack";
6148 clock-names = "xo";
6150 power-domains = <&rpmhpd RPMHPD_CX>,
6154 power-domain-names = "cx",
6161 memory-region = <&cdsp_mem>;
6165 qcom,smem-states = <&smp2p_cdsp_out 0>;
6166 qcom,smem-state-names = "stop";
6170 glink-edge {
6171 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
6178 qcom,remote-pid = <5>;
6182 qcom,glink-channels = "fastrpcglink-apps-dsp";
6184 #address-cells = <1>;
6185 #size-cells = <0>;
6187 compute-cb@1 {
6188 compatible = "qcom,fastrpc-compute-cb";
6192 dma-coherent;
6195 compute-cb@2 {
6196 compatible = "qcom,fastrpc-compute-cb";
6200 dma-coherent;
6203 compute-cb@3 {
6204 compatible = "qcom,fastrpc-compute-cb";
6208 dma-coherent;
6211 compute-cb@4 {
6212 compatible = "qcom,fastrpc-compute-cb";
6216 dma-coherent;
6224 compatible = "arm,armv8-timer";