Lines Matching +full:dload +full:- +full:mode
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
11 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
13 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
16 #include <dt-bindings/dma/qcom-gpi.h>
17 #include <dt-bindings/firmware/qcom,scm.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/interconnect/qcom,icc.h>
20 #include <dt-bindings/interconnect/qcom,osm-l3.h>
21 #include <dt-bindings/interconnect/qcom,sc7280.h>
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 #include <dt-bindings/mailbox/qcom-ipcc.h>
24 #include <dt-bindings/phy/phy-qcom-qmp.h>
25 #include <dt-bindings/power/qcom-rpmpd.h>
26 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
27 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
28 #include <dt-bindings/soc/qcom,apr.h>
29 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
30 #include <dt-bindings/sound/qcom,lpass.h>
31 #include <dt-bindings/sound/qcom,q6afe.h>
32 #include <dt-bindings/sound/qcom,q6asm.h>
33 #include <dt-bindings/thermal/thermal.h>
36 interrupt-parent = <&intc>;
38 #address-cells = <2>;
39 #size-cells = <2>;
81 xo_board: xo-board {
82 compatible = "fixed-clock";
83 clock-frequency = <76800000>;
84 #clock-cells = <0>;
87 sleep_clk: sleep-clk {
88 compatible = "fixed-clock";
89 clock-frequency = <32764>;
90 #clock-cells = <0>;
94 reserved-memory {
95 #address-cells = <2>;
96 #size-cells = <2>;
99 wlan_ce_mem: wlan-ce@4cd000 {
100 no-map;
106 no-map;
111 no-map;
116 no-map;
119 aop_cmd_db_mem: aop-cmd-db@80860000 {
121 compatible = "qcom,cmd-db";
122 no-map;
125 reserved_xbl_uefi_log: xbl-uefi-res@80880000 {
127 no-map;
130 sec_apps_mem: sec-apps@808ff000 {
132 no-map;
137 no-map;
141 no-map;
145 wlan_fw_mem: wlan-fw@80c00000 {
147 no-map;
152 no-map;
157 no-map;
162 no-map;
165 ipa_fw_mem: ipa-fw@8b700000 {
167 no-map;
172 no-map;
177 no-map;
182 no-map;
186 compatible = "qcom,rmtfs-mem";
188 no-map;
190 qcom,client-id = <1>;
196 #address-cells = <2>;
197 #size-cells = <0>;
204 enable-method = "psci";
205 power-domains = <&cpu_pd0>;
206 power-domain-names = "psci";
207 next-level-cache = <&l2_0>;
208 operating-points-v2 = <&cpu0_opp_table>;
209 capacity-dmips-mhz = <1024>;
210 dynamic-power-coefficient = <100>;
213 qcom,freq-domain = <&cpufreq_hw 0>;
214 #cooling-cells = <2>;
215 l2_0: l2-cache {
217 cache-level = <2>;
218 cache-unified;
219 next-level-cache = <&l3_0>;
220 l3_0: l3-cache {
222 cache-level = <3>;
223 cache-unified;
233 enable-method = "psci";
234 power-domains = <&cpu_pd1>;
235 power-domain-names = "psci";
236 next-level-cache = <&l2_100>;
237 operating-points-v2 = <&cpu0_opp_table>;
238 capacity-dmips-mhz = <1024>;
239 dynamic-power-coefficient = <100>;
242 qcom,freq-domain = <&cpufreq_hw 0>;
243 #cooling-cells = <2>;
244 l2_100: l2-cache {
246 cache-level = <2>;
247 cache-unified;
248 next-level-cache = <&l3_0>;
257 enable-method = "psci";
258 power-domains = <&cpu_pd2>;
259 power-domain-names = "psci";
260 next-level-cache = <&l2_200>;
261 operating-points-v2 = <&cpu0_opp_table>;
262 capacity-dmips-mhz = <1024>;
263 dynamic-power-coefficient = <100>;
266 qcom,freq-domain = <&cpufreq_hw 0>;
267 #cooling-cells = <2>;
268 l2_200: l2-cache {
270 cache-level = <2>;
271 cache-unified;
272 next-level-cache = <&l3_0>;
281 enable-method = "psci";
282 power-domains = <&cpu_pd3>;
283 power-domain-names = "psci";
284 next-level-cache = <&l2_300>;
285 operating-points-v2 = <&cpu0_opp_table>;
286 capacity-dmips-mhz = <1024>;
287 dynamic-power-coefficient = <100>;
290 qcom,freq-domain = <&cpufreq_hw 0>;
291 #cooling-cells = <2>;
292 l2_300: l2-cache {
294 cache-level = <2>;
295 cache-unified;
296 next-level-cache = <&l3_0>;
305 enable-method = "psci";
306 power-domains = <&cpu_pd4>;
307 power-domain-names = "psci";
308 next-level-cache = <&l2_400>;
309 operating-points-v2 = <&cpu4_opp_table>;
310 capacity-dmips-mhz = <1946>;
311 dynamic-power-coefficient = <520>;
314 qcom,freq-domain = <&cpufreq_hw 1>;
315 #cooling-cells = <2>;
316 l2_400: l2-cache {
318 cache-level = <2>;
319 cache-unified;
320 next-level-cache = <&l3_0>;
329 enable-method = "psci";
330 power-domains = <&cpu_pd5>;
331 power-domain-names = "psci";
332 next-level-cache = <&l2_500>;
333 operating-points-v2 = <&cpu4_opp_table>;
334 capacity-dmips-mhz = <1946>;
335 dynamic-power-coefficient = <520>;
338 qcom,freq-domain = <&cpufreq_hw 1>;
339 #cooling-cells = <2>;
340 l2_500: l2-cache {
342 cache-level = <2>;
343 cache-unified;
344 next-level-cache = <&l3_0>;
353 enable-method = "psci";
354 power-domains = <&cpu_pd6>;
355 power-domain-names = "psci";
356 next-level-cache = <&l2_600>;
357 operating-points-v2 = <&cpu4_opp_table>;
358 capacity-dmips-mhz = <1946>;
359 dynamic-power-coefficient = <520>;
362 qcom,freq-domain = <&cpufreq_hw 1>;
363 #cooling-cells = <2>;
364 l2_600: l2-cache {
366 cache-level = <2>;
367 cache-unified;
368 next-level-cache = <&l3_0>;
377 enable-method = "psci";
378 power-domains = <&cpu_pd7>;
379 power-domain-names = "psci";
380 next-level-cache = <&l2_700>;
381 operating-points-v2 = <&cpu7_opp_table>;
382 capacity-dmips-mhz = <1985>;
383 dynamic-power-coefficient = <552>;
386 qcom,freq-domain = <&cpufreq_hw 2>;
387 #cooling-cells = <2>;
388 l2_700: l2-cache {
390 cache-level = <2>;
391 cache-unified;
392 next-level-cache = <&l3_0>;
396 cpu-map {
432 idle-states {
433 entry-method = "psci";
435 little_cpu_sleep_0: cpu-sleep-0-0 {
436 compatible = "arm,idle-state";
437 idle-state-name = "little-power-down";
438 arm,psci-suspend-param = <0x40000003>;
439 entry-latency-us = <549>;
440 exit-latency-us = <901>;
441 min-residency-us = <1774>;
442 local-timer-stop;
445 little_cpu_sleep_1: cpu-sleep-0-1 {
446 compatible = "arm,idle-state";
447 idle-state-name = "little-rail-power-down";
448 arm,psci-suspend-param = <0x40000004>;
449 entry-latency-us = <702>;
450 exit-latency-us = <915>;
451 min-residency-us = <4001>;
452 local-timer-stop;
455 big_cpu_sleep_0: cpu-sleep-1-0 {
456 compatible = "arm,idle-state";
457 idle-state-name = "big-power-down";
458 arm,psci-suspend-param = <0x40000003>;
459 entry-latency-us = <523>;
460 exit-latency-us = <1244>;
461 min-residency-us = <2207>;
462 local-timer-stop;
465 big_cpu_sleep_1: cpu-sleep-1-1 {
466 compatible = "arm,idle-state";
467 idle-state-name = "big-rail-power-down";
468 arm,psci-suspend-param = <0x40000004>;
469 entry-latency-us = <526>;
470 exit-latency-us = <1854>;
471 min-residency-us = <5555>;
472 local-timer-stop;
476 domain_idle_states: domain-idle-states {
477 cluster_sleep_apss_off: cluster-sleep-0 {
478 compatible = "domain-idle-state";
479 arm,psci-suspend-param = <0x41000044>;
480 entry-latency-us = <2752>;
481 exit-latency-us = <3048>;
482 min-residency-us = <6118>;
485 cluster_sleep_cx_ret: cluster-sleep-1 {
486 compatible = "domain-idle-state";
487 arm,psci-suspend-param = <0x41001344>;
488 entry-latency-us = <3263>;
489 exit-latency-us = <4562>;
490 min-residency-us = <8467>;
493 cluster_sleep_llcc_off: cluster-sleep-2 {
494 compatible = "domain-idle-state";
495 arm,psci-suspend-param = <0x4100b344>;
496 entry-latency-us = <3638>;
497 exit-latency-us = <6562>;
498 min-residency-us = <9826>;
503 cpu0_opp_table: opp-table-cpu0 {
504 compatible = "operating-points-v2";
505 opp-shared;
507 cpu0_opp_300mhz: opp-300000000 {
508 opp-hz = /bits/ 64 <300000000>;
509 opp-peak-kBps = <800000 9600000>;
512 cpu0_opp_691mhz: opp-691200000 {
513 opp-hz = /bits/ 64 <691200000>;
514 opp-peak-kBps = <800000 17817600>;
517 cpu0_opp_806mhz: opp-806400000 {
518 opp-hz = /bits/ 64 <806400000>;
519 opp-peak-kBps = <800000 20889600>;
522 cpu0_opp_941mhz: opp-940800000 {
523 opp-hz = /bits/ 64 <940800000>;
524 opp-peak-kBps = <1804000 24576000>;
527 cpu0_opp_1152mhz: opp-1152000000 {
528 opp-hz = /bits/ 64 <1152000000>;
529 opp-peak-kBps = <2188000 27033600>;
532 cpu0_opp_1325mhz: opp-1324800000 {
533 opp-hz = /bits/ 64 <1324800000>;
534 opp-peak-kBps = <2188000 33792000>;
537 cpu0_opp_1517mhz: opp-1516800000 {
538 opp-hz = /bits/ 64 <1516800000>;
539 opp-peak-kBps = <3072000 38092800>;
542 cpu0_opp_1651mhz: opp-1651200000 {
543 opp-hz = /bits/ 64 <1651200000>;
544 opp-peak-kBps = <3072000 41779200>;
547 cpu0_opp_1805mhz: opp-1804800000 {
548 opp-hz = /bits/ 64 <1804800000>;
549 opp-peak-kBps = <4068000 48537600>;
552 cpu0_opp_1958mhz: opp-1958400000 {
553 opp-hz = /bits/ 64 <1958400000>;
554 opp-peak-kBps = <4068000 48537600>;
557 cpu0_opp_2016mhz: opp-2016000000 {
558 opp-hz = /bits/ 64 <2016000000>;
559 opp-peak-kBps = <6220000 48537600>;
563 cpu4_opp_table: opp-table-cpu4 {
564 compatible = "operating-points-v2";
565 opp-shared;
567 cpu4_opp_691mhz: opp-691200000 {
568 opp-hz = /bits/ 64 <691200000>;
569 opp-peak-kBps = <1804000 9600000>;
572 cpu4_opp_941mhz: opp-940800000 {
573 opp-hz = /bits/ 64 <940800000>;
574 opp-peak-kBps = <2188000 17817600>;
577 cpu4_opp_1229mhz: opp-1228800000 {
578 opp-hz = /bits/ 64 <1228800000>;
579 opp-peak-kBps = <4068000 24576000>;
582 cpu4_opp_1344mhz: opp-1344000000 {
583 opp-hz = /bits/ 64 <1344000000>;
584 opp-peak-kBps = <4068000 24576000>;
587 cpu4_opp_1517mhz: opp-1516800000 {
588 opp-hz = /bits/ 64 <1516800000>;
589 opp-peak-kBps = <4068000 24576000>;
592 cpu4_opp_1651mhz: opp-1651200000 {
593 opp-hz = /bits/ 64 <1651200000>;
594 opp-peak-kBps = <6220000 38092800>;
597 cpu4_opp_1901mhz: opp-1900800000 {
598 opp-hz = /bits/ 64 <1900800000>;
599 opp-peak-kBps = <6220000 44851200>;
602 cpu4_opp_2054mhz: opp-2054400000 {
603 opp-hz = /bits/ 64 <2054400000>;
604 opp-peak-kBps = <6220000 44851200>;
607 cpu4_opp_2112mhz: opp-2112000000 {
608 opp-hz = /bits/ 64 <2112000000>;
609 opp-peak-kBps = <6220000 44851200>;
612 cpu4_opp_2131mhz: opp-2131200000 {
613 opp-hz = /bits/ 64 <2131200000>;
614 opp-peak-kBps = <6220000 44851200>;
617 cpu4_opp_2208mhz: opp-2208000000 {
618 opp-hz = /bits/ 64 <2208000000>;
619 opp-peak-kBps = <6220000 44851200>;
622 cpu4_opp_2400mhz: opp-2400000000 {
623 opp-hz = /bits/ 64 <2400000000>;
624 opp-peak-kBps = <12787200 48537600>;
627 cpu4_opp_2611mhz: opp-2611200000 {
628 opp-hz = /bits/ 64 <2611200000>;
629 opp-peak-kBps = <12787200 48537600>;
633 cpu7_opp_table: opp-table-cpu7 {
634 compatible = "operating-points-v2";
635 opp-shared;
637 cpu7_opp_806mhz: opp-806400000 {
638 opp-hz = /bits/ 64 <806400000>;
639 opp-peak-kBps = <1804000 9600000>;
642 cpu7_opp_1056mhz: opp-1056000000 {
643 opp-hz = /bits/ 64 <1056000000>;
644 opp-peak-kBps = <2188000 17817600>;
647 cpu7_opp_1325mhz: opp-1324800000 {
648 opp-hz = /bits/ 64 <1324800000>;
649 opp-peak-kBps = <4068000 24576000>;
652 cpu7_opp_1517mhz: opp-1516800000 {
653 opp-hz = /bits/ 64 <1516800000>;
654 opp-peak-kBps = <4068000 24576000>;
657 cpu7_opp_1766mhz: opp-1766400000 {
658 opp-hz = /bits/ 64 <1766400000>;
659 opp-peak-kBps = <6220000 38092800>;
662 cpu7_opp_1862mhz: opp-1862400000 {
663 opp-hz = /bits/ 64 <1862400000>;
664 opp-peak-kBps = <6220000 38092800>;
667 cpu7_opp_2035mhz: opp-2035200000 {
668 opp-hz = /bits/ 64 <2035200000>;
669 opp-peak-kBps = <6220000 38092800>;
672 cpu7_opp_2112mhz: opp-2112000000 {
673 opp-hz = /bits/ 64 <2112000000>;
674 opp-peak-kBps = <6220000 44851200>;
677 cpu7_opp_2208mhz: opp-2208000000 {
678 opp-hz = /bits/ 64 <2208000000>;
679 opp-peak-kBps = <6220000 44851200>;
682 cpu7_opp_2381mhz: opp-2380800000 {
683 opp-hz = /bits/ 64 <2380800000>;
684 opp-peak-kBps = <6832000 44851200>;
687 cpu7_opp_2400mhz: opp-2400000000 {
688 opp-hz = /bits/ 64 <2400000000>;
689 opp-peak-kBps = <12787200 48537600>;
692 cpu7_opp_2515mhz: opp-2515200000 {
693 opp-hz = /bits/ 64 <2515200000>;
694 opp-peak-kBps = <12787200 48537600>;
697 cpu7_opp_2707mhz: opp-2707200000 {
698 opp-hz = /bits/ 64 <2707200000>;
699 opp-peak-kBps = <12787200 48537600>;
702 cpu7_opp_3014mhz: opp-3014400000 {
703 opp-hz = /bits/ 64 <3014400000>;
704 opp-peak-kBps = <12787200 48537600>;
716 compatible = "qcom,scm-sc7280", "qcom,scm";
717 qcom,dload-mode = <&tcsr_2 0x13000>;
722 compatible = "qcom,sc7280-clk-virt";
723 #interconnect-cells = <2>;
724 qcom,bcm-voters = <&apps_bcm_voter>;
729 memory-region = <&smem_mem>;
733 smp2p-adsp {
736 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
742 qcom,local-pid = <0>;
743 qcom,remote-pid = <2>;
745 adsp_smp2p_out: master-kernel {
746 qcom,entry-name = "master-kernel";
747 #qcom,smem-state-cells = <1>;
750 adsp_smp2p_in: slave-kernel {
751 qcom,entry-name = "slave-kernel";
752 interrupt-controller;
753 #interrupt-cells = <2>;
757 smp2p-cdsp {
760 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
766 qcom,local-pid = <0>;
767 qcom,remote-pid = <5>;
769 cdsp_smp2p_out: master-kernel {
770 qcom,entry-name = "master-kernel";
771 #qcom,smem-state-cells = <1>;
774 cdsp_smp2p_in: slave-kernel {
775 qcom,entry-name = "slave-kernel";
776 interrupt-controller;
777 #interrupt-cells = <2>;
781 smp2p-mpss {
784 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
790 qcom,local-pid = <0>;
791 qcom,remote-pid = <1>;
793 modem_smp2p_out: master-kernel {
794 qcom,entry-name = "master-kernel";
795 #qcom,smem-state-cells = <1>;
798 modem_smp2p_in: slave-kernel {
799 qcom,entry-name = "slave-kernel";
800 interrupt-controller;
801 #interrupt-cells = <2>;
804 ipa_smp2p_out: ipa-ap-to-modem {
805 qcom,entry-name = "ipa";
806 #qcom,smem-state-cells = <1>;
809 ipa_smp2p_in: ipa-modem-to-ap {
810 qcom,entry-name = "ipa";
811 interrupt-controller;
812 #interrupt-cells = <2>;
816 smp2p-wpss {
819 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
825 qcom,local-pid = <0>;
826 qcom,remote-pid = <13>;
828 wpss_smp2p_out: master-kernel {
829 qcom,entry-name = "master-kernel";
830 #qcom,smem-state-cells = <1>;
833 wpss_smp2p_in: slave-kernel {
834 qcom,entry-name = "slave-kernel";
835 interrupt-controller;
836 #interrupt-cells = <2>;
839 wlan_smp2p_out: wlan-ap-to-wpss {
840 qcom,entry-name = "wlan";
841 #qcom,smem-state-cells = <1>;
844 wlan_smp2p_in: wlan-wpss-to-ap {
845 qcom,entry-name = "wlan";
846 interrupt-controller;
847 #interrupt-cells = <2>;
851 pmu-a55 {
852 compatible = "arm,cortex-a55-pmu";
856 pmu-a78 {
857 compatible = "arm,cortex-a78-pmu";
862 compatible = "arm,psci-1.0";
865 cpu_pd0: power-domain-cpu0 {
866 #power-domain-cells = <0>;
867 power-domains = <&cluster_pd>;
868 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
871 cpu_pd1: power-domain-cpu1 {
872 #power-domain-cells = <0>;
873 power-domains = <&cluster_pd>;
874 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
877 cpu_pd2: power-domain-cpu2 {
878 #power-domain-cells = <0>;
879 power-domains = <&cluster_pd>;
880 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
883 cpu_pd3: power-domain-cpu3 {
884 #power-domain-cells = <0>;
885 power-domains = <&cluster_pd>;
886 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
889 cpu_pd4: power-domain-cpu4 {
890 #power-domain-cells = <0>;
891 power-domains = <&cluster_pd>;
892 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
895 cpu_pd5: power-domain-cpu5 {
896 #power-domain-cells = <0>;
897 power-domains = <&cluster_pd>;
898 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
901 cpu_pd6: power-domain-cpu6 {
902 #power-domain-cells = <0>;
903 power-domains = <&cluster_pd>;
904 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
907 cpu_pd7: power-domain-cpu7 {
908 #power-domain-cells = <0>;
909 power-domains = <&cluster_pd>;
910 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
913 cluster_pd: power-domain-cluster {
914 #power-domain-cells = <0>;
915 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>;
919 qspi_opp_table: opp-table-qspi {
920 compatible = "operating-points-v2";
922 opp-75000000 {
923 opp-hz = /bits/ 64 <75000000>;
924 required-opps = <&rpmhpd_opp_low_svs>;
927 opp-150000000 {
928 opp-hz = /bits/ 64 <150000000>;
929 required-opps = <&rpmhpd_opp_svs>;
932 opp-200000000 {
933 opp-hz = /bits/ 64 <200000000>;
934 required-opps = <&rpmhpd_opp_svs_l1>;
937 opp-300000000 {
938 opp-hz = /bits/ 64 <300000000>;
939 required-opps = <&rpmhpd_opp_nom>;
943 qup_opp_table: opp-table-qup {
944 compatible = "operating-points-v2";
946 opp-75000000 {
947 opp-hz = /bits/ 64 <75000000>;
948 required-opps = <&rpmhpd_opp_low_svs>;
951 opp-100000000 {
952 opp-hz = /bits/ 64 <100000000>;
953 required-opps = <&rpmhpd_opp_svs>;
956 opp-128000000 {
957 opp-hz = /bits/ 64 <128000000>;
958 required-opps = <&rpmhpd_opp_nom>;
963 #address-cells = <2>;
964 #size-cells = <2>;
966 dma-ranges = <0 0 0 0 0x10 0>;
967 compatible = "simple-bus";
969 gcc: clock-controller@100000 {
970 compatible = "qcom,gcc-sc7280";
977 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
982 #clock-cells = <1>;
983 #reset-cells = <1>;
984 #power-domain-cells = <1>;
985 power-domains = <&rpmhpd SC7280_CX>;
989 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
992 interrupt-controller;
993 #interrupt-cells = <3>;
994 #mbox-cells = <2>;
998 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
1004 clock-names = "core";
1005 power-domains = <&rpmhpd SC7280_MX>;
1006 #address-cells = <1>;
1007 #size-cells = <1>;
1009 gpu_speed_bin: gpu-speed-bin@1e9 {
1016 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
1017 pinctrl-names = "default", "sleep";
1018 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
1019 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
1024 reg-names = "hc", "cqhci";
1029 interrupt-names = "hc_irq", "pwr_irq";
1034 clock-names = "iface", "core", "xo";
1037 interconnect-names = "sdhc-ddr","cpu-sdhc";
1038 power-domains = <&rpmhpd SC7280_CX>;
1039 operating-points-v2 = <&sdhc1_opp_table>;
1041 bus-width = <8>;
1042 supports-cqe;
1043 dma-coherent;
1045 qcom,dll-config = <0x0007642c>;
1046 qcom,ddr-config = <0x80040868>;
1048 mmc-ddr-1_8v;
1049 mmc-hs200-1_8v;
1050 mmc-hs400-1_8v;
1051 mmc-hs400-enhanced-strobe;
1055 sdhc1_opp_table: opp-table {
1056 compatible = "operating-points-v2";
1058 opp-100000000 {
1059 opp-hz = /bits/ 64 <100000000>;
1060 required-opps = <&rpmhpd_opp_low_svs>;
1061 opp-peak-kBps = <1800000 400000>;
1062 opp-avg-kBps = <100000 0>;
1065 opp-384000000 {
1066 opp-hz = /bits/ 64 <384000000>;
1067 required-opps = <&rpmhpd_opp_nom>;
1068 opp-peak-kBps = <5400000 1600000>;
1069 opp-avg-kBps = <390000 0>;
1074 gpi_dma0: dma-controller@900000 {
1075 #dma-cells = <3>;
1076 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1090 dma-channels = <12>;
1091 dma-channel-mask = <0x7f>;
1097 compatible = "qcom,geni-se-qup";
1101 clock-names = "m-ahb", "s-ahb";
1102 #address-cells = <2>;
1103 #size-cells = <2>;
1109 compatible = "qcom,geni-i2c";
1112 clock-names = "se";
1113 pinctrl-names = "default";
1114 pinctrl-0 = <&qup_i2c0_data_clk>;
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1121 interconnect-names = "qup-core", "qup-config",
1122 "qup-memory";
1123 power-domains = <&rpmhpd SC7280_CX>;
1124 required-opps = <&rpmhpd_opp_low_svs>;
1127 dma-names = "tx", "rx";
1132 compatible = "qcom,geni-spi";
1135 clock-names = "se";
1136 pinctrl-names = "default";
1137 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1141 power-domains = <&rpmhpd SC7280_CX>;
1142 operating-points-v2 = <&qup_opp_table>;
1145 interconnect-names = "qup-core", "qup-config";
1148 dma-names = "tx", "rx";
1153 compatible = "qcom,geni-uart";
1156 clock-names = "se";
1157 pinctrl-names = "default";
1158 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1160 power-domains = <&rpmhpd SC7280_CX>;
1161 operating-points-v2 = <&qup_opp_table>;
1164 interconnect-names = "qup-core", "qup-config";
1169 compatible = "qcom,geni-i2c";
1172 clock-names = "se";
1173 pinctrl-names = "default";
1174 pinctrl-0 = <&qup_i2c1_data_clk>;
1176 #address-cells = <1>;
1177 #size-cells = <0>;
1181 interconnect-names = "qup-core", "qup-config",
1182 "qup-memory";
1183 power-domains = <&rpmhpd SC7280_CX>;
1184 required-opps = <&rpmhpd_opp_low_svs>;
1187 dma-names = "tx", "rx";
1192 compatible = "qcom,geni-spi";
1195 clock-names = "se";
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1201 power-domains = <&rpmhpd SC7280_CX>;
1202 operating-points-v2 = <&qup_opp_table>;
1205 interconnect-names = "qup-core", "qup-config";
1208 dma-names = "tx", "rx";
1213 compatible = "qcom,geni-uart";
1216 clock-names = "se";
1217 pinctrl-names = "default";
1218 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1220 power-domains = <&rpmhpd SC7280_CX>;
1221 operating-points-v2 = <&qup_opp_table>;
1224 interconnect-names = "qup-core", "qup-config";
1229 compatible = "qcom,geni-i2c";
1232 clock-names = "se";
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&qup_i2c2_data_clk>;
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1241 interconnect-names = "qup-core", "qup-config",
1242 "qup-memory";
1243 power-domains = <&rpmhpd SC7280_CX>;
1244 required-opps = <&rpmhpd_opp_low_svs>;
1247 dma-names = "tx", "rx";
1252 compatible = "qcom,geni-spi";
1255 clock-names = "se";
1256 pinctrl-names = "default";
1257 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1259 #address-cells = <1>;
1260 #size-cells = <0>;
1261 power-domains = <&rpmhpd SC7280_CX>;
1262 operating-points-v2 = <&qup_opp_table>;
1265 interconnect-names = "qup-core", "qup-config";
1268 dma-names = "tx", "rx";
1273 compatible = "qcom,geni-uart";
1276 clock-names = "se";
1277 pinctrl-names = "default";
1278 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1280 power-domains = <&rpmhpd SC7280_CX>;
1281 operating-points-v2 = <&qup_opp_table>;
1284 interconnect-names = "qup-core", "qup-config";
1289 compatible = "qcom,geni-i2c";
1292 clock-names = "se";
1293 pinctrl-names = "default";
1294 pinctrl-0 = <&qup_i2c3_data_clk>;
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1301 interconnect-names = "qup-core", "qup-config",
1302 "qup-memory";
1303 power-domains = <&rpmhpd SC7280_CX>;
1304 required-opps = <&rpmhpd_opp_low_svs>;
1307 dma-names = "tx", "rx";
1312 compatible = "qcom,geni-spi";
1315 clock-names = "se";
1316 pinctrl-names = "default";
1317 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1319 #address-cells = <1>;
1320 #size-cells = <0>;
1321 power-domains = <&rpmhpd SC7280_CX>;
1322 operating-points-v2 = <&qup_opp_table>;
1325 interconnect-names = "qup-core", "qup-config";
1328 dma-names = "tx", "rx";
1333 compatible = "qcom,geni-uart";
1336 clock-names = "se";
1337 pinctrl-names = "default";
1338 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1340 power-domains = <&rpmhpd SC7280_CX>;
1341 operating-points-v2 = <&qup_opp_table>;
1344 interconnect-names = "qup-core", "qup-config";
1349 compatible = "qcom,geni-i2c";
1352 clock-names = "se";
1353 pinctrl-names = "default";
1354 pinctrl-0 = <&qup_i2c4_data_clk>;
1356 #address-cells = <1>;
1357 #size-cells = <0>;
1361 interconnect-names = "qup-core", "qup-config",
1362 "qup-memory";
1363 power-domains = <&rpmhpd SC7280_CX>;
1364 required-opps = <&rpmhpd_opp_low_svs>;
1367 dma-names = "tx", "rx";
1372 compatible = "qcom,geni-spi";
1375 clock-names = "se";
1376 pinctrl-names = "default";
1377 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1379 #address-cells = <1>;
1380 #size-cells = <0>;
1381 power-domains = <&rpmhpd SC7280_CX>;
1382 operating-points-v2 = <&qup_opp_table>;
1385 interconnect-names = "qup-core", "qup-config";
1388 dma-names = "tx", "rx";
1393 compatible = "qcom,geni-uart";
1396 clock-names = "se";
1397 pinctrl-names = "default";
1398 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1400 power-domains = <&rpmhpd SC7280_CX>;
1401 operating-points-v2 = <&qup_opp_table>;
1404 interconnect-names = "qup-core", "qup-config";
1409 compatible = "qcom,geni-i2c";
1412 clock-names = "se";
1413 pinctrl-names = "default";
1414 pinctrl-0 = <&qup_i2c5_data_clk>;
1416 #address-cells = <1>;
1417 #size-cells = <0>;
1421 interconnect-names = "qup-core", "qup-config",
1422 "qup-memory";
1423 power-domains = <&rpmhpd SC7280_CX>;
1424 required-opps = <&rpmhpd_opp_low_svs>;
1427 dma-names = "tx", "rx";
1432 compatible = "qcom,geni-spi";
1435 clock-names = "se";
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1441 power-domains = <&rpmhpd SC7280_CX>;
1442 operating-points-v2 = <&qup_opp_table>;
1445 interconnect-names = "qup-core", "qup-config";
1448 dma-names = "tx", "rx";
1453 compatible = "qcom,geni-debug-uart";
1456 clock-names = "se";
1457 pinctrl-names = "default";
1458 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
1460 power-domains = <&rpmhpd SC7280_CX>;
1461 operating-points-v2 = <&qup_opp_table>;
1464 interconnect-names = "qup-core", "qup-config";
1469 compatible = "qcom,geni-i2c";
1472 clock-names = "se";
1473 pinctrl-names = "default";
1474 pinctrl-0 = <&qup_i2c6_data_clk>;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1481 interconnect-names = "qup-core", "qup-config",
1482 "qup-memory";
1483 power-domains = <&rpmhpd SC7280_CX>;
1484 required-opps = <&rpmhpd_opp_low_svs>;
1487 dma-names = "tx", "rx";
1492 compatible = "qcom,geni-spi";
1495 clock-names = "se";
1496 pinctrl-names = "default";
1497 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1499 #address-cells = <1>;
1500 #size-cells = <0>;
1501 power-domains = <&rpmhpd SC7280_CX>;
1502 operating-points-v2 = <&qup_opp_table>;
1505 interconnect-names = "qup-core", "qup-config";
1508 dma-names = "tx", "rx";
1513 compatible = "qcom,geni-uart";
1516 clock-names = "se";
1517 pinctrl-names = "default";
1518 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1520 power-domains = <&rpmhpd SC7280_CX>;
1521 operating-points-v2 = <&qup_opp_table>;
1524 interconnect-names = "qup-core", "qup-config";
1529 compatible = "qcom,geni-i2c";
1532 clock-names = "se";
1533 pinctrl-names = "default";
1534 pinctrl-0 = <&qup_i2c7_data_clk>;
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1541 interconnect-names = "qup-core", "qup-config",
1542 "qup-memory";
1543 power-domains = <&rpmhpd SC7280_CX>;
1544 required-opps = <&rpmhpd_opp_low_svs>;
1547 dma-names = "tx", "rx";
1552 compatible = "qcom,geni-spi";
1555 clock-names = "se";
1556 pinctrl-names = "default";
1557 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1559 #address-cells = <1>;
1560 #size-cells = <0>;
1561 power-domains = <&rpmhpd SC7280_CX>;
1562 operating-points-v2 = <&qup_opp_table>;
1565 interconnect-names = "qup-core", "qup-config";
1568 dma-names = "tx", "rx";
1573 compatible = "qcom,geni-uart";
1576 clock-names = "se";
1577 pinctrl-names = "default";
1578 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1580 power-domains = <&rpmhpd SC7280_CX>;
1581 operating-points-v2 = <&qup_opp_table>;
1584 interconnect-names = "qup-core", "qup-config";
1589 gpi_dma1: dma-controller@a00000 {
1590 #dma-cells = <3>;
1591 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1605 dma-channels = <12>;
1606 dma-channel-mask = <0x1e>;
1612 compatible = "qcom,geni-se-qup";
1616 clock-names = "m-ahb", "s-ahb";
1617 #address-cells = <2>;
1618 #size-cells = <2>;
1624 compatible = "qcom,geni-i2c";
1627 clock-names = "se";
1628 pinctrl-names = "default";
1629 pinctrl-0 = <&qup_i2c8_data_clk>;
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1636 interconnect-names = "qup-core", "qup-config",
1637 "qup-memory";
1638 power-domains = <&rpmhpd SC7280_CX>;
1639 required-opps = <&rpmhpd_opp_low_svs>;
1642 dma-names = "tx", "rx";
1647 compatible = "qcom,geni-spi";
1650 clock-names = "se";
1651 pinctrl-names = "default";
1652 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1654 #address-cells = <1>;
1655 #size-cells = <0>;
1656 power-domains = <&rpmhpd SC7280_CX>;
1657 operating-points-v2 = <&qup_opp_table>;
1660 interconnect-names = "qup-core", "qup-config";
1663 dma-names = "tx", "rx";
1668 compatible = "qcom,geni-uart";
1671 clock-names = "se";
1672 pinctrl-names = "default";
1673 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1675 power-domains = <&rpmhpd SC7280_CX>;
1676 operating-points-v2 = <&qup_opp_table>;
1679 interconnect-names = "qup-core", "qup-config";
1684 compatible = "qcom,geni-i2c";
1687 clock-names = "se";
1688 pinctrl-names = "default";
1689 pinctrl-0 = <&qup_i2c9_data_clk>;
1691 #address-cells = <1>;
1692 #size-cells = <0>;
1696 interconnect-names = "qup-core", "qup-config",
1697 "qup-memory";
1698 power-domains = <&rpmhpd SC7280_CX>;
1699 required-opps = <&rpmhpd_opp_low_svs>;
1702 dma-names = "tx", "rx";
1707 compatible = "qcom,geni-spi";
1710 clock-names = "se";
1711 pinctrl-names = "default";
1712 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1714 #address-cells = <1>;
1715 #size-cells = <0>;
1716 power-domains = <&rpmhpd SC7280_CX>;
1717 operating-points-v2 = <&qup_opp_table>;
1720 interconnect-names = "qup-core", "qup-config";
1723 dma-names = "tx", "rx";
1728 compatible = "qcom,geni-uart";
1731 clock-names = "se";
1732 pinctrl-names = "default";
1733 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1735 power-domains = <&rpmhpd SC7280_CX>;
1736 operating-points-v2 = <&qup_opp_table>;
1739 interconnect-names = "qup-core", "qup-config";
1744 compatible = "qcom,geni-i2c";
1747 clock-names = "se";
1748 pinctrl-names = "default";
1749 pinctrl-0 = <&qup_i2c10_data_clk>;
1751 #address-cells = <1>;
1752 #size-cells = <0>;
1756 interconnect-names = "qup-core", "qup-config",
1757 "qup-memory";
1758 power-domains = <&rpmhpd SC7280_CX>;
1759 required-opps = <&rpmhpd_opp_low_svs>;
1762 dma-names = "tx", "rx";
1767 compatible = "qcom,geni-spi";
1770 clock-names = "se";
1771 pinctrl-names = "default";
1772 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1774 #address-cells = <1>;
1775 #size-cells = <0>;
1776 power-domains = <&rpmhpd SC7280_CX>;
1777 operating-points-v2 = <&qup_opp_table>;
1780 interconnect-names = "qup-core", "qup-config";
1783 dma-names = "tx", "rx";
1788 compatible = "qcom,geni-uart";
1791 clock-names = "se";
1792 pinctrl-names = "default";
1793 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1795 power-domains = <&rpmhpd SC7280_CX>;
1796 operating-points-v2 = <&qup_opp_table>;
1799 interconnect-names = "qup-core", "qup-config";
1804 compatible = "qcom,geni-i2c";
1807 clock-names = "se";
1808 pinctrl-names = "default";
1809 pinctrl-0 = <&qup_i2c11_data_clk>;
1811 #address-cells = <1>;
1812 #size-cells = <0>;
1816 interconnect-names = "qup-core", "qup-config",
1817 "qup-memory";
1818 power-domains = <&rpmhpd SC7280_CX>;
1819 required-opps = <&rpmhpd_opp_low_svs>;
1822 dma-names = "tx", "rx";
1827 compatible = "qcom,geni-spi";
1830 clock-names = "se";
1831 pinctrl-names = "default";
1832 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1834 #address-cells = <1>;
1835 #size-cells = <0>;
1836 power-domains = <&rpmhpd SC7280_CX>;
1837 operating-points-v2 = <&qup_opp_table>;
1840 interconnect-names = "qup-core", "qup-config";
1843 dma-names = "tx", "rx";
1848 compatible = "qcom,geni-uart";
1851 clock-names = "se";
1852 pinctrl-names = "default";
1853 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1855 power-domains = <&rpmhpd SC7280_CX>;
1856 operating-points-v2 = <&qup_opp_table>;
1859 interconnect-names = "qup-core", "qup-config";
1864 compatible = "qcom,geni-i2c";
1867 clock-names = "se";
1868 pinctrl-names = "default";
1869 pinctrl-0 = <&qup_i2c12_data_clk>;
1871 #address-cells = <1>;
1872 #size-cells = <0>;
1876 interconnect-names = "qup-core", "qup-config",
1877 "qup-memory";
1878 power-domains = <&rpmhpd SC7280_CX>;
1879 required-opps = <&rpmhpd_opp_low_svs>;
1882 dma-names = "tx", "rx";
1887 compatible = "qcom,geni-spi";
1890 clock-names = "se";
1891 pinctrl-names = "default";
1892 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1894 #address-cells = <1>;
1895 #size-cells = <0>;
1896 power-domains = <&rpmhpd SC7280_CX>;
1897 operating-points-v2 = <&qup_opp_table>;
1900 interconnect-names = "qup-core", "qup-config";
1903 dma-names = "tx", "rx";
1908 compatible = "qcom,geni-uart";
1911 clock-names = "se";
1912 pinctrl-names = "default";
1913 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1915 power-domains = <&rpmhpd SC7280_CX>;
1916 operating-points-v2 = <&qup_opp_table>;
1919 interconnect-names = "qup-core", "qup-config";
1924 compatible = "qcom,geni-i2c";
1927 clock-names = "se";
1928 pinctrl-names = "default";
1929 pinctrl-0 = <&qup_i2c13_data_clk>;
1931 #address-cells = <1>;
1932 #size-cells = <0>;
1936 interconnect-names = "qup-core", "qup-config",
1937 "qup-memory";
1938 power-domains = <&rpmhpd SC7280_CX>;
1939 required-opps = <&rpmhpd_opp_low_svs>;
1942 dma-names = "tx", "rx";
1947 compatible = "qcom,geni-spi";
1950 clock-names = "se";
1951 pinctrl-names = "default";
1952 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1954 #address-cells = <1>;
1955 #size-cells = <0>;
1956 power-domains = <&rpmhpd SC7280_CX>;
1957 operating-points-v2 = <&qup_opp_table>;
1960 interconnect-names = "qup-core", "qup-config";
1963 dma-names = "tx", "rx";
1968 compatible = "qcom,geni-uart";
1971 clock-names = "se";
1972 pinctrl-names = "default";
1973 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1975 power-domains = <&rpmhpd SC7280_CX>;
1976 operating-points-v2 = <&qup_opp_table>;
1979 interconnect-names = "qup-core", "qup-config";
1984 compatible = "qcom,geni-i2c";
1987 clock-names = "se";
1988 pinctrl-names = "default";
1989 pinctrl-0 = <&qup_i2c14_data_clk>;
1991 #address-cells = <1>;
1992 #size-cells = <0>;
1996 interconnect-names = "qup-core", "qup-config",
1997 "qup-memory";
1998 power-domains = <&rpmhpd SC7280_CX>;
1999 required-opps = <&rpmhpd_opp_low_svs>;
2002 dma-names = "tx", "rx";
2007 compatible = "qcom,geni-spi";
2010 clock-names = "se";
2011 pinctrl-names = "default";
2012 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2014 #address-cells = <1>;
2015 #size-cells = <0>;
2016 power-domains = <&rpmhpd SC7280_CX>;
2017 operating-points-v2 = <&qup_opp_table>;
2020 interconnect-names = "qup-core", "qup-config";
2023 dma-names = "tx", "rx";
2028 compatible = "qcom,geni-uart";
2031 clock-names = "se";
2032 pinctrl-names = "default";
2033 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
2035 power-domains = <&rpmhpd SC7280_CX>;
2036 operating-points-v2 = <&qup_opp_table>;
2039 interconnect-names = "qup-core", "qup-config";
2044 compatible = "qcom,geni-i2c";
2047 clock-names = "se";
2048 pinctrl-names = "default";
2049 pinctrl-0 = <&qup_i2c15_data_clk>;
2051 #address-cells = <1>;
2052 #size-cells = <0>;
2056 interconnect-names = "qup-core", "qup-config",
2057 "qup-memory";
2058 power-domains = <&rpmhpd SC7280_CX>;
2059 required-opps = <&rpmhpd_opp_low_svs>;
2062 dma-names = "tx", "rx";
2067 compatible = "qcom,geni-spi";
2070 clock-names = "se";
2071 pinctrl-names = "default";
2072 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2074 #address-cells = <1>;
2075 #size-cells = <0>;
2076 power-domains = <&rpmhpd SC7280_CX>;
2077 operating-points-v2 = <&qup_opp_table>;
2080 interconnect-names = "qup-core", "qup-config";
2083 dma-names = "tx", "rx";
2088 compatible = "qcom,geni-uart";
2091 clock-names = "se";
2092 pinctrl-names = "default";
2093 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2095 power-domains = <&rpmhpd SC7280_CX>;
2096 operating-points-v2 = <&qup_opp_table>;
2099 interconnect-names = "qup-core", "qup-config";
2105 compatible = "qcom,sc7280-trng", "qcom,trng";
2111 compatible = "qcom,sc7280-cnoc2";
2112 #interconnect-cells = <2>;
2113 qcom,bcm-voters = <&apps_bcm_voter>;
2118 compatible = "qcom,sc7280-cnoc3";
2119 #interconnect-cells = <2>;
2120 qcom,bcm-voters = <&apps_bcm_voter>;
2125 compatible = "qcom,sc7280-mc-virt";
2126 #interconnect-cells = <2>;
2127 qcom,bcm-voters = <&apps_bcm_voter>;
2132 compatible = "qcom,sc7280-system-noc";
2133 #interconnect-cells = <2>;
2134 qcom,bcm-voters = <&apps_bcm_voter>;
2138 compatible = "qcom,sc7280-aggre1-noc";
2140 #interconnect-cells = <2>;
2141 qcom,bcm-voters = <&apps_bcm_voter>;
2148 compatible = "qcom,sc7280-aggre2-noc";
2149 #interconnect-cells = <2>;
2150 qcom,bcm-voters = <&apps_bcm_voter>;
2156 compatible = "qcom,sc7280-mmss-noc";
2157 #interconnect-cells = <2>;
2158 qcom,bcm-voters = <&apps_bcm_voter>;
2162 compatible = "qcom,wcn6750-wifi";
2198 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2200 qcom,smem-states = <&wlan_smp2p_out 0>;
2201 qcom,smem-state-names = "wlan-smp2p-out";
2205 compatible = "qcom,pcie-sc7280";
2212 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2214 linux,pci-domain = <0>;
2215 bus-range = <0x00 0xff>;
2216 num-lanes = <1>;
2218 #address-cells = <3>;
2219 #size-cells = <2>;
2233 interrupt-names = "msi0",
2242 #interrupt-cells = <1>;
2243 interrupt-map-mask = <0 0 0 0x7>;
2244 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2262 clock-names = "pipe",
2276 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2280 reset-names = "pci";
2282 power-domains = <&gcc GCC_PCIE_0_GDSC>;
2285 phy-names = "pciephy";
2287 pinctrl-names = "default";
2288 pinctrl-0 = <&pcie0_clkreq_n>;
2289 dma-coherent;
2296 bus-range = <0x01 0xff>;
2298 #address-cells = <3>;
2299 #size-cells = <2>;
2305 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2313 clock-names = "aux",
2319 clock-output-names = "pcie_0_pipe_clk";
2320 #clock-cells = <0>;
2322 #phy-cells = <0>;
2325 reset-names = "phy";
2327 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
2328 assigned-clock-rates = <100000000>;
2334 compatible = "qcom,pcie-sc7280";
2341 reg-names = "parf", "dbi", "elbi", "atu", "config";
2343 linux,pci-domain = <1>;
2344 bus-range = <0x00 0xff>;
2345 num-lanes = <2>;
2347 #address-cells = <3>;
2348 #size-cells = <2>;
2362 interrupt-names = "msi0",
2371 #interrupt-cells = <1>;
2372 interrupt-map-mask = <0 0 0 0x7>;
2373 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2392 clock-names = "pipe",
2406 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2407 assigned-clock-rates = <19200000>;
2410 reset-names = "pci";
2412 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2415 phy-names = "pciephy";
2417 pinctrl-names = "default";
2418 pinctrl-0 = <&pcie1_clkreq_n>;
2420 dma-coherent;
2422 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2430 bus-range = <0x01 0xff>;
2432 #address-cells = <3>;
2433 #size-cells = <2>;
2439 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2446 clock-names = "aux",
2452 clock-output-names = "pcie_1_pipe_clk";
2453 #clock-cells = <0>;
2455 #phy-cells = <0>;
2458 reset-names = "phy";
2460 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2461 assigned-clock-rates = <100000000>;
2467 compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
2468 "jedec,ufs-2.0";
2472 phy-names = "ufsphy";
2473 lanes-per-direction = <2>;
2474 #reset-cells = <1>;
2476 reset-names = "rst";
2478 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
2479 required-opps = <&rpmhpd_opp_nom>;
2482 dma-coherent;
2488 interconnect-names = "ufs-ddr", "cpu-ufs";
2498 clock-names = "core_clk",
2507 operating-points-v2 = <&ufs_opp_table>;
2513 ufs_opp_table: opp-table {
2514 compatible = "operating-points-v2";
2516 opp-75000000 {
2517 opp-hz = /bits/ 64 <75000000>,
2525 required-opps = <&rpmhpd_opp_low_svs>;
2528 opp-150000000 {
2529 opp-hz = /bits/ 64 <150000000>,
2537 required-opps = <&rpmhpd_opp_svs>;
2540 opp-300000000 {
2541 opp-hz = /bits/ 64 <300000000>,
2549 required-opps = <&rpmhpd_opp_nom>;
2555 compatible = "qcom,sc7280-qmp-ufs-phy";
2560 clock-names = "ref", "ref_aux", "qref";
2562 power-domains = <&rpmhpd SC7280_MX>;
2565 reset-names = "ufsphy";
2567 #clock-cells = <1>;
2568 #phy-cells = <0>;
2574 compatible = "qcom,sc7280-inline-crypto-engine",
2575 "qcom,inline-crypto-engine";
2580 cryptobam: dma-controller@1dc4000 {
2581 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2584 #dma-cells = <1>;
2588 qcom,controlled-remotely;
2589 num-channels = <16>;
2590 qcom,num-ees = <4>;
2594 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";
2597 dma-names = "rx", "tx";
2601 interconnect-names = "memory";
2605 compatible = "qcom,sc7280-ipa";
2612 reg-names = "ipa-reg",
2613 "ipa-shared",
2616 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2620 interrupt-names = "ipa",
2622 "ipa-clock-query",
2623 "ipa-setup-ready";
2626 clock-names = "core";
2630 interconnect-names = "memory",
2635 qcom,smem-states = <&ipa_smp2p_out 0>,
2637 qcom,smem-state-names = "ipa-clock-enabled-valid",
2638 "ipa-clock-enabled";
2644 compatible = "qcom,tcsr-mutex";
2646 #hwlock-cells = <1>;
2650 compatible = "qcom,sc7280-tcsr", "syscon";
2655 compatible = "qcom,sc7280-tcsr", "syscon";
2660 compatible = "qcom,sc7280-lpasscc";
2663 reg-names = "qdsp6ss", "top_cc";
2665 clock-names = "iface";
2666 #clock-cells = <1>;
2671 compatible = "qcom,sc7280-lpass-rx-macro";
2674 pinctrl-names = "default";
2675 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2680 clock-names = "mclk", "npl", "fsgen";
2682 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2684 power-domain-names = "macro", "dcodec";
2686 #clock-cells = <0>;
2687 #sound-dai-cells = <1>;
2693 compatible = "qcom,soundwire-v1.6.0";
2698 clock-names = "iface";
2700 qcom,din-ports = <0>;
2701 qcom,dout-ports = <5>;
2704 reset-names = "swr_audio_cgcr";
2706 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2707 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2708 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2709 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2710 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2711 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2712 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2713 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2714 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2716 #sound-dai-cells = <1>;
2717 #address-cells = <2>;
2718 #size-cells = <0>;
2724 compatible = "qcom,sc7280-lpass-tx-macro";
2727 pinctrl-names = "default";
2728 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2733 clock-names = "mclk", "npl", "fsgen";
2735 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2737 power-domain-names = "macro", "dcodec";
2739 #clock-cells = <0>;
2740 #sound-dai-cells = <1>;
2746 compatible = "qcom,soundwire-v1.6.0";
2749 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2752 clock-names = "iface";
2754 qcom,din-ports = <3>;
2755 qcom,dout-ports = <0>;
2758 reset-names = "swr_audio_cgcr";
2760 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2761 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2762 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2763 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2764 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2765 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2766 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2767 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2768 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2770 #sound-dai-cells = <1>;
2771 #address-cells = <2>;
2772 #size-cells = <0>;
2778 compatible = "qcom,sc7280-lpass-wsa-macro";
2786 clock-names = "mclk",
2792 pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>;
2793 pinctrl-names = "default";
2795 #clock-cells = <0>;
2796 clock-output-names = "mclk";
2797 #sound-dai-cells = <1>;
2803 compatible = "qcom,soundwire-v1.6.0";
2808 clock-names = "iface";
2811 reset-names = "swr_audio_cgcr";
2813 qcom,din-ports = <2>;
2814 qcom,dout-ports = <6>;
2816 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07
2818 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2819 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2820 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2821 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2822 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2823 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01
2825 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff
2827 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff
2830 #address-cells = <2>;
2831 #size-cells = <0>;
2832 #sound-dai-cells = <1>;
2837 lpass_audiocc: clock-controller@3300000 {
2838 compatible = "qcom,sc7280-lpassaudiocc";
2843 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2844 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2845 #clock-cells = <1>;
2846 #power-domain-cells = <1>;
2847 #reset-cells = <1>;
2851 compatible = "qcom,sc7280-lpass-va-macro";
2855 clock-names = "mclk";
2857 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2859 power-domain-names = "macro", "dcodec";
2861 #clock-cells = <0>;
2862 #sound-dai-cells = <1>;
2867 lpass_aon: clock-controller@3380000 {
2868 compatible = "qcom,sc7280-lpassaoncc";
2873 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2874 #clock-cells = <1>;
2875 #power-domain-cells = <1>;
2879 lpass_core: clock-controller@3900000 {
2880 compatible = "qcom,sc7280-lpasscorecc";
2883 clock-names = "bi_tcxo";
2884 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2885 #clock-cells = <1>;
2886 #power-domain-cells = <1>;
2891 compatible = "qcom,sc7280-lpass-cpu";
2899 reg-names = "lpass-hdmiif",
2900 "lpass-lpaif",
2901 "lpass-rxtx-cdc-dma-lpm",
2902 "lpass-rxtx-lpaif",
2903 "lpass-va-lpaif",
2904 "lpass-va-cdc-dma-lpm";
2910 power-domains = <&rpmhpd SC7280_LCX>;
2911 power-domain-names = "lcx";
2912 required-opps = <&rpmhpd_opp_nom>;
2924 clock-names = "aon_cc_audio_hm_h",
2935 #sound-dai-cells = <1>;
2936 #address-cells = <1>;
2937 #size-cells = <0>;
2943 interrupt-names = "lpass-irq-lpaif",
2944 "lpass-irq-hdmi",
2945 "lpass-irq-vaif",
2946 "lpass-irq-rxtxif";
2951 slimbam: dma-controller@3a84000 {
2952 compatible = "qcom,bam-v1.7.0";
2955 #dma-cells = <1>;
2956 qcom,controlled-remotely;
2957 num-channels = <31>;
2959 qcom,num-ees = <2>;
2964 slim: slim-ngd@3ac0000 {
2965 compatible = "qcom,slim-ngd-v1.5.0";
2969 dma-names = "rx", "tx";
2971 #address-cells = <1>;
2972 #size-cells = <0>;
2976 lpass_hm: clock-controller@3c00000 {
2977 compatible = "qcom,sc7280-lpasshm";
2980 clock-names = "bi_tcxo";
2981 #clock-cells = <1>;
2982 #power-domain-cells = <1>;
2988 compatible = "qcom,sc7280-lpass-ag-noc";
2989 #interconnect-cells = <2>;
2990 qcom,bcm-voters = <&apps_bcm_voter>;
2994 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2997 gpio-controller;
2998 #gpio-cells = <2>;
2999 gpio-ranges = <&lpass_tlmm 0 0 15>;
3001 lpass_dmic01_clk: dmic01-clk-state {
3004 drive-strength = <8>;
3005 bias-disable;
3008 lpass_dmic01_data: dmic01-data-state {
3011 drive-strength = <8>;
3012 bias-pull-down;
3015 lpass_dmic23_clk: dmic23-clk-state {
3018 drive-strength = <8>;
3019 bias-disable;
3022 lpass_dmic23_data: dmic23-data-state {
3025 drive-strength = <8>;
3026 bias-pull-down;
3029 lpass_rx_swr_clk: rx-swr-clk-state {
3032 drive-strength = <2>;
3033 slew-rate = <1>;
3034 bias-disable;
3037 lpass_rx_swr_data: rx-swr-data-state {
3040 drive-strength = <2>;
3041 slew-rate = <1>;
3042 bias-bus-hold;
3045 lpass_tx_swr_clk: tx-swr-clk-state {
3048 drive-strength = <2>;
3049 slew-rate = <1>;
3050 bias-disable;
3053 lpass_tx_swr_data: tx-swr-data-state {
3056 drive-strength = <2>;
3057 slew-rate = <1>;
3058 bias-bus-hold;
3061 lpass_wsa_swr_clk: wsa-swr-clk-state {
3064 drive-strength = <2>;
3065 slew-rate = <1>;
3066 bias-disable;
3069 lpass_wsa_swr_data: wsa-swr-data-state {
3072 drive-strength = <2>;
3073 slew-rate = <1>;
3074 bias-bus-hold;
3079 compatible = "qcom,adreno-635.0", "qcom,adreno";
3083 reg-names = "kgsl_3d0_reg_memory",
3089 operating-points-v2 = <&gpu_opp_table>;
3092 interconnect-names = "gfx-mem";
3093 #cooling-cells = <2>;
3095 nvmem-cells = <&gpu_speed_bin>;
3096 nvmem-cell-names = "speed_bin";
3100 gpu_zap_shader: zap-shader {
3101 memory-region = <&gpu_zap_mem>;
3104 gpu_opp_table: opp-table {
3105 compatible = "operating-points-v2";
3107 opp-315000000 {
3108 opp-hz = /bits/ 64 <315000000>;
3109 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3110 opp-peak-kBps = <1804000>;
3111 opp-supported-hw = <0x17>;
3114 opp-450000000 {
3115 opp-hz = /bits/ 64 <450000000>;
3116 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3117 opp-peak-kBps = <4068000>;
3118 opp-supported-hw = <0x17>;
3122 opp-550000000-0 {
3123 opp-hz = /bits/ 64 <550000000>;
3124 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3125 opp-peak-kBps = <8368000>;
3126 opp-supported-hw = <0x01>;
3129 opp-550000000-1 {
3130 opp-hz = /bits/ 64 <550000000>;
3131 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3132 opp-peak-kBps = <6832000>;
3133 opp-supported-hw = <0x16>;
3136 opp-608000000 {
3137 opp-hz = /bits/ 64 <608000000>;
3138 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3139 opp-peak-kBps = <8368000>;
3140 opp-supported-hw = <0x16>;
3143 opp-700000000 {
3144 opp-hz = /bits/ 64 <700000000>;
3145 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3146 opp-peak-kBps = <8532000>;
3147 opp-supported-hw = <0x06>;
3150 opp-812000000 {
3151 opp-hz = /bits/ 64 <812000000>;
3152 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3153 opp-peak-kBps = <8532000>;
3154 opp-supported-hw = <0x06>;
3157 opp-840000000 {
3158 opp-hz = /bits/ 64 <840000000>;
3159 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3160 opp-peak-kBps = <8532000>;
3161 opp-supported-hw = <0x02>;
3164 opp-900000000 {
3165 opp-hz = /bits/ 64 <900000000>;
3166 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3167 opp-peak-kBps = <8532000>;
3168 opp-supported-hw = <0x02>;
3174 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
3178 reg-names = "gmu", "rscc", "gmu_pdc";
3181 interrupt-names = "hfi", "gmu";
3189 clock-names = "gmu",
3196 power-domains = <&gpucc GPU_CC_CX_GDSC>,
3198 power-domain-names = "cx",
3201 operating-points-v2 = <&gmu_opp_table>;
3203 gmu_opp_table: opp-table {
3204 compatible = "operating-points-v2";
3206 opp-200000000 {
3207 opp-hz = /bits/ 64 <200000000>;
3208 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3213 gpucc: clock-controller@3d90000 {
3214 compatible = "qcom,sc7280-gpucc";
3219 clock-names = "bi_tcxo",
3222 #clock-cells = <1>;
3223 #reset-cells = <1>;
3224 #power-domain-cells = <1>;
3228 compatible = "qcom,sc7280-dcc", "qcom,dcc";
3234 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
3235 "qcom,smmu-500", "arm,mmu-500";
3237 #iommu-cells = <2>;
3238 #global-interrupts = <2>;
3259 clock-names = "gcc_gpu_memnoc_gfx_clk",
3267 power-domains = <&gpucc GPU_CC_CX_GDSC>;
3268 dma-coherent;
3272 compatible = "qcom,sc7280-tbu";
3274 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>;
3278 compatible = "qcom,sc7280-tbu";
3280 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>;
3284 compatible = "qcom,sc7280-mpss-pas";
3287 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
3293 interrupt-names = "wdog", "fatal", "ready", "handover",
3294 "stop-ack", "shutdown-ack";
3297 clock-names = "xo";
3299 power-domains = <&rpmhpd SC7280_CX>,
3301 power-domain-names = "cx", "mss";
3303 memory-region = <&mpss_mem>;
3307 qcom,smem-states = <&modem_smp2p_out 0>;
3308 qcom,smem-state-names = "stop";
3312 glink-edge {
3313 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
3319 qcom,remote-pid = <1>;
3324 compatible = "arm,coresight-stm", "arm,primecell";
3327 reg-names = "stm-base", "stm-stimulus-base";
3330 clock-names = "apb_pclk";
3332 out-ports {
3335 remote-endpoint = <&funnel0_in7>;
3342 compatible = "qcom,coresight-tpda", "arm,primecell";
3346 clock-names = "apb_pclk";
3348 in-ports {
3349 #address-cells = <1>;
3350 #size-cells = <0>;
3356 remote-endpoint = <&spdm_tpdm_out>;
3361 out-ports {
3364 remote-endpoint = <&qdss_dl_funnel_in0>;
3371 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3375 clock-names = "apb_pclk";
3377 in-ports {
3380 remote-endpoint = <&qdss_tpda_out>;
3385 out-ports {
3388 remote-endpoint = <&funnel0_in6>;
3395 compatible = "qcom,coresight-tpdm", "arm,primecell";
3399 clock-names = "apb_pclk";
3401 qcom,cmb-element-bits = <32>;
3402 qcom,cmb-msrs-num = <32>;
3404 out-ports {
3407 remote-endpoint = <&qdss_tpda_in28>;
3414 compatible = "arm,coresight-cti", "arm,primecell";
3418 clock-names = "apb_pclk";
3422 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3426 clock-names = "apb_pclk";
3428 out-ports {
3431 remote-endpoint = <&merge_funnel_in0>;
3436 in-ports {
3437 #address-cells = <1>;
3438 #size-cells = <0>;
3444 remote-endpoint = <&qdss_dl_funnel_out>;
3451 remote-endpoint = <&stm_out>;
3458 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3462 clock-names = "apb_pclk";
3464 out-ports {
3467 remote-endpoint = <&merge_funnel_in1>;
3472 in-ports {
3473 #address-cells = <1>;
3474 #size-cells = <0>;
3479 remote-endpoint = <&apss_merge_funnel_out>;
3486 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3490 clock-names = "apb_pclk";
3492 out-ports {
3495 remote-endpoint = <&swao_funnel_in>;
3500 in-ports {
3501 #address-cells = <1>;
3502 #size-cells = <0>;
3507 remote-endpoint = <&funnel0_out>;
3514 remote-endpoint = <&funnel1_out>;
3521 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3525 clock-names = "apb_pclk";
3527 out-ports {
3530 remote-endpoint = <&etr_in>;
3535 in-ports {
3538 remote-endpoint = <&swao_replicator_out>;
3545 compatible = "arm,coresight-tmc", "arm,primecell";
3550 clock-names = "apb_pclk";
3551 arm,scatter-gather;
3553 in-ports {
3556 remote-endpoint = <&replicator_out>;
3563 compatible = "arm,coresight-cti", "arm,primecell";
3567 clock-names = "apb_pclk";
3571 compatible = "arm,coresight-cti", "arm,primecell";
3575 clock-names = "apb_pclk";
3579 compatible = "arm,coresight-cti", "arm,primecell";
3583 clock-names = "apb_pclk";
3587 compatible = "arm,coresight-cti", "arm,primecell";
3591 clock-names = "apb_pclk";
3595 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3599 clock-names = "apb_pclk";
3601 out-ports {
3604 remote-endpoint = <&etf_in>;
3609 in-ports {
3610 #address-cells = <1>;
3611 #size-cells = <0>;
3617 remote-endpoint = <&aoss_tpda_out>;
3624 remote-endpoint = <&merge_funnel_out>;
3631 compatible = "arm,coresight-tmc", "arm,primecell";
3635 clock-names = "apb_pclk";
3637 out-ports {
3640 remote-endpoint = <&swao_replicator_in>;
3645 in-ports {
3648 remote-endpoint = <&swao_funnel_out>;
3655 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3659 clock-names = "apb_pclk";
3660 qcom,replicator-loses-context;
3662 out-ports {
3665 remote-endpoint = <&replicator_in>;
3670 in-ports {
3673 remote-endpoint = <&etf_out>;
3680 compatible = "qcom,coresight-tpda", "arm,primecell";
3684 clock-names = "apb_pclk";
3686 in-ports {
3687 #address-cells = <1>;
3688 #size-cells = <0>;
3694 remote-endpoint = <&swao_prio0_tpdm_out>;
3702 remote-endpoint = <&swao_prio1_tpdm_out>;
3710 remote-endpoint = <&swao_prio2_tpdm_out>;
3718 remote-endpoint = <&swao_prio3_tpdm_out>;
3726 remote-endpoint = <&swao_tpdm_out>;
3731 out-ports {
3734 remote-endpoint = <&swao_funnel_in6>;
3741 compatible = "qcom,coresight-tpdm", "arm,primecell";
3745 clock-names = "apb_pclk";
3747 qcom,cmb-element-bits = <64>;
3748 qcom,cmb-msrs-num = <32>;
3750 out-ports {
3753 remote-endpoint = <&aoss_tpda_in0>;
3760 compatible = "qcom,coresight-tpdm", "arm,primecell";
3764 clock-names = "apb_pclk";
3766 qcom,cmb-element-bits = <64>;
3767 qcom,cmb-msrs-num = <32>;
3769 out-ports {
3772 remote-endpoint = <&aoss_tpda_in1>;
3779 compatible = "qcom,coresight-tpdm", "arm,primecell";
3783 clock-names = "apb_pclk";
3785 qcom,cmb-element-bits = <64>;
3786 qcom,cmb-msrs-num = <32>;
3788 out-ports {
3791 remote-endpoint = <&aoss_tpda_in2>;
3798 compatible = "qcom,coresight-tpdm", "arm,primecell";
3802 clock-names = "apb_pclk";
3804 qcom,cmb-element-bits = <64>;
3805 qcom,cmb-msrs-num = <32>;
3807 out-ports {
3810 remote-endpoint = <&aoss_tpda_in3>;
3817 compatible = "qcom,coresight-tpdm", "arm,primecell";
3821 clock-names = "apb_pclk";
3823 qcom,dsb-element-bits = <32>;
3824 qcom,dsb-msrs-num = <32>;
3826 out-ports {
3829 remote-endpoint = <&aoss_tpda_in4>;
3836 compatible = "arm,coresight-cti", "arm,primecell";
3840 clock-names = "apb_pclk";
3844 compatible = "arm,coresight-etm4x", "arm,primecell";
3850 clock-names = "apb_pclk";
3851 arm,coresight-loses-context-with-cpu;
3852 qcom,skip-power-up;
3854 out-ports {
3857 remote-endpoint = <&apss_funnel_in0>;
3864 compatible = "arm,coresight-etm4x", "arm,primecell";
3870 clock-names = "apb_pclk";
3871 arm,coresight-loses-context-with-cpu;
3872 qcom,skip-power-up;
3874 out-ports {
3877 remote-endpoint = <&apss_funnel_in1>;
3884 compatible = "arm,coresight-etm4x", "arm,primecell";
3890 clock-names = "apb_pclk";
3891 arm,coresight-loses-context-with-cpu;
3892 qcom,skip-power-up;
3894 out-ports {
3897 remote-endpoint = <&apss_funnel_in2>;
3904 compatible = "arm,coresight-etm4x", "arm,primecell";
3910 clock-names = "apb_pclk";
3911 arm,coresight-loses-context-with-cpu;
3912 qcom,skip-power-up;
3914 out-ports {
3917 remote-endpoint = <&apss_funnel_in3>;
3924 compatible = "arm,coresight-etm4x", "arm,primecell";
3930 clock-names = "apb_pclk";
3931 arm,coresight-loses-context-with-cpu;
3932 qcom,skip-power-up;
3934 out-ports {
3937 remote-endpoint = <&apss_funnel_in4>;
3944 compatible = "arm,coresight-etm4x", "arm,primecell";
3950 clock-names = "apb_pclk";
3951 arm,coresight-loses-context-with-cpu;
3952 qcom,skip-power-up;
3954 out-ports {
3957 remote-endpoint = <&apss_funnel_in5>;
3964 compatible = "arm,coresight-etm4x", "arm,primecell";
3970 clock-names = "apb_pclk";
3971 arm,coresight-loses-context-with-cpu;
3972 qcom,skip-power-up;
3974 out-ports {
3977 remote-endpoint = <&apss_funnel_in6>;
3984 compatible = "arm,coresight-etm4x", "arm,primecell";
3990 clock-names = "apb_pclk";
3991 arm,coresight-loses-context-with-cpu;
3992 qcom,skip-power-up;
3994 out-ports {
3997 remote-endpoint = <&apss_funnel_in7>;
4004 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4008 clock-names = "apb_pclk";
4010 out-ports {
4013 remote-endpoint = <&apss_merge_funnel_in>;
4018 in-ports {
4019 #address-cells = <1>;
4020 #size-cells = <0>;
4025 remote-endpoint = <&etm0_out>;
4032 remote-endpoint = <&etm1_out>;
4039 remote-endpoint = <&etm2_out>;
4046 remote-endpoint = <&etm3_out>;
4053 remote-endpoint = <&etm4_out>;
4060 remote-endpoint = <&etm5_out>;
4067 remote-endpoint = <&etm6_out>;
4074 remote-endpoint = <&etm7_out>;
4081 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
4085 clock-names = "apb_pclk";
4087 out-ports {
4090 remote-endpoint = <&funnel1_in4>;
4095 in-ports {
4098 remote-endpoint = <&apss_funnel_out>;
4105 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
4106 pinctrl-names = "default", "sleep";
4107 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
4108 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
4116 interrupt-names = "hc_irq", "pwr_irq";
4121 clock-names = "iface", "core", "xo";
4124 interconnect-names = "sdhc-ddr","cpu-sdhc";
4125 power-domains = <&rpmhpd SC7280_CX>;
4126 operating-points-v2 = <&sdhc2_opp_table>;
4128 bus-width = <4>;
4129 dma-coherent;
4131 qcom,dll-config = <0x0007642c>;
4135 sdhc2_opp_table: opp-table {
4136 compatible = "operating-points-v2";
4138 opp-100000000 {
4139 opp-hz = /bits/ 64 <100000000>;
4140 required-opps = <&rpmhpd_opp_low_svs>;
4141 opp-peak-kBps = <1800000 400000>;
4142 opp-avg-kBps = <100000 0>;
4145 opp-202000000 {
4146 opp-hz = /bits/ 64 <202000000>;
4147 required-opps = <&rpmhpd_opp_nom>;
4148 opp-peak-kBps = <5400000 1600000>;
4149 opp-avg-kBps = <200000 0>;
4155 compatible = "qcom,sc7280-usb-hs-phy",
4156 "qcom,usb-snps-hs-7nm-phy";
4159 #phy-cells = <0>;
4162 clock-names = "ref";
4168 compatible = "qcom,sc7280-usb-hs-phy",
4169 "qcom,usb-snps-hs-7nm-phy";
4172 #phy-cells = <0>;
4175 clock-names = "ref";
4181 compatible = "qcom,sc7280-refgen-regulator",
4182 "qcom,sm8250-refgen-regulator";
4187 compatible = "qcom,sc7280-qmp-usb3-dp-phy";
4195 clock-names = "aux",
4202 reset-names = "phy", "common";
4204 #clock-cells = <1>;
4205 #phy-cells = <1>;
4207 orientation-switch;
4210 #address-cells = <1>;
4211 #size-cells = <0>;
4224 remote-endpoint = <&usb_1_dwc3_ss>;
4232 remote-endpoint = <&mdss_dp_out>;
4239 compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3";
4248 clock-names = "cfg_noc",
4254 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4256 assigned-clock-rates = <19200000>, <200000000>;
4258 interrupts-extended = <&intc GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
4263 interrupt-names = "dwc_usb3",
4269 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
4270 required-opps = <&rpmhpd_opp_nom>;
4276 interconnect-names = "usb-ddr", "apps-usb";
4281 snps,dis-u1-entry-quirk;
4282 snps,dis-u2-entry-quirk;
4284 phy-names = "usb2-phy";
4285 maximum-speed = "high-speed";
4286 usb-role-switch;
4290 remote-endpoint = <&eud_ep>;
4296 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
4299 #address-cells = <1>;
4300 #size-cells = <0>;
4304 clock-names = "iface", "core";
4307 interconnect-names = "qspi-config";
4308 power-domains = <&rpmhpd SC7280_CX>;
4309 operating-points-v2 = <&qspi_opp_table>;
4314 compatible = "qcom,sc7280-adsp-pas";
4317 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4323 interrupt-names = "wdog", "fatal", "ready", "handover",
4324 "stop-ack", "shutdown-ack";
4327 clock-names = "xo";
4329 power-domains = <&rpmhpd SC7280_LCX>,
4331 power-domain-names = "lcx", "lmx";
4333 memory-region = <&adsp_mem>;
4337 qcom,smem-states = <&adsp_smp2p_out 0>;
4338 qcom,smem-state-names = "stop";
4342 remoteproc_adsp_glink: glink-edge {
4343 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4351 qcom,remote-pid = <2>;
4354 compatible = "qcom,apr-v2";
4355 qcom,glink-channels = "apr_audio_svc";
4357 #address-cells = <1>;
4358 #size-cells = <0>;
4363 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4369 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4372 compatible = "qcom,q6afe-dais";
4373 #address-cells = <1>;
4374 #size-cells = <0>;
4375 #sound-dai-cells = <1>;
4378 q6afecc: clock-controller {
4379 compatible = "qcom,q6afe-clocks";
4380 #clock-cells = <2>;
4386 #sound-dai-cells = <1>;
4387 qcom,usb-audio-intr-idx = /bits/ 16 <2>;
4394 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4397 compatible = "qcom,q6asm-dais";
4398 #address-cells = <1>;
4399 #size-cells = <0>;
4400 #sound-dai-cells = <1>;
4420 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4423 compatible = "qcom,q6adm-routing";
4424 #sound-dai-cells = <0>;
4431 qcom,glink-channels = "fastrpcglink-apps-dsp";
4433 qcom,non-secure-domain;
4434 #address-cells = <1>;
4435 #size-cells = <0>;
4437 compute-cb@3 {
4438 compatible = "qcom,fastrpc-compute-cb";
4441 dma-coherent;
4444 compute-cb@4 {
4445 compatible = "qcom,fastrpc-compute-cb";
4448 dma-coherent;
4451 compute-cb@5 {
4452 compatible = "qcom,fastrpc-compute-cb";
4455 dma-coherent;
4462 compatible = "qcom,sc7280-wpss-pas";
4465 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
4471 interrupt-names = "wdog", "fatal", "ready", "handover",
4472 "stop-ack", "shutdown-ack";
4475 clock-names = "xo";
4477 power-domains = <&rpmhpd SC7280_CX>,
4479 power-domain-names = "cx", "mx";
4481 memory-region = <&wpss_mem>;
4485 qcom,smem-states = <&wpss_smp2p_out 0>;
4486 qcom,smem-state-names = "stop";
4491 glink-edge {
4492 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
4499 qcom,remote-pid = <13>;
4504 compatible = "qcom,sc7280-llcc-bwmon";
4511 operating-points-v2 = <&llcc_bwmon_opp_table>;
4513 llcc_bwmon_opp_table: opp-table {
4514 compatible = "operating-points-v2";
4516 opp-0 {
4517 opp-peak-kBps = <800000>;
4519 opp-1 {
4520 opp-peak-kBps = <1804000>;
4522 opp-2 {
4523 opp-peak-kBps = <2188000>;
4525 opp-3 {
4526 opp-peak-kBps = <3072000>;
4528 opp-4 {
4529 opp-peak-kBps = <4068000>;
4531 opp-5 {
4532 opp-peak-kBps = <6220000>;
4534 opp-6 {
4535 opp-peak-kBps = <6832000>;
4537 opp-7 {
4538 opp-peak-kBps = <8532000>;
4540 opp-8 {
4541 opp-peak-kBps = <10944000>;
4543 opp-9 {
4544 opp-peak-kBps = <12787200>;
4550 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
4556 operating-points-v2 = <&cpu_bwmon_opp_table>;
4558 cpu_bwmon_opp_table: opp-table {
4559 compatible = "operating-points-v2";
4561 opp-0 {
4562 opp-peak-kBps = <2400000>;
4564 opp-1 {
4565 opp-peak-kBps = <4800000>;
4567 opp-2 {
4568 opp-peak-kBps = <7456000>;
4570 opp-3 {
4571 opp-peak-kBps = <9600000>;
4573 opp-4 {
4574 opp-peak-kBps = <12896000>;
4576 opp-5 {
4577 opp-peak-kBps = <14928000>;
4579 opp-6 {
4580 opp-peak-kBps = <17056000>;
4587 compatible = "qcom,sc7280-dc-noc";
4588 #interconnect-cells = <2>;
4589 qcom,bcm-voters = <&apps_bcm_voter>;
4594 compatible = "qcom,sc7280-gem-noc";
4595 #interconnect-cells = <2>;
4596 qcom,bcm-voters = <&apps_bcm_voter>;
4599 system-cache-controller@9200000 {
4600 compatible = "qcom,sc7280-llcc";
4603 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
4608 compatible = "qcom,sc7280-eud", "qcom,eud";
4611 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
4616 #address-cells = <1>;
4617 #size-cells = <0>;
4622 remote-endpoint = <&usb2_role_switch>;
4630 compatible = "qcom,sc7280-nsp-noc";
4631 #interconnect-cells = <2>;
4632 qcom,bcm-voters = <&apps_bcm_voter>;
4636 compatible = "qcom,sc7280-cdsp-pas";
4639 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4645 interrupt-names = "wdog", "fatal", "ready", "handover",
4646 "stop-ack", "shutdown-ack";
4649 clock-names = "xo";
4651 power-domains = <&rpmhpd SC7280_CX>,
4653 power-domain-names = "cx", "mx";
4657 memory-region = <&cdsp_mem>;
4661 qcom,smem-states = <&cdsp_smp2p_out 0>;
4662 qcom,smem-state-names = "stop";
4666 glink-edge {
4667 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4674 qcom,remote-pid = <5>;
4678 qcom,glink-channels = "fastrpcglink-apps-dsp";
4680 qcom,non-secure-domain;
4681 #address-cells = <1>;
4682 #size-cells = <0>;
4684 compute-cb@1 {
4685 compatible = "qcom,fastrpc-compute-cb";
4689 dma-coherent;
4692 compute-cb@2 {
4693 compatible = "qcom,fastrpc-compute-cb";
4697 dma-coherent;
4700 compute-cb@3 {
4701 compatible = "qcom,fastrpc-compute-cb";
4705 dma-coherent;
4708 compute-cb@4 {
4709 compatible = "qcom,fastrpc-compute-cb";
4713 dma-coherent;
4716 compute-cb@5 {
4717 compatible = "qcom,fastrpc-compute-cb";
4721 dma-coherent;
4724 compute-cb@6 {
4725 compatible = "qcom,fastrpc-compute-cb";
4729 dma-coherent;
4732 compute-cb@7 {
4733 compatible = "qcom,fastrpc-compute-cb";
4737 dma-coherent;
4740 compute-cb@8 {
4741 compatible = "qcom,fastrpc-compute-cb";
4745 dma-coherent;
4750 compute-cb@11 {
4751 compatible = "qcom,fastrpc-compute-cb";
4755 dma-coherent;
4758 compute-cb@12 {
4759 compatible = "qcom,fastrpc-compute-cb";
4763 dma-coherent;
4766 compute-cb@13 {
4767 compatible = "qcom,fastrpc-compute-cb";
4771 dma-coherent;
4774 compute-cb@14 {
4775 compatible = "qcom,fastrpc-compute-cb";
4779 dma-coherent;
4786 compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3";
4795 clock-names = "cfg_noc",
4801 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4803 assigned-clock-rates = <19200000>, <200000000>;
4805 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
4811 interrupt-names = "dwc_usb3",
4818 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4819 required-opps = <&rpmhpd_opp_nom>;
4825 interconnect-names = "usb-ddr", "apps-usb";
4827 wakeup-source;
4832 snps,parkmode-disable-ss-quirk;
4833 snps,dis-u1-entry-quirk;
4834 snps,dis-u2-entry-quirk;
4835 num-hc-interrupters = /bits/ 16 <3>;
4837 phy-names = "usb2-phy", "usb3-phy";
4838 maximum-speed = "super-speed";
4841 #address-cells = <1>;
4842 #size-cells = <0>;
4855 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
4861 venus: video-codec@aa00000 {
4862 compatible = "qcom,sc7280-venus";
4871 clock-names = "core", "bus", "iface",
4874 power-domains = <&videocc MVSC_GDSC>,
4877 power-domain-names = "venus", "vcodec0", "cx";
4878 operating-points-v2 = <&venus_opp_table>;
4882 interconnect-names = "cpu-cfg", "video-mem";
4885 memory-region = <&video_mem>;
4889 venus_opp_table: opp-table {
4890 compatible = "operating-points-v2";
4892 opp-133330000 {
4893 opp-hz = /bits/ 64 <133330000>;
4894 required-opps = <&rpmhpd_opp_low_svs>;
4897 opp-240000000 {
4898 opp-hz = /bits/ 64 <240000000>;
4899 required-opps = <&rpmhpd_opp_svs>;
4902 opp-335000000 {
4903 opp-hz = /bits/ 64 <335000000>;
4904 required-opps = <&rpmhpd_opp_svs_l1>;
4907 opp-424000000 {
4908 opp-hz = /bits/ 64 <424000000>;
4909 required-opps = <&rpmhpd_opp_nom>;
4912 opp-460000048 {
4913 opp-hz = /bits/ 64 <460000048>;
4914 required-opps = <&rpmhpd_opp_turbo>;
4919 videocc: clock-controller@aaf0000 {
4920 compatible = "qcom,sc7280-videocc";
4924 clock-names = "bi_tcxo", "bi_tcxo_ao";
4925 #clock-cells = <1>;
4926 #reset-cells = <1>;
4927 #power-domain-cells = <1>;
4931 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4934 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4941 clock-names = "camnoc_axi",
4946 pinctrl-0 = <&cci0_default &cci1_default>;
4947 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4948 pinctrl-names = "default", "sleep";
4950 #address-cells = <1>;
4951 #size-cells = <0>;
4955 cci0_i2c0: i2c-bus@0 {
4957 clock-frequency = <1000000>;
4958 #address-cells = <1>;
4959 #size-cells = <0>;
4962 cci0_i2c1: i2c-bus@1 {
4964 clock-frequency = <1000000>;
4965 #address-cells = <1>;
4966 #size-cells = <0>;
4971 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4974 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4981 clock-names = "camnoc_axi",
4986 pinctrl-0 = <&cci2_default &cci3_default>;
4987 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
4988 pinctrl-names = "default", "sleep";
4990 #address-cells = <1>;
4991 #size-cells = <0>;
4995 cci1_i2c0: i2c-bus@0 {
4997 clock-frequency = <1000000>;
4998 #address-cells = <1>;
4999 #size-cells = <0>;
5002 cci1_i2c1: i2c-bus@1 {
5004 clock-frequency = <1000000>;
5005 #address-cells = <1>;
5006 #size-cells = <0>;
5011 compatible = "qcom,sc7280-camss";
5028 reg-names = "csid0",
5077 clock-names = "camnoc_axi",
5126 interrupt-names = "csid0",
5146 interconnect-names = "ahb",
5151 power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
5155 power-domain-names = "ife0",
5163 #address-cells = <1>;
5164 #size-cells = <0>;
5188 camcc: clock-controller@ad00000 {
5189 compatible = "qcom,sc7280-camcc";
5194 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
5195 #clock-cells = <1>;
5196 #reset-cells = <1>;
5197 #power-domain-cells = <1>;
5200 dispcc: clock-controller@af00000 {
5201 compatible = "qcom,sc7280-dispcc";
5211 clock-names = "bi_tcxo",
5219 #clock-cells = <1>;
5220 #reset-cells = <1>;
5221 #power-domain-cells = <1>;
5224 mdss: display-subsystem@ae00000 {
5225 compatible = "qcom,sc7280-mdss";
5227 reg-names = "mdss";
5229 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
5234 clock-names = "iface",
5239 interrupt-controller;
5240 #interrupt-cells = <1>;
5246 interconnect-names = "mdp0-mem",
5247 "cpu-cfg";
5253 #address-cells = <2>;
5254 #size-cells = <2>;
5259 mdss_mdp: display-controller@ae01000 {
5260 compatible = "qcom,sc7280-dpu";
5263 reg-names = "mdp", "vbif";
5271 clock-names = "bus",
5277 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
5279 assigned-clock-rates = <19200000>,
5281 operating-points-v2 = <&mdp_opp_table>;
5282 power-domains = <&rpmhpd SC7280_CX>;
5284 interrupt-parent = <&mdss>;
5288 #address-cells = <1>;
5289 #size-cells = <0>;
5294 remote-endpoint = <&mdss_dsi0_in>;
5301 remote-endpoint = <&edp_in>;
5308 remote-endpoint = <&dp_in>;
5313 mdp_opp_table: opp-table {
5314 compatible = "operating-points-v2";
5316 opp-200000000 {
5317 opp-hz = /bits/ 64 <200000000>;
5318 required-opps = <&rpmhpd_opp_low_svs>;
5321 opp-300000000 {
5322 opp-hz = /bits/ 64 <300000000>;
5323 required-opps = <&rpmhpd_opp_svs>;
5326 opp-380000000 {
5327 opp-hz = /bits/ 64 <380000000>;
5328 required-opps = <&rpmhpd_opp_svs_l1>;
5331 opp-506666667 {
5332 opp-hz = /bits/ 64 <506666667>;
5333 required-opps = <&rpmhpd_opp_nom>;
5336 opp-608000000 {
5337 opp-hz = /bits/ 64 <608000000>;
5338 required-opps = <&rpmhpd_opp_turbo>;
5344 compatible = "qcom,sc7280-dsi-ctrl",
5345 "qcom,mdss-dsi-ctrl";
5347 reg-names = "dsi_ctrl";
5349 interrupt-parent = <&mdss>;
5358 clock-names = "byte",
5365 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
5367 assigned-clock-parents = <&mdss_dsi_phy DSI_BYTE_PLL_CLK>,
5370 operating-points-v2 = <&dsi_opp_table>;
5371 power-domains = <&rpmhpd SC7280_CX>;
5375 refgen-supply = <&refgen>;
5377 #address-cells = <1>;
5378 #size-cells = <0>;
5383 #address-cells = <1>;
5384 #size-cells = <0>;
5389 remote-endpoint = <&dpu_intf1_out>;
5400 dsi_opp_table: opp-table {
5401 compatible = "operating-points-v2";
5403 opp-187500000 {
5404 opp-hz = /bits/ 64 <187500000>;
5405 required-opps = <&rpmhpd_opp_low_svs>;
5408 opp-300000000 {
5409 opp-hz = /bits/ 64 <300000000>;
5410 required-opps = <&rpmhpd_opp_svs>;
5413 opp-358000000 {
5414 opp-hz = /bits/ 64 <358000000>;
5415 required-opps = <&rpmhpd_opp_svs_l1>;
5421 compatible = "qcom,sc7280-dsi-phy-7nm";
5425 reg-names = "dsi_phy",
5429 #clock-cells = <1>;
5430 #phy-cells = <0>;
5434 clock-names = "iface", "ref";
5440 compatible = "qcom,sc7280-edp";
5441 pinctrl-names = "default";
5442 pinctrl-0 = <&edp_hot_plug_det>;
5450 interrupt-parent = <&mdss>;
5458 clock-names = "core_iface",
5463 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
5465 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
5468 phy-names = "dp";
5470 operating-points-v2 = <&edp_opp_table>;
5471 power-domains = <&rpmhpd SC7280_CX>;
5476 #address-cells = <1>;
5477 #size-cells = <0>;
5482 remote-endpoint = <&dpu_intf5_out>;
5492 edp_opp_table: opp-table {
5493 compatible = "operating-points-v2";
5495 opp-160000000 {
5496 opp-hz = /bits/ 64 <160000000>;
5497 required-opps = <&rpmhpd_opp_low_svs>;
5500 opp-270000000 {
5501 opp-hz = /bits/ 64 <270000000>;
5502 required-opps = <&rpmhpd_opp_svs>;
5505 opp-540000000 {
5506 opp-hz = /bits/ 64 <540000000>;
5507 required-opps = <&rpmhpd_opp_nom>;
5510 opp-810000000 {
5511 opp-hz = /bits/ 64 <810000000>;
5512 required-opps = <&rpmhpd_opp_nom>;
5518 compatible = "qcom,sc7280-edp-phy";
5527 clock-names = "aux",
5530 #clock-cells = <1>;
5531 #phy-cells = <0>;
5536 mdss_dp: displayport-controller@ae90000 {
5537 compatible = "qcom,sc7280-dp";
5545 interrupt-parent = <&mdss>;
5553 clock-names = "core_iface",
5558 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
5560 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5563 phy-names = "dp";
5565 operating-points-v2 = <&dp_opp_table>;
5566 power-domains = <&rpmhpd SC7280_CX>;
5568 #sound-dai-cells = <0>;
5573 #address-cells = <1>;
5574 #size-cells = <0>;
5579 remote-endpoint = <&dpu_intf0_out>;
5586 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
5591 dp_opp_table: opp-table {
5592 compatible = "operating-points-v2";
5594 opp-160000000 {
5595 opp-hz = /bits/ 64 <160000000>;
5596 required-opps = <&rpmhpd_opp_low_svs>;
5599 opp-270000000 {
5600 opp-hz = /bits/ 64 <270000000>;
5601 required-opps = <&rpmhpd_opp_svs>;
5604 opp-540000000 {
5605 opp-hz = /bits/ 64 <540000000>;
5606 required-opps = <&rpmhpd_opp_svs_l1>;
5609 opp-810000000 {
5610 opp-hz = /bits/ 64 <810000000>;
5611 required-opps = <&rpmhpd_opp_nom>;
5617 pdc: interrupt-controller@b220000 {
5618 compatible = "qcom,sc7280-pdc", "qcom,pdc";
5620 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
5625 #interrupt-cells = <2>;
5626 interrupt-parent = <&intc>;
5627 interrupt-controller;
5630 pdc_reset: reset-controller@b5e0000 {
5631 compatible = "qcom,sc7280-pdc-global";
5633 #reset-cells = <1>;
5637 tsens0: thermal-sensor@c263000 {
5638 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
5644 interrupt-names = "uplow","critical";
5645 #thermal-sensor-cells = <1>;
5648 tsens1: thermal-sensor@c265000 {
5649 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
5655 interrupt-names = "uplow","critical";
5656 #thermal-sensor-cells = <1>;
5659 aoss_reset: reset-controller@c2a0000 {
5660 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
5662 #reset-cells = <1>;
5665 aoss_qmp: power-management@c300000 {
5666 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
5668 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5674 #clock-cells = <0>;
5678 compatible = "qcom,rpmh-stats";
5683 compatible = "qcom,spmi-pmic-arb";
5689 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5690 interrupt-names = "periph_irq";
5691 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5694 #address-cells = <2>;
5695 #size-cells = <0>;
5696 interrupt-controller;
5697 #interrupt-cells = <4>;
5701 compatible = "qcom,sc7280-pinctrl";
5704 gpio-controller;
5705 #gpio-cells = <2>;
5706 interrupt-controller;
5707 #interrupt-cells = <2>;
5708 gpio-ranges = <&tlmm 0 0 175>;
5709 wakeup-parent = <&pdc>;
5711 cci0_default: cci0-default-state {
5714 drive-strength = <2>;
5715 bias-pull-up;
5718 cci0_sleep: cci0-sleep-state {
5721 drive-strength = <2>;
5722 bias-pull-down;
5725 cci1_default: cci1-default-state {
5728 drive-strength = <2>;
5729 bias-pull-up;
5732 cci1_sleep: cci1-sleep-state {
5735 drive-strength = <2>;
5736 bias-pull-down;
5739 cci2_default: cci2-default-state {
5742 drive-strength = <2>;
5743 bias-pull-up;
5746 cci2_sleep: cci2-sleep-state {
5749 drive-strength = <2>;
5750 bias-pull-down;
5753 cci3_default: cci3-default-state {
5756 drive-strength = <2>;
5757 bias-pull-up;
5760 cci3_sleep: cci3-sleep-state {
5763 drive-strength = <2>;
5764 bias-pull-down;
5767 dp_hot_plug_det: dp-hot-plug-det-state {
5772 edp_hot_plug_det: edp-hot-plug-det-state {
5777 mi2s0_data0: mi2s0-data0-state {
5782 mi2s0_data1: mi2s0-data1-state {
5787 mi2s0_mclk: mi2s0-mclk-state {
5792 mi2s0_sclk: mi2s0-sclk-state {
5797 mi2s0_ws: mi2s0-ws-state {
5802 mi2s1_data0: mi2s1-data0-state {
5807 mi2s1_sclk: mi2s1-sclk-state {
5812 mi2s1_ws: mi2s1-ws-state {
5817 pcie0_clkreq_n: pcie0-clkreq-n-state {
5822 pcie1_clkreq_n: pcie1-clkreq-n-state {
5827 qspi_clk: qspi-clk-state {
5832 qspi_cs0: qspi-cs0-state {
5837 qspi_cs1: qspi-cs1-state {
5842 qspi_data0: qspi-data0-state {
5847 qspi_data1: qspi-data1-state {
5852 qspi_data23: qspi-data23-state {
5857 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5862 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5867 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5872 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5877 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5882 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5887 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5892 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5897 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5902 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5907 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5912 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5917 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5922 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5927 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5932 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5937 qup_spi0_data_clk: qup-spi0-data-clk-state {
5942 qup_spi0_cs: qup-spi0-cs-state {
5947 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5952 qup_spi1_data_clk: qup-spi1-data-clk-state {
5957 qup_spi1_cs: qup-spi1-cs-state {
5962 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5967 qup_spi2_data_clk: qup-spi2-data-clk-state {
5972 qup_spi2_cs: qup-spi2-cs-state {
5977 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5982 qup_spi3_data_clk: qup-spi3-data-clk-state {
5987 qup_spi3_cs: qup-spi3-cs-state {
5992 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5997 qup_spi4_data_clk: qup-spi4-data-clk-state {
6002 qup_spi4_cs: qup-spi4-cs-state {
6007 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
6012 qup_spi5_data_clk: qup-spi5-data-clk-state {
6017 qup_spi5_cs: qup-spi5-cs-state {
6022 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
6027 qup_spi6_data_clk: qup-spi6-data-clk-state {
6032 qup_spi6_cs: qup-spi6-cs-state {
6037 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
6042 qup_spi7_data_clk: qup-spi7-data-clk-state {
6047 qup_spi7_cs: qup-spi7-cs-state {
6052 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
6057 qup_spi8_data_clk: qup-spi8-data-clk-state {
6062 qup_spi8_cs: qup-spi8-cs-state {
6067 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
6072 qup_spi9_data_clk: qup-spi9-data-clk-state {
6077 qup_spi9_cs: qup-spi9-cs-state {
6082 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
6087 qup_spi10_data_clk: qup-spi10-data-clk-state {
6092 qup_spi10_cs: qup-spi10-cs-state {
6097 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
6102 qup_spi11_data_clk: qup-spi11-data-clk-state {
6107 qup_spi11_cs: qup-spi11-cs-state {
6112 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
6117 qup_spi12_data_clk: qup-spi12-data-clk-state {
6122 qup_spi12_cs: qup-spi12-cs-state {
6127 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
6132 qup_spi13_data_clk: qup-spi13-data-clk-state {
6137 qup_spi13_cs: qup-spi13-cs-state {
6142 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
6147 qup_spi14_data_clk: qup-spi14-data-clk-state {
6152 qup_spi14_cs: qup-spi14-cs-state {
6157 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
6162 qup_spi15_data_clk: qup-spi15-data-clk-state {
6167 qup_spi15_cs: qup-spi15-cs-state {
6172 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
6177 qup_uart0_cts: qup-uart0-cts-state {
6182 qup_uart0_rts: qup-uart0-rts-state {
6187 qup_uart0_tx: qup-uart0-tx-state {
6192 qup_uart0_rx: qup-uart0-rx-state {
6197 qup_uart1_cts: qup-uart1-cts-state {
6202 qup_uart1_rts: qup-uart1-rts-state {
6207 qup_uart1_tx: qup-uart1-tx-state {
6212 qup_uart1_rx: qup-uart1-rx-state {
6217 qup_uart2_cts: qup-uart2-cts-state {
6222 qup_uart2_rts: qup-uart2-rts-state {
6227 qup_uart2_tx: qup-uart2-tx-state {
6232 qup_uart2_rx: qup-uart2-rx-state {
6237 qup_uart3_cts: qup-uart3-cts-state {
6242 qup_uart3_rts: qup-uart3-rts-state {
6247 qup_uart3_tx: qup-uart3-tx-state {
6252 qup_uart3_rx: qup-uart3-rx-state {
6257 qup_uart4_cts: qup-uart4-cts-state {
6262 qup_uart4_rts: qup-uart4-rts-state {
6267 qup_uart4_tx: qup-uart4-tx-state {
6272 qup_uart4_rx: qup-uart4-rx-state {
6277 qup_uart5_tx: qup-uart5-tx-state {
6282 qup_uart5_rx: qup-uart5-rx-state {
6287 qup_uart6_cts: qup-uart6-cts-state {
6292 qup_uart6_rts: qup-uart6-rts-state {
6297 qup_uart6_tx: qup-uart6-tx-state {
6302 qup_uart6_rx: qup-uart6-rx-state {
6307 qup_uart7_cts: qup-uart7-cts-state {
6312 qup_uart7_rts: qup-uart7-rts-state {
6317 qup_uart7_tx: qup-uart7-tx-state {
6322 qup_uart7_rx: qup-uart7-rx-state {
6327 qup_uart8_cts: qup-uart8-cts-state {
6332 qup_uart8_rts: qup-uart8-rts-state {
6337 qup_uart8_tx: qup-uart8-tx-state {
6342 qup_uart8_rx: qup-uart8-rx-state {
6347 qup_uart9_cts: qup-uart9-cts-state {
6352 qup_uart9_rts: qup-uart9-rts-state {
6357 qup_uart9_tx: qup-uart9-tx-state {
6362 qup_uart9_rx: qup-uart9-rx-state {
6367 qup_uart10_cts: qup-uart10-cts-state {
6372 qup_uart10_rts: qup-uart10-rts-state {
6377 qup_uart10_tx: qup-uart10-tx-state {
6382 qup_uart10_rx: qup-uart10-rx-state {
6387 qup_uart11_cts: qup-uart11-cts-state {
6392 qup_uart11_rts: qup-uart11-rts-state {
6397 qup_uart11_tx: qup-uart11-tx-state {
6402 qup_uart11_rx: qup-uart11-rx-state {
6407 qup_uart12_cts: qup-uart12-cts-state {
6412 qup_uart12_rts: qup-uart12-rts-state {
6417 qup_uart12_tx: qup-uart12-tx-state {
6422 qup_uart12_rx: qup-uart12-rx-state {
6427 qup_uart13_cts: qup-uart13-cts-state {
6432 qup_uart13_rts: qup-uart13-rts-state {
6437 qup_uart13_tx: qup-uart13-tx-state {
6442 qup_uart13_rx: qup-uart13-rx-state {
6447 qup_uart14_cts: qup-uart14-cts-state {
6452 qup_uart14_rts: qup-uart14-rts-state {
6457 qup_uart14_tx: qup-uart14-tx-state {
6462 qup_uart14_rx: qup-uart14-rx-state {
6467 qup_uart15_cts: qup-uart15-cts-state {
6472 qup_uart15_rts: qup-uart15-rts-state {
6477 qup_uart15_tx: qup-uart15-tx-state {
6482 qup_uart15_rx: qup-uart15-rx-state {
6487 sdc1_clk: sdc1-clk-state {
6491 sdc1_cmd: sdc1-cmd-state {
6495 sdc1_data: sdc1-data-state {
6499 sdc1_rclk: sdc1-rclk-state {
6503 sdc1_clk_sleep: sdc1-clk-sleep-state {
6505 drive-strength = <2>;
6506 bias-bus-hold;
6509 sdc1_cmd_sleep: sdc1-cmd-sleep-state {
6511 drive-strength = <2>;
6512 bias-bus-hold;
6515 sdc1_data_sleep: sdc1-data-sleep-state {
6517 drive-strength = <2>;
6518 bias-bus-hold;
6521 sdc1_rclk_sleep: sdc1-rclk-sleep-state {
6523 drive-strength = <2>;
6524 bias-bus-hold;
6527 sdc2_clk: sdc2-clk-state {
6531 sdc2_cmd: sdc2-cmd-state {
6535 sdc2_data: sdc2-data-state {
6539 sdc2_clk_sleep: sdc2-clk-sleep-state {
6541 drive-strength = <2>;
6542 bias-bus-hold;
6545 sdc2_cmd_sleep: sdc2-cmd-sleep-state {
6547 drive-strength = <2>;
6548 bias-bus-hold;
6551 sdc2_data_sleep: sdc2-data-sleep-state {
6553 drive-strength = <2>;
6554 bias-bus-hold;
6559 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
6562 #address-cells = <1>;
6563 #size-cells = <1>;
6567 pil-reloc@594c {
6568 compatible = "qcom,pil-reloc-info";
6574 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
6576 #iommu-cells = <2>;
6577 #global-interrupts = <1>;
6578 dma-coherent;
6663 compatible = "qcom,sc7280-tbu";
6667 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
6671 compatible = "qcom,sc7280-tbu";
6675 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
6679 compatible = "qcom,sc7280-tbu";
6683 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
6684 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
6688 compatible = "qcom,sc7280-tbu";
6692 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
6693 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
6697 compatible = "qcom,sc7280-tbu";
6701 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>;
6702 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
6706 compatible = "qcom,sc7280-tbu";
6710 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>;
6711 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
6715 compatible = "qcom,sc7280-tbu";
6719 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
6723 compatible = "qcom,sc7280-tbu";
6727 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
6731 compatible = "qcom,sc7280-tbu";
6735 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>;
6736 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>;
6739 intc: interrupt-controller@17a00000 {
6740 compatible = "arm,gic-v3";
6744 #interrupt-cells = <3>;
6745 interrupt-controller;
6746 #address-cells = <2>;
6747 #size-cells = <2>;
6750 msi-controller@17a40000 {
6751 compatible = "arm,gic-v3-its";
6753 msi-controller;
6754 #msi-cells = <1>;
6760 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
6768 #address-cells = <1>;
6769 #size-cells = <1>;
6771 compatible = "arm,armv7-timer-mem";
6775 frame-number = <0>;
6783 frame-number = <1>;
6790 frame-number = <2>;
6797 frame-number = <3>;
6804 frame-number = <4>;
6811 frame-number = <5>;
6818 frame-number = <6>;
6826 compatible = "qcom,rpmh-rsc";
6830 reg-names = "drv-0", "drv-1", "drv-2";
6834 qcom,tcs-offset = <0xd00>;
6835 qcom,drv-id = <2>;
6836 qcom,tcs-config = <ACTIVE_TCS 2>,
6840 power-domains = <&cluster_pd>;
6842 apps_bcm_voter: bcm-voter {
6843 compatible = "qcom,bcm-voter";
6846 rpmhpd: power-controller {
6847 compatible = "qcom,sc7280-rpmhpd";
6848 #power-domain-cells = <1>;
6849 operating-points-v2 = <&rpmhpd_opp_table>;
6851 rpmhpd_opp_table: opp-table {
6852 compatible = "operating-points-v2";
6855 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6859 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6863 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6867 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6871 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
6875 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6879 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6883 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6887 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6892 rpmhcc: clock-controller {
6893 compatible = "qcom,sc7280-rpmh-clk";
6895 clock-names = "xo";
6896 #clock-cells = <1>;
6901 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
6904 clock-names = "xo", "alternate";
6905 #interconnect-cells = <1>;
6909 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
6917 interrupt-names = "dcvsh-irq-0",
6918 "dcvsh-irq-1",
6919 "dcvsh-irq-2";
6922 clock-names = "xo", "alternate";
6923 #freq-domain-cells = <1>;
6924 #clock-cells = <1>;
6931 thermal_zones: thermal-zones {
6932 cpu0-thermal {
6933 polling-delay-passive = <250>;
6935 thermal-sensors = <&tsens0 1>;
6938 cpu0_alert0: trip-point0 {
6944 cpu0_alert1: trip-point1 {
6950 cpu0_crit: cpu-crit {
6957 cooling-maps {
6960 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6967 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6975 cpu1-thermal {
6976 polling-delay-passive = <250>;
6978 thermal-sensors = <&tsens0 2>;
6981 cpu1_alert0: trip-point0 {
6987 cpu1_alert1: trip-point1 {
6993 cpu1_crit: cpu-crit {
7000 cooling-maps {
7003 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7010 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7018 cpu2-thermal {
7019 polling-delay-passive = <250>;
7021 thermal-sensors = <&tsens0 3>;
7024 cpu2_alert0: trip-point0 {
7030 cpu2_alert1: trip-point1 {
7036 cpu2_crit: cpu-crit {
7043 cooling-maps {
7046 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7053 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7061 cpu3-thermal {
7062 polling-delay-passive = <250>;
7064 thermal-sensors = <&tsens0 4>;
7067 cpu3_alert0: trip-point0 {
7073 cpu3_alert1: trip-point1 {
7079 cpu3_crit: cpu-crit {
7086 cooling-maps {
7089 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7096 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7104 cpu4-thermal {
7105 polling-delay-passive = <250>;
7107 thermal-sensors = <&tsens0 7>;
7110 cpu4_alert0: trip-point0 {
7116 cpu4_alert1: trip-point1 {
7122 cpu4_crit: cpu-crit {
7129 cooling-maps {
7132 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7139 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7147 cpu5-thermal {
7148 polling-delay-passive = <250>;
7150 thermal-sensors = <&tsens0 8>;
7153 cpu5_alert0: trip-point0 {
7159 cpu5_alert1: trip-point1 {
7165 cpu5_crit: cpu-crit {
7172 cooling-maps {
7175 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7182 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7190 cpu6-thermal {
7191 polling-delay-passive = <250>;
7193 thermal-sensors = <&tsens0 9>;
7196 cpu6_alert0: trip-point0 {
7202 cpu6_alert1: trip-point1 {
7208 cpu6_crit: cpu-crit {
7215 cooling-maps {
7218 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7225 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7233 cpu7-thermal {
7234 polling-delay-passive = <250>;
7236 thermal-sensors = <&tsens0 10>;
7239 cpu7_alert0: trip-point0 {
7245 cpu7_alert1: trip-point1 {
7251 cpu7_crit: cpu-crit {
7258 cooling-maps {
7261 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7268 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7276 cpu8-thermal {
7277 polling-delay-passive = <250>;
7279 thermal-sensors = <&tsens0 11>;
7282 cpu8_alert0: trip-point0 {
7288 cpu8_alert1: trip-point1 {
7294 cpu8_crit: cpu-crit {
7301 cooling-maps {
7304 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7311 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7319 cpu9-thermal {
7320 polling-delay-passive = <250>;
7322 thermal-sensors = <&tsens0 12>;
7325 cpu9_alert0: trip-point0 {
7331 cpu9_alert1: trip-point1 {
7337 cpu9_crit: cpu-crit {
7344 cooling-maps {
7347 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7354 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7362 cpu10-thermal {
7363 polling-delay-passive = <250>;
7365 thermal-sensors = <&tsens0 13>;
7368 cpu10_alert0: trip-point0 {
7374 cpu10_alert1: trip-point1 {
7380 cpu10_crit: cpu-crit {
7387 cooling-maps {
7390 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7397 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7405 cpu11-thermal {
7406 polling-delay-passive = <250>;
7408 thermal-sensors = <&tsens0 14>;
7411 cpu11_alert0: trip-point0 {
7417 cpu11_alert1: trip-point1 {
7423 cpu11_crit: cpu-crit {
7430 cooling-maps {
7433 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7440 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
7448 aoss0-thermal {
7449 polling-delay-passive = <0>;
7451 thermal-sensors = <&tsens0 0>;
7454 aoss0_alert0: trip-point0 {
7460 aoss0_crit: aoss0-crit {
7468 aoss1-thermal {
7469 polling-delay-passive = <0>;
7471 thermal-sensors = <&tsens1 0>;
7474 aoss1_alert0: trip-point0 {
7480 aoss1_crit: aoss1-crit {
7488 cpuss0-thermal {
7489 polling-delay-passive = <0>;
7491 thermal-sensors = <&tsens0 5>;
7494 cpuss0_alert0: trip-point0 {
7499 cpuss0_crit: cluster0-crit {
7507 cpuss1-thermal {
7508 polling-delay-passive = <0>;
7510 thermal-sensors = <&tsens0 6>;
7513 cpuss1_alert0: trip-point0 {
7518 cpuss1_crit: cluster0-crit {
7526 gpuss0-thermal {
7527 polling-delay-passive = <100>;
7529 thermal-sensors = <&tsens1 1>;
7532 gpuss0_alert0: trip-point0 {
7538 gpuss0_crit: gpuss0-crit {
7545 cooling-maps {
7548 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7553 gpuss1-thermal {
7554 polling-delay-passive = <100>;
7556 thermal-sensors = <&tsens1 2>;
7559 gpuss1_alert0: trip-point0 {
7565 gpuss1_crit: gpuss1-crit {
7572 cooling-maps {
7575 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
7580 nspss0-thermal {
7581 thermal-sensors = <&tsens1 3>;
7584 nspss0_alert0: trip-point0 {
7590 nspss0_crit: nspss0-crit {
7598 nspss1-thermal {
7599 thermal-sensors = <&tsens1 4>;
7602 nspss1_alert0: trip-point0 {
7608 nspss1_crit: nspss1-crit {
7616 video-thermal {
7617 thermal-sensors = <&tsens1 5>;
7620 video_alert0: trip-point0 {
7626 video_crit: video-crit {
7634 ddr-thermal {
7635 thermal-sensors = <&tsens1 6>;
7638 ddr_alert0: trip-point0 {
7644 ddr_crit: ddr-crit {
7652 mdmss0-thermal {
7653 thermal-sensors = <&tsens1 7>;
7656 mdmss0_alert0: trip-point0 {
7662 mdmss0_crit: mdmss0-crit {
7670 mdmss1-thermal {
7671 thermal-sensors = <&tsens1 8>;
7674 mdmss1_alert0: trip-point0 {
7680 mdmss1_crit: mdmss1-crit {
7688 mdmss2-thermal {
7689 thermal-sensors = <&tsens1 9>;
7692 mdmss2_alert0: trip-point0 {
7698 mdmss2_crit: mdmss2-crit {
7706 mdmss3-thermal {
7707 thermal-sensors = <&tsens1 10>;
7710 mdmss3_alert0: trip-point0 {
7716 mdmss3_crit: mdmss3-crit {
7724 camera0-thermal {
7725 thermal-sensors = <&tsens1 11>;
7728 camera0_alert0: trip-point0 {
7734 camera0_crit: camera0-crit {
7744 compatible = "arm,armv8-timer";