Lines Matching +full:mt8186 +full:- +full:sound
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/memory/mediatek,mt8365-larb-port.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mediatek,mt8365-power.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
37 #address-cells = <1>;
38 #size-cells = <0>;
40 cluster0_opp: opp-table-0 {
41 compatible = "operating-points-v2";
42 opp-shared;
44 opp-850000000 {
45 opp-hz = /bits/ 64 <850000000>;
46 opp-microvolt = <650000>;
49 opp-918000000 {
50 opp-hz = /bits/ 64 <918000000>;
51 opp-microvolt = <668750>;
54 opp-987000000 {
55 opp-hz = /bits/ 64 <987000000>;
56 opp-microvolt = <687500>;
59 opp-1056000000 {
60 opp-hz = /bits/ 64 <1056000000>;
61 opp-microvolt = <706250>;
64 opp-1125000000 {
65 opp-hz = /bits/ 64 <1125000000>;
66 opp-microvolt = <725000>;
69 opp-1216000000 {
70 opp-hz = /bits/ 64 <1216000000>;
71 opp-microvolt = <750000>;
74 opp-1308000000 {
75 opp-hz = /bits/ 64 <1308000000>;
76 opp-microvolt = <775000>;
79 opp-1400000000 {
80 opp-hz = /bits/ 64 <1400000000>;
81 opp-microvolt = <800000>;
84 opp-1466000000 {
85 opp-hz = /bits/ 64 <1466000000>;
86 opp-microvolt = <825000>;
89 opp-1533000000 {
90 opp-hz = /bits/ 64 <1533000000>;
91 opp-microvolt = <850000>;
94 opp-1633000000 {
95 opp-hz = /bits/ 64 <1633000000>;
96 opp-microvolt = <887500>;
99 opp-1700000000 {
100 opp-hz = /bits/ 64 <1700000000>;
101 opp-microvolt = <912500>;
104 opp-1767000000 {
105 opp-hz = /bits/ 64 <1767000000>;
106 opp-microvolt = <937500>;
109 opp-1834000000 {
110 opp-hz = /bits/ 64 <1834000000>;
111 opp-microvolt = <962500>;
114 opp-1917000000 {
115 opp-hz = /bits/ 64 <1917000000>;
116 opp-microvolt = <993750>;
119 opp-2001000000 {
120 opp-hz = /bits/ 64 <2001000000>;
121 opp-microvolt = <1025000>;
125 cpu-map {
144 compatible = "arm,cortex-a53";
146 #cooling-cells = <2>;
147 enable-method = "psci";
148 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
149 i-cache-size = <0x8000>;
150 i-cache-line-size = <64>;
151 i-cache-sets = <256>;
152 d-cache-size = <0x8000>;
153 d-cache-line-size = <64>;
154 d-cache-sets = <256>;
155 next-level-cache = <&l2>;
158 clock-names = "cpu", "intermediate";
159 operating-points-v2 = <&cluster0_opp>;
164 compatible = "arm,cortex-a53";
166 #cooling-cells = <2>;
167 enable-method = "psci";
168 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
169 i-cache-size = <0x8000>;
170 i-cache-line-size = <64>;
171 i-cache-sets = <256>;
172 d-cache-size = <0x8000>;
173 d-cache-line-size = <64>;
174 d-cache-sets = <256>;
175 next-level-cache = <&l2>;
178 clock-names = "cpu", "intermediate", "armpll";
179 operating-points-v2 = <&cluster0_opp>;
184 compatible = "arm,cortex-a53";
186 #cooling-cells = <2>;
187 enable-method = "psci";
188 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
189 i-cache-size = <0x8000>;
190 i-cache-line-size = <64>;
191 i-cache-sets = <256>;
192 d-cache-size = <0x8000>;
193 d-cache-line-size = <64>;
194 d-cache-sets = <256>;
195 next-level-cache = <&l2>;
198 clock-names = "cpu", "intermediate", "armpll";
199 operating-points-v2 = <&cluster0_opp>;
204 compatible = "arm,cortex-a53";
206 #cooling-cells = <2>;
207 enable-method = "psci";
208 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
209 i-cache-size = <0x8000>;
210 i-cache-line-size = <64>;
211 i-cache-sets = <256>;
212 d-cache-size = <0x8000>;
213 d-cache-line-size = <64>;
214 d-cache-sets = <256>;
215 next-level-cache = <&l2>;
218 clock-names = "cpu", "intermediate", "armpll";
219 operating-points-v2 = <&cluster0_opp>;
222 idle-states {
223 entry-method = "psci";
225 CPU_MCDI: cpu-mcdi {
226 compatible = "arm,idle-state";
227 local-timer-stop;
228 arm,psci-suspend-param = <0x00010001>;
229 entry-latency-us = <300>;
230 exit-latency-us = <200>;
231 min-residency-us = <1000>;
234 CLUSTER_MCDI: cluster-mcdi {
235 compatible = "arm,idle-state";
236 local-timer-stop;
237 arm,psci-suspend-param = <0x01010001>;
238 entry-latency-us = <350>;
239 exit-latency-us = <250>;
240 min-residency-us = <1200>;
243 CLUSTER_DPIDLE: cluster-dpidle {
244 compatible = "arm,idle-state";
245 local-timer-stop;
246 arm,psci-suspend-param = <0x01010004>;
247 entry-latency-us = <300>;
248 exit-latency-us = <800>;
249 min-residency-us = <3300>;
253 l2: l2-cache {
255 cache-level = <2>;
256 cache-size = <0x80000>;
257 cache-line-size = <64>;
258 cache-sets = <512>;
259 cache-unified;
264 compatible = "fixed-clock";
265 #clock-cells = <0>;
266 clock-frequency = <26000000>;
267 clock-output-names = "clk26m";
271 compatible = "arm,psci-1.0";
276 #address-cells = <2>;
277 #size-cells = <2>;
278 compatible = "simple-bus";
281 gic: interrupt-controller@c000000 {
282 compatible = "arm,gic-v3";
283 #interrupt-cells = <3>;
284 interrupt-parent = <&gic>;
285 interrupt-controller;
296 compatible = "mediatek,mt8365-topckgen", "syscon";
298 #clock-cells = <1>;
302 compatible = "mediatek,mt8365-infracfg", "syscon";
304 #clock-cells = <1>;
308 compatible = "mediatek,mt8365-pericfg", "syscon";
310 #clock-cells = <1>;
313 syscfg_pctl: syscfg-pctl@10005000 {
314 compatible = "mediatek,mt8365-syscfg", "syscon";
319 compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd";
323 spm: power-controller {
324 compatible = "mediatek,mt8365-power-controller";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 #power-domain-cells = <1>;
330 power-domain@MT8365_POWER_DOMAIN_MM {
337 clock-names = "mm", "mm-0", "mm-1",
338 "mm-2", "mm-3";
339 #power-domain-cells = <0>;
341 mediatek,infracfg-nao = <&infracfg_nao>;
342 #address-cells = <1>;
343 #size-cells = <0>;
345 power-domain@MT8365_POWER_DOMAIN_CAM {
353 clock-names = "cam-0", "cam-1",
354 "cam-2", "cam-3",
355 "cam-4", "cam-5";
356 #power-domain-cells = <0>;
361 power-domain@MT8365_POWER_DOMAIN_VDEC {
363 #power-domain-cells = <0>;
367 power-domain@MT8365_POWER_DOMAIN_VENC {
369 #power-domain-cells = <0>;
373 power-domain@MT8365_POWER_DOMAIN_APU {
382 clock-names = "apu", "apu-0",
383 "apu-1", "apu-2",
384 "apu-3", "apu-4",
385 "apu-5";
386 #power-domain-cells = <0>;
392 power-domain@MT8365_POWER_DOMAIN_CONN {
396 clock-names = "conn", "conn1";
397 #power-domain-cells = <0>;
401 power-domain@MT8365_POWER_DOMAIN_MFG {
404 clock-names = "mfg";
405 #power-domain-cells = <0>;
409 power-domain@MT8365_POWER_DOMAIN_AUDIO {
414 clock-names = "audio", "audio1", "audio2";
415 #power-domain-cells = <0>;
419 power-domain@MT8365_POWER_DOMAIN_DSP {
423 clock-names = "dsp", "dsp1";
424 #power-domain-cells = <0>;
431 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
433 #reset-cells = <1>;
437 compatible = "mediatek,mt8365-pinctrl";
439 mediatek,pctl-regmap = <&syscfg_pctl>;
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
448 compatible = "mediatek,mt8365-apmixedsys", "syscon";
450 #clock-cells = <1>;
454 compatible = "mediatek,mt8365-pwrap";
456 reg-names = "pwrap";
462 clock-names = "spi", "wrap", "sys", "tmr";
466 compatible = "mediatek,mt8365-keypad",
467 "mediatek,mt6779-keypad";
469 wakeup-source;
472 clock-names = "kpd";
477 compatible = "mediatek,mt8365-mcucfg", "syscon";
479 #clock-cells = <1>;
482 sysirq: interrupt-controller@10200a80 {
483 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
484 interrupt-controller;
485 #interrupt-cells = <3>;
486 interrupt-parent = <&gic>;
491 compatible = "mediatek,mt8365-m4u";
495 #iommu-cells = <1>;
499 compatible = "mediatek,mt8365-infracfg", "syscon";
501 #clock-cells = <1>;
505 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
508 clock-names = "rng";
511 apdma: dma-controller@11000280 {
512 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
525 dma-requests = <6>;
527 clock-names = "apdma";
528 #dma-cells = <1>;
532 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
536 clock-names = "baud", "bus";
538 dma-names = "tx", "rx";
543 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
547 clock-names = "baud", "bus";
549 dma-names = "tx", "rx";
554 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
558 clock-names = "baud", "bus";
560 dma-names = "tx", "rx";
565 compatible = "mediatek,mt8365-pwm";
567 #pwm-cells = <2>;
574 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
578 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
581 clock-div = <1>;
583 clock-names = "main", "dma";
584 #address-cells = <1>;
585 #size-cells = <0>;
590 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
593 clock-div = <1>;
595 clock-names = "main", "dma";
596 #address-cells = <1>;
597 #size-cells = <0>;
602 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
605 clock-div = <1>;
607 clock-names = "main", "dma";
608 #address-cells = <1>;
609 #size-cells = <0>;
614 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
616 #address-cells = <1>;
617 #size-cells = <0>;
622 clock-names = "parent-clk", "sel-clk", "spi-clk";
627 compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm";
629 clock-names = "main", "mm";
631 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
632 #pwm-cells = <2>;
636 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
639 clock-div = <1>;
641 clock-names = "main", "dma";
642 #address-cells = <1>;
643 #size-cells = <0>;
648 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
650 reg-names = "mac", "ippc";
658 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
659 #address-cells = <2>;
660 #size-cells = <2>;
665 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
667 reg-names = "mac";
674 clock-names = "sys_ck", "ref_ck", "mcu_ck",
681 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
688 clock-names = "source", "hclk", "source_cg";
693 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
700 clock-names = "source", "hclk", "source_cg";
705 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
714 clock-names = "source", "hclk", "source_cg",
720 compatible = "mediatek,mt8365-eth";
727 clock-names = "core", "reg", "trans";
731 mipi_tx0: dsi-phy@11c00000 {
732 compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx";
734 clock-output-names = "mipi_tx0_pll";
736 #clock-cells = <0>;
737 #phy-cells = <0>;
740 u3phy: t-phy@11cc0000 {
741 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
742 #address-cells = <1>;
743 #size-cells = <1>;
746 u2port0: usb-phy@0 {
750 clock-names = "ref", "da_ref";
751 #phy-cells = <1>;
754 u2port1: usb-phy@1000 {
758 clock-names = "ref", "da_ref";
759 #phy-cells = <1>;
764 compatible = "mediatek,mt8365-mmsys", "syscon";
766 #clock-cells = <1>;
768 #address-cells = <1>;
769 #size-cells = <0>;
773 remote-endpoint = <&ovl0_in>;
777 remote-endpoint = <&rdma1_in>;
783 compatible = "mediatek,mt8365-disp-mutex";
786 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
790 compatible = "mediatek,mt8365-smi-common";
796 clock-names = "apb", "smi", "gals0", "gals1";
797 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
801 compatible = "mediatek,mt8365-smi-larb",
802 "mediatek,mt8186-smi-larb";
807 clock-names = "apb", "smi";
808 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
809 mediatek,larb-id = <0>;
813 compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl";
818 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
820 #address-cells = <1>;
821 #size-cells = <0>;
824 #address-cells = <1>;
825 #size-cells = <0>;
829 remote-endpoint = <&mmsys_main>;
834 #address-cells = <1>;
835 #size-cells = <0>;
839 remote-endpoint = <&rdma0_in>;
846 compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma";
851 mediatek,rdma-fifo-size = <5120>;
852 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
854 #address-cells = <1>;
855 #size-cells = <0>;
858 #address-cells = <1>;
859 #size-cells = <0>;
863 remote-endpoint = <&ovl0_out>;
868 #address-cells = <1>;
869 #size-cells = <0>;
873 remote-endpoint = <&color0_in>;
880 compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color";
884 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
886 #address-cells = <1>;
887 #size-cells = <0>;
890 #address-cells = <1>;
891 #size-cells = <0>;
895 remote-endpoint = <&rdma0_out>;
900 #address-cells = <1>;
901 #size-cells = <0>;
905 remote-endpoint = <&ccorr0_in>;
912 compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr";
916 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
918 #address-cells = <1>;
919 #size-cells = <0>;
922 #address-cells = <1>;
923 #size-cells = <0>;
927 remote-endpoint = <&color0_out>;
932 #address-cells = <1>;
933 #size-cells = <0>;
937 remote-endpoint = <&aal0_in>;
944 compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal";
948 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
950 #address-cells = <1>;
951 #size-cells = <0>;
954 #address-cells = <1>;
955 #size-cells = <0>;
959 remote-endpoint = <&ccorr0_out>;
964 #address-cells = <1>;
965 #size-cells = <0>;
969 remote-endpoint = <&gamma0_in>;
976 compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma";
980 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
982 #address-cells = <1>;
983 #size-cells = <0>;
986 #address-cells = <1>;
987 #size-cells = <0>;
991 remote-endpoint = <&aal0_out>;
996 #address-cells = <1>;
997 #size-cells = <0>;
1001 remote-endpoint = <&dither0_in>;
1008 compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither";
1012 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1023 remote-endpoint = <&gamma0_out>;
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1039 compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi";
1041 clock-names = "engine", "digital", "hs";
1046 phy-names = "dphy";
1048 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
1052 compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma";
1057 mediatek,rdma-fifo-size = <2048>;
1058 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
1060 #address-cells = <1>;
1061 #size-cells = <0>;
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1069 remote-endpoint = <&mmsys_ext>;
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1085 compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi";
1090 clock-names = "pixel", "engine", "pll";
1092 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
1097 compatible = "mediatek,mt8365-imgsys", "syscon";
1099 #clock-cells = <1>;
1103 compatible = "mediatek,mt8365-smi-larb",
1104 "mediatek,mt8186-smi-larb";
1109 clock-names = "apb", "smi";
1110 power-domains = <&spm MT8365_POWER_DOMAIN_CAM>;
1111 mediatek,larb-id = <2>;
1115 compatible = "mediatek,mt8365-vdecsys", "syscon";
1117 #clock-cells = <1>;
1121 compatible = "mediatek,mt8365-smi-larb",
1122 "mediatek,mt8186-smi-larb";
1127 clock-names = "apb", "smi";
1128 power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>;
1129 mediatek,larb-id = <3>;
1133 compatible = "mediatek,mt8365-vencsys", "syscon";
1135 #clock-cells = <1>;
1139 compatible = "mediatek,mt8365-smi-larb",
1140 "mediatek,mt8186-smi-larb";
1144 clock-names = "apb", "smi";
1145 power-domains = <&spm MT8365_POWER_DOMAIN_VENC>;
1146 mediatek,larb-id = <1>;
1150 compatible = "mediatek,mt8365-apu", "syscon";
1152 #clock-cells = <1>;
1155 afe: audio-controller@11220000 {
1156 compatible = "mediatek,mt8365-afe-pcm";
1158 #sound-dai-cells = <0>;
1173 clock-names = "top_clk26m_clk",
1188 power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>;
1194 compatible = "arm,armv8-timer";
1195 interrupt-parent = <&gic>;
1203 compatible = "fixed-clock";
1204 clock-frequency = <13000000>;
1205 #clock-cells = <0>;
1209 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
1213 clock-names = "clk13m";