Lines Matching +full:mt8183 +full:- +full:xhci
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/power/mediatek,mt8365-power.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cluster0_opp: opp-table-0 {
27 compatible = "operating-points-v2";
28 opp-shared;
30 opp-850000000 {
31 opp-hz = /bits/ 64 <850000000>;
32 opp-microvolt = <650000>;
35 opp-918000000 {
36 opp-hz = /bits/ 64 <918000000>;
37 opp-microvolt = <668750>;
40 opp-987000000 {
41 opp-hz = /bits/ 64 <987000000>;
42 opp-microvolt = <687500>;
45 opp-1056000000 {
46 opp-hz = /bits/ 64 <1056000000>;
47 opp-microvolt = <706250>;
50 opp-1125000000 {
51 opp-hz = /bits/ 64 <1125000000>;
52 opp-microvolt = <725000>;
55 opp-1216000000 {
56 opp-hz = /bits/ 64 <1216000000>;
57 opp-microvolt = <750000>;
60 opp-1308000000 {
61 opp-hz = /bits/ 64 <1308000000>;
62 opp-microvolt = <775000>;
65 opp-1400000000 {
66 opp-hz = /bits/ 64 <1400000000>;
67 opp-microvolt = <800000>;
70 opp-1466000000 {
71 opp-hz = /bits/ 64 <1466000000>;
72 opp-microvolt = <825000>;
75 opp-1533000000 {
76 opp-hz = /bits/ 64 <1533000000>;
77 opp-microvolt = <850000>;
80 opp-1633000000 {
81 opp-hz = /bits/ 64 <1633000000>;
82 opp-microvolt = <887500>;
85 opp-1700000000 {
86 opp-hz = /bits/ 64 <1700000000>;
87 opp-microvolt = <912500>;
90 opp-1767000000 {
91 opp-hz = /bits/ 64 <1767000000>;
92 opp-microvolt = <937500>;
95 opp-1834000000 {
96 opp-hz = /bits/ 64 <1834000000>;
97 opp-microvolt = <962500>;
100 opp-1917000000 {
101 opp-hz = /bits/ 64 <1917000000>;
102 opp-microvolt = <993750>;
105 opp-2001000000 {
106 opp-hz = /bits/ 64 <2001000000>;
107 opp-microvolt = <1025000>;
111 cpu-map {
130 compatible = "arm,cortex-a53";
132 #cooling-cells = <2>;
133 enable-method = "psci";
134 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
135 i-cache-size = <0x8000>;
136 i-cache-line-size = <64>;
137 i-cache-sets = <256>;
138 d-cache-size = <0x8000>;
139 d-cache-line-size = <64>;
140 d-cache-sets = <256>;
141 next-level-cache = <&l2>;
144 clock-names = "cpu", "intermediate";
145 operating-points-v2 = <&cluster0_opp>;
150 compatible = "arm,cortex-a53";
152 #cooling-cells = <2>;
153 enable-method = "psci";
154 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
155 i-cache-size = <0x8000>;
156 i-cache-line-size = <64>;
157 i-cache-sets = <256>;
158 d-cache-size = <0x8000>;
159 d-cache-line-size = <64>;
160 d-cache-sets = <256>;
161 next-level-cache = <&l2>;
164 clock-names = "cpu", "intermediate", "armpll";
165 operating-points-v2 = <&cluster0_opp>;
170 compatible = "arm,cortex-a53";
172 #cooling-cells = <2>;
173 enable-method = "psci";
174 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
175 i-cache-size = <0x8000>;
176 i-cache-line-size = <64>;
177 i-cache-sets = <256>;
178 d-cache-size = <0x8000>;
179 d-cache-line-size = <64>;
180 d-cache-sets = <256>;
181 next-level-cache = <&l2>;
184 clock-names = "cpu", "intermediate", "armpll";
185 operating-points-v2 = <&cluster0_opp>;
190 compatible = "arm,cortex-a53";
192 #cooling-cells = <2>;
193 enable-method = "psci";
194 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
195 i-cache-size = <0x8000>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <0x8000>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2>;
204 clock-names = "cpu", "intermediate", "armpll";
205 operating-points-v2 = <&cluster0_opp>;
208 idle-states {
209 entry-method = "psci";
211 CPU_MCDI: cpu-mcdi {
212 compatible = "arm,idle-state";
213 local-timer-stop;
214 arm,psci-suspend-param = <0x00010001>;
215 entry-latency-us = <300>;
216 exit-latency-us = <200>;
217 min-residency-us = <1000>;
220 CLUSTER_MCDI: cluster-mcdi {
221 compatible = "arm,idle-state";
222 local-timer-stop;
223 arm,psci-suspend-param = <0x01010001>;
224 entry-latency-us = <350>;
225 exit-latency-us = <250>;
226 min-residency-us = <1200>;
229 CLUSTER_DPIDLE: cluster-dpidle {
230 compatible = "arm,idle-state";
231 local-timer-stop;
232 arm,psci-suspend-param = <0x01010004>;
233 entry-latency-us = <300>;
234 exit-latency-us = <800>;
235 min-residency-us = <3300>;
239 l2: l2-cache {
241 cache-level = <2>;
242 cache-size = <0x80000>;
243 cache-line-size = <64>;
244 cache-sets = <512>;
245 cache-unified;
250 compatible = "fixed-clock";
251 #clock-cells = <0>;
252 clock-frequency = <26000000>;
253 clock-output-names = "clk26m";
257 compatible = "arm,psci-1.0";
262 #address-cells = <2>;
263 #size-cells = <2>;
264 compatible = "simple-bus";
267 gic: interrupt-controller@c000000 {
268 compatible = "arm,gic-v3";
269 #interrupt-cells = <3>;
270 interrupt-parent = <&gic>;
271 interrupt-controller;
282 compatible = "mediatek,mt8365-topckgen", "syscon";
284 #clock-cells = <1>;
288 compatible = "mediatek,mt8365-infracfg", "syscon";
290 #clock-cells = <1>;
294 compatible = "mediatek,mt8365-pericfg", "syscon";
296 #clock-cells = <1>;
299 syscfg_pctl: syscfg-pctl@10005000 {
300 compatible = "mediatek,mt8365-syscfg", "syscon";
305 compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd";
309 spm: power-controller {
310 compatible = "mediatek,mt8365-power-controller";
311 #address-cells = <1>;
312 #size-cells = <0>;
313 #power-domain-cells = <1>;
316 power-domain@MT8365_POWER_DOMAIN_MM {
323 clock-names = "mm", "mm-0", "mm-1",
324 "mm-2", "mm-3";
325 #power-domain-cells = <0>;
327 mediatek,infracfg-nao = <&infracfg_nao>;
328 #address-cells = <1>;
329 #size-cells = <0>;
331 power-domain@MT8365_POWER_DOMAIN_CAM {
339 clock-names = "cam-0", "cam-1",
340 "cam-2", "cam-3",
341 "cam-4", "cam-5";
342 #power-domain-cells = <0>;
347 power-domain@MT8365_POWER_DOMAIN_VDEC {
349 #power-domain-cells = <0>;
353 power-domain@MT8365_POWER_DOMAIN_VENC {
355 #power-domain-cells = <0>;
359 power-domain@MT8365_POWER_DOMAIN_APU {
368 clock-names = "apu", "apu-0",
369 "apu-1", "apu-2",
370 "apu-3", "apu-4",
371 "apu-5";
372 #power-domain-cells = <0>;
378 power-domain@MT8365_POWER_DOMAIN_CONN {
382 clock-names = "conn", "conn1";
383 #power-domain-cells = <0>;
387 power-domain@MT8365_POWER_DOMAIN_MFG {
390 clock-names = "mfg";
391 #power-domain-cells = <0>;
395 power-domain@MT8365_POWER_DOMAIN_AUDIO {
400 clock-names = "audio", "audio1", "audio2";
401 #power-domain-cells = <0>;
405 power-domain@MT8365_POWER_DOMAIN_DSP {
409 clock-names = "dsp", "dsp1";
410 #power-domain-cells = <0>;
417 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
419 #reset-cells = <1>;
423 compatible = "mediatek,mt8365-pinctrl";
425 mediatek,pctl-regmap = <&syscfg_pctl>;
426 gpio-controller;
427 #gpio-cells = <2>;
428 interrupt-controller;
429 #interrupt-cells = <2>;
434 compatible = "mediatek,mt8365-apmixedsys", "syscon";
436 #clock-cells = <1>;
440 compatible = "mediatek,mt8365-pwrap";
442 reg-names = "pwrap";
448 clock-names = "spi", "wrap", "sys", "tmr";
452 compatible = "mediatek,mt6779-keypad";
454 wakeup-source;
457 clock-names = "kpd";
462 compatible = "mediatek,mt8365-mcucfg", "syscon";
464 #clock-cells = <1>;
467 sysirq: interrupt-controller@10200a80 {
468 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
469 interrupt-controller;
470 #interrupt-cells = <3>;
471 interrupt-parent = <&gic>;
476 compatible = "mediatek,mt8365-m4u";
480 #iommu-cells = <1>;
484 compatible = "mediatek,mt8365-infracfg", "syscon";
486 #clock-cells = <1>;
490 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
493 clock-names = "rng";
496 apdma: dma-controller@11000280 {
497 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
510 dma-requests = <6>;
512 clock-names = "apdma";
513 #dma-cells = <1>;
517 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
521 clock-names = "baud", "bus";
523 dma-names = "tx", "rx";
528 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
532 clock-names = "baud", "bus";
534 dma-names = "tx", "rx";
539 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
543 clock-names = "baud", "bus";
545 dma-names = "tx", "rx";
550 compatible = "mediatek,mt8365-pwm";
552 #pwm-cells = <2>;
559 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
563 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
566 clock-div = <1>;
568 clock-names = "main", "dma";
569 #address-cells = <1>;
570 #size-cells = <0>;
575 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
578 clock-div = <1>;
580 clock-names = "main", "dma";
581 #address-cells = <1>;
582 #size-cells = <0>;
587 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
590 clock-div = <1>;
592 clock-names = "main", "dma";
593 #address-cells = <1>;
594 #size-cells = <0>;
599 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
601 #address-cells = <1>;
602 #size-cells = <0>;
607 clock-names = "parent-clk", "sel-clk", "spi-clk";
612 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
615 clock-div = <1>;
617 clock-names = "main", "dma";
618 #address-cells = <1>;
619 #size-cells = <0>;
624 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
626 reg-names = "mac", "ippc";
634 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
635 #address-cells = <2>;
636 #size-cells = <2>;
641 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
643 reg-names = "mac";
650 clock-names = "sys_ck", "ref_ck", "mcu_ck",
657 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
664 clock-names = "source", "hclk", "source_cg";
669 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
676 clock-names = "source", "hclk", "source_cg";
681 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
690 clock-names = "source", "hclk", "source_cg",
696 compatible = "mediatek,mt8365-eth";
703 clock-names = "core", "reg", "trans";
707 u3phy: t-phy@11cc0000 {
708 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
709 #address-cells = <1>;
710 #size-cells = <1>;
713 u2port0: usb-phy@0 {
717 clock-names = "ref", "da_ref";
718 #phy-cells = <1>;
721 u2port1: usb-phy@1000 {
725 clock-names = "ref", "da_ref";
726 #phy-cells = <1>;
731 compatible = "mediatek,mt8365-mmsys", "syscon";
733 #clock-cells = <1>;
737 compatible = "mediatek,mt8365-smi-common";
743 clock-names = "apb", "smi", "gals0", "gals1";
744 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
748 compatible = "mediatek,mt8365-smi-larb",
749 "mediatek,mt8186-smi-larb";
754 clock-names = "apb", "smi";
755 power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
756 mediatek,larb-id = <0>;
760 compatible = "mediatek,mt8365-imgsys", "syscon";
762 #clock-cells = <1>;
766 compatible = "mediatek,mt8365-smi-larb",
767 "mediatek,mt8186-smi-larb";
772 clock-names = "apb", "smi";
773 power-domains = <&spm MT8365_POWER_DOMAIN_CAM>;
774 mediatek,larb-id = <2>;
778 compatible = "mediatek,mt8365-vdecsys", "syscon";
780 #clock-cells = <1>;
784 compatible = "mediatek,mt8365-smi-larb",
785 "mediatek,mt8186-smi-larb";
790 clock-names = "apb", "smi";
791 power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>;
792 mediatek,larb-id = <3>;
796 compatible = "mediatek,mt8365-vencsys", "syscon";
798 #clock-cells = <1>;
802 compatible = "mediatek,mt8365-smi-larb",
803 "mediatek,mt8186-smi-larb";
807 clock-names = "apb", "smi";
808 power-domains = <&spm MT8365_POWER_DOMAIN_VENC>;
809 mediatek,larb-id = <1>;
813 compatible = "mediatek,mt8365-apu", "syscon";
815 #clock-cells = <1>;
818 afe: audio-controller@11220000 {
819 compatible = "mediatek,mt8365-afe-pcm";
821 #sound-dai-cells = <0>;
836 clock-names = "top_clk26m_clk",
851 power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>;
857 compatible = "arm,armv8-timer";
858 interrupt-parent = <&gic>;
866 compatible = "fixed-clock";
867 clock-frequency = <13000000>;
868 #clock-cells = <0>;
872 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
876 clock-names = "clk13m";