Lines Matching +full:0 +full:x01010001
38 #size-cells = <0>;
40 cluster0_opp: opp-table-0 {
142 cpu0: cpu@0 {
145 reg = <0x0>;
149 i-cache-size = <0x8000>;
152 d-cache-size = <0x8000>;
165 reg = <0x1>;
169 i-cache-size = <0x8000>;
172 d-cache-size = <0x8000>;
185 reg = <0x2>;
189 i-cache-size = <0x8000>;
192 d-cache-size = <0x8000>;
205 reg = <0x3>;
209 i-cache-size = <0x8000>;
212 d-cache-size = <0x8000>;
228 arm,psci-suspend-param = <0x00010001>;
237 arm,psci-suspend-param = <0x01010001>;
246 arm,psci-suspend-param = <0x01010004>;
256 cache-size = <0x80000>;
265 #clock-cells = <0>;
286 reg = <0 0x0c000000 0 0x10000>, /* GICD */
287 <0 0x0c080000 0 0x80000>, /* GICR */
288 <0 0x0c400000 0 0x2000>, /* GICC */
289 <0 0x0c410000 0 0x1000>, /* GICH */
290 <0 0x0c420000 0 0x2000>; /* GICV */
297 reg = <0 0x10000000 0 0x1000>;
303 reg = <0 0x10001000 0 0x1000>;
309 reg = <0 0x10003000 0 0x1000>;
315 reg = <0 0x10005000 0 0x1000>;
320 reg = <0 0x10006000 0 0x1000>;
326 #size-cells = <0>;
337 clock-names = "mm", "mm-0", "mm-1",
339 #power-domain-cells = <0>;
343 #size-cells = <0>;
353 clock-names = "cam-0", "cam-1",
356 #power-domain-cells = <0>;
363 #power-domain-cells = <0>;
369 #power-domain-cells = <0>;
382 clock-names = "apu", "apu-0",
386 #power-domain-cells = <0>;
397 #power-domain-cells = <0>;
405 #power-domain-cells = <0>;
415 #power-domain-cells = <0>;
424 #power-domain-cells = <0>;
432 reg = <0 0x10007000 0 0x100>;
438 reg = <0 0x1000b000 0 0x1000>;
449 reg = <0 0x1000c000 0 0x1000>;
455 reg = <0 0x1000d000 0 0x1000>;
468 reg = <0 0x10010000 0 0x1000>;
478 reg = <0 0x10200000 0 0x2000>;
487 reg = <0 0x10200a80 0 0x20>;
492 reg = <0 0x10205000 0 0x1000>;
500 reg = <0 0x1020e000 0 0x1000>;
506 reg = <0 0x1020f000 0 0x100>;
513 reg = <0 0x11000280 0 0x80>,
514 <0 0x11000300 0 0x80>,
515 <0 0x11000380 0 0x80>,
516 <0 0x11000400 0 0x80>,
517 <0 0x11000580 0 0x80>,
518 <0 0x11000600 0 0x80>;
533 reg = <0 0x11002000 0 0x1000>;
537 dmas = <&apdma 0>, <&apdma 1>;
544 reg = <0 0x11003000 0 0x1000>;
555 reg = <0 0x11004000 0 0x1000>;
566 reg = <0 0x11006000 0 0x1000>;
579 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
585 #size-cells = <0>;
591 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
597 #size-cells = <0>;
603 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
609 #size-cells = <0>;
615 reg = <0 0x1100a000 0 0x100>;
617 #size-cells = <0>;
628 reg = <0 0x1100e000 0 0x1000>;
637 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
643 #size-cells = <0>;
649 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
666 reg = <0 0x11200000 0 0x1000>;
682 reg = <0 0x11230000 0 0x1000>,
683 <0 0x11cd0000 0 0x1000>;
694 reg = <0 0x11240000 0 0x1000>,
695 <0 0x11c90000 0 0x1000>;
706 reg = <0 0x11250000 0 0x1000>,
707 <0 0x11c60000 0 0x1000>;
721 reg = <0 0x112a0000 0 0x1000>;
733 reg = <0 0x11c00000 0 0x800>;
736 #clock-cells = <0>;
737 #phy-cells = <0>;
744 ranges = <0 0 0x11cc0000 0x9000>;
746 u2port0: usb-phy@0 {
747 reg = <0x0 0x400>;
755 reg = <0x1000 0x400>;
765 reg = <0 0x14000000 0 0x1000>;
769 #size-cells = <0>;
771 mmsys_main: endpoint@0 {
772 reg = <0>;
784 reg = <0 0x14001000 0 0x1000>;
791 reg = <0 0x14002000 0 0x1000>;
803 reg = <0 0x14003000 0 0x1000>;
809 mediatek,larb-id = <0>;
814 reg = <0 0x1400b000 0 0x1000>;
821 #size-cells = <0>;
823 port@0 {
825 #size-cells = <0>;
826 reg = <0>;
827 ovl0_in: endpoint@0 {
828 reg = <0>;
835 #size-cells = <0>;
837 ovl0_out: endpoint@0 {
838 reg = <0>;
847 reg = <0 0x1400d000 0 0x1000>;
855 #size-cells = <0>;
857 port@0 {
859 #size-cells = <0>;
860 reg = <0>;
861 rdma0_in: endpoint@0 {
862 reg = <0>;
869 #size-cells = <0>;
871 rdma0_out: endpoint@0 {
872 reg = <0>;
881 reg = <0 0x1400f000 0 0x1000>;
887 #size-cells = <0>;
889 port@0 {
891 #size-cells = <0>;
892 reg = <0>;
893 color0_in: endpoint@0 {
894 reg = <0>;
901 #size-cells = <0>;
903 color0_out: endpoint@0 {
904 reg = <0>;
913 reg = <0 0x14010000 0 0x1000>;
919 #size-cells = <0>;
921 port@0 {
923 #size-cells = <0>;
924 reg = <0>;
925 ccorr0_in: endpoint@0 {
926 reg = <0>;
933 #size-cells = <0>;
935 ccorr0_out: endpoint@0 {
936 reg = <0>;
945 reg = <0 0x14011000 0 0x1000>;
951 #size-cells = <0>;
953 port@0 {
955 #size-cells = <0>;
956 reg = <0>;
957 aal0_in: endpoint@0 {
958 reg = <0>;
965 #size-cells = <0>;
967 aal0_out: endpoint@0 {
968 reg = <0>;
977 reg = <0 0x14012000 0 0x1000>;
983 #size-cells = <0>;
985 port@0 {
987 #size-cells = <0>;
988 reg = <0>;
989 gamma0_in: endpoint@0 {
990 reg = <0>;
997 #size-cells = <0>;
999 gamma0_out: endpoint@0 {
1000 reg = <0>;
1009 reg = <0 0x14013000 0 0x1000>;
1015 #size-cells = <0>;
1017 port@0 {
1019 #size-cells = <0>;
1020 reg = <0>;
1021 dither0_in: endpoint@0 {
1022 reg = <0>;
1029 #size-cells = <0>;
1031 dither0_out: endpoint@0 {
1032 reg = <0>;
1040 reg = <0 0x14014000 0 0x1000>;
1053 reg = <0 0x14016000 0 0x1000>;
1061 #size-cells = <0>;
1063 port@0 {
1065 #size-cells = <0>;
1066 reg = <0>;
1075 #size-cells = <0>;
1086 reg = <0 0x14018000 0 0x1000>;
1098 reg = <0 0x15000000 0 0x1000>;
1105 reg = <0 0x15001000 0 0x1000>;
1116 reg = <0 0x16000000 0 0x1000>;
1123 reg = <0 0x16010000 0 0x1000>;
1134 reg = <0 0x17000000 0 0x1000>;
1141 reg = <0 0x17010000 0 0x1000>;
1151 reg = <0 0x19020000 0 0x1000>;
1157 reg = <0 0x11220000 0 0x1000>;
1158 #sound-dai-cells = <0>;
1205 #clock-cells = <0>;
1210 reg = <0 0x10017000 0 0x100>;