Lines Matching +full:imx93 +full:- +full:adc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2024-2025 NXP
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx94-clock.h"
12 #include "imx94-pinfunc.h"
13 #include "imx94-power.h"
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&gic>;
20 osc_24m: clock-24m {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24000000>;
24 clock-output-names = "osc_24m";
27 dummy: clock-dummy {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <0>;
31 clock-output-names = "dummy";
34 clk_ext1: clock-ext1 {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <133000000>;
38 clock-output-names = "clk_ext1";
41 sai1_mclk: clock-sai1-mclk1 {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
45 clock-output-names = "sai1_mclk";
48 sai2_mclk: clock-sai2-mclk1 {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <0>;
52 clock-output-names = "sai2_mclk";
55 sai3_mclk: clock-sai3-mclk1 {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 clock-output-names = "sai3_mclk";
62 sai4_mclk: clock-sai4-mclk1 {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 clock-output-names = "sai4_mclk";
72 #address-cells = <1>;
73 #size-cells = <0>;
76 arm,max-rx-timeout-ms = <5000>;
80 #power-domain-cells = <1>;
89 #power-domain-cells = <1>;
94 #clock-cells = <1>;
112 compatible = "fsl,imx943-aonmix-mqs";
117 compatible = "fsl,imx943-wakeupmix-mqs";
122 compatible = "arm,cortex-a55-pmu";
127 compatible = "arm,psci-1.0";
132 compatible = "arm,armv8-timer";
137 clock-frequency = <24000000>;
138 interrupt-parent = <&gic>;
139 arm,no-tick-in-suspend;
142 gic: interrupt-controller@48000000 {
143 compatible = "arm,gic-v3";
147 #interrupt-cells = <3>;
148 interrupt-controller;
150 #address-cells = <2>;
151 #size-cells = <2>;
152 dma-noncoherent;
153 interrupt-parent = <&gic>;
155 its: msi-controller@48040000 {
156 compatible = "arm,gic-v3-its";
158 #msi-cells = <1>;
159 dma-noncoherent;
160 msi-controller;
165 compatible = "simple-bus";
167 #address-cells = <2>;
168 #size-cells = <2>;
171 compatible = "fsl,aips-bus", "simple-bus";
174 #address-cells = <1>;
175 #size-cells = <1>;
177 edma2: dma-controller@42000000 {
178 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5";
181 clock-names = "dma";
182 #dma-cells = <3>;
183 dma-channels = <64>;
184 interrupts-extended = <&a55_irqsteer 0>, <&a55_irqsteer 1>,
220 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
224 #mbox-cells = <2>;
229 compatible = "silvaco,i3c-master-v1";
232 #address-cells = <3>;
233 #size-cells = <0>;
237 clock-names = "pclk", "fast_clk", "slow_clk";
242 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
245 #address-cells = <1>;
246 #size-cells = <0>;
249 clock-names = "per", "ipg";
251 dma-names = "tx", "rx";
256 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
259 #address-cells = <1>;
260 #size-cells = <0>;
263 clock-names = "per", "ipg";
265 dma-names = "tx", "rx";
270 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
273 #address-cells = <1>;
274 #size-cells = <0>;
277 clock-names = "per", "ipg";
279 dma-names = "tx", "rx";
284 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
287 #address-cells = <1>;
288 #size-cells = <0>;
291 clock-names = "per", "ipg";
293 dma-names = "tx", "rx";
298 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
299 "fsl,imx7ulp-lpuart";
303 clock-names = "ipg";
305 dma-names = "rx", "tx";
310 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
311 "fsl,imx7ulp-lpuart";
315 clock-names = "ipg";
317 dma-names = "rx", "tx";
322 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
323 "fsl,imx7ulp-lpuart";
327 clock-names = "ipg";
329 dma-names = "rx", "tx";
334 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
335 "fsl,imx7ulp-lpuart";
339 clock-names = "ipg";
341 dma-names = "rx", "tx";
346 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
351 clock-names = "ipg", "per";
352 assigned-clocks = <&scmi_clk IMX94_CLK_CAN2>;
353 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
354 assigned-clock-rates = <80000000>;
355 fsl,clk-source = /bits/ 8 <0>;
360 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
365 clock-names = "ipg", "per";
366 assigned-clocks = <&scmi_clk IMX94_CLK_CAN3>;
367 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
368 assigned-clock-rates = <80000000>;
369 fsl,clk-source = /bits/ 8 <0>;
374 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
379 clock-names = "ipg", "per";
380 assigned-clocks = <&scmi_clk IMX94_CLK_CAN4>;
381 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
382 assigned-clock-rates = <80000000>;
383 fsl,clk-source = /bits/ 8 <0>;
388 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
393 clock-names = "ipg", "per";
394 assigned-clocks = <&scmi_clk IMX94_CLK_CAN5>;
395 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
396 assigned-clock-rates = <80000000>;
397 fsl,clk-source = /bits/ 8 <0>;
402 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
407 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
409 dma-names = "rx", "tx";
410 #sound-dai-cells = <0>;
415 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
420 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
422 dma-names = "rx", "tx";
423 #sound-dai-cells = <0>;
428 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
433 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
435 dma-names = "rx", "tx";
436 #sound-dai-cells = <0>;
441 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
442 "fsl,imx7ulp-lpuart";
446 clock-names = "ipg";
448 dma-names = "rx", "tx";
453 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
454 "fsl,imx7ulp-lpuart";
458 clock-names = "ipg";
460 dma-names = "rx", "tx";
465 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
468 #address-cells = <1>;
469 #size-cells = <0>;
472 clock-names = "per", "ipg";
474 dma-names = "tx", "rx";
479 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
482 #address-cells = <1>;
483 #size-cells = <0>;
486 clock-names = "per", "ipg";
488 dma-names = "tx", "rx";
493 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
496 #address-cells = <1>;
497 #size-cells = <0>;
500 clock-names = "per", "ipg";
502 dma-names = "tx", "rx";
507 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
510 #address-cells = <1>;
511 #size-cells = <0>;
514 clock-names = "per", "ipg";
516 dma-names = "tx", "rx";
521 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
524 #address-cells = <1>;
525 #size-cells = <0>;
528 clock-names = "per", "ipg";
530 dma-names = "tx", "rx";
535 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
538 #address-cells = <1>;
539 #size-cells = <0>;
542 clock-names = "per", "ipg";
544 dma-names = "tx", "rx";
549 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
552 #address-cells = <1>;
553 #size-cells = <0>;
556 clock-names = "per", "ipg";
558 dma-names = "tx", "rx";
563 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
566 #address-cells = <1>;
567 #size-cells = <0>;
570 clock-names = "per", "ipg";
572 dma-names = "tx", "rx";
577 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
581 #mbox-cells = <2>;
585 edma4: dma-controller@42df0000 {
586 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5";
589 clock-names = "dma";
590 #dma-cells = <3>;
591 dma-channels = <64>;
592 interrupts-extended = <&a55_irqsteer 128>, <&a55_irqsteer 129>,
629 compatible = "fsl,aips-bus", "simple-bus";
633 #address-cells = <1>;
634 #size-cells = <1>;
637 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";
643 clock-names = "ipg", "ahb", "per";
644 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC1>;
645 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>;
646 assigned-clock-rates = <400000000>;
647 bus-width = <8>;
648 fsl,tuning-start-tap = <1>;
649 fsl,tuning-step = <2>;
654 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";
660 clock-names = "ipg", "ahb", "per";
661 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC2>;
662 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>;
663 assigned-clock-rates = <200000000>;
664 bus-width = <4>;
665 fsl,tuning-start-tap = <1>;
666 fsl,tuning-step = <2>;
671 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";
677 clock-names = "ipg", "ahb", "per";
678 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC3>;
679 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>;
680 assigned-clock-rates = <200000000>;
681 bus-width = <4>;
682 fsl,tuning-start-tap = <1>;
683 fsl,tuning-step = <2>;
688 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
689 "fsl,imx7ulp-lpuart";
693 clock-names = "ipg";
695 dma-names = "rx", "tx";
700 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
701 "fsl,imx7ulp-lpuart";
705 clock-names = "ipg";
707 dma-names = "rx", "tx";
712 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
713 "fsl,imx7ulp-lpuart";
717 clock-names = "ipg";
719 dma-names = "rx", "tx";
724 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
725 "fsl,imx7ulp-lpuart";
729 clock-names = "ipg";
731 dma-names = "rx", "tx";
736 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
740 #mbox-cells = <2>;
745 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
749 #mbox-cells = <2>;
754 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
758 #mbox-cells = <2>;
763 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
767 #mbox-cells = <2>;
772 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
776 #mbox-cells = <2>;
781 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
785 #mbox-cells = <2>;
791 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
793 #interrupt-cells = <2>;
794 interrupt-controller;
797 #gpio-cells = <2>;
798 gpio-controller;
799 gpio-ranges = <&scmi_iomuxc 0 4 32>;
804 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
806 #interrupt-cells = <2>;
807 interrupt-controller;
810 #gpio-cells = <2>;
811 gpio-controller;
812 gpio-ranges = <&scmi_iomuxc 0 36 26>;
817 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
819 #interrupt-cells = <2>;
820 interrupt-controller;
823 #gpio-cells = <2>;
824 gpio-controller;
825 gpio-ranges = <&scmi_iomuxc 0 62 4>, <&scmi_iomuxc 4 0 4>,
831 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
833 #interrupt-cells = <2>;
834 interrupt-controller;
837 #gpio-cells = <2>;
838 gpio-controller;
839 gpio-ranges = <&scmi_iomuxc 0 108 32>;
844 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
846 #interrupt-cells = <2>;
847 interrupt-controller;
850 #gpio-cells = <2>;
851 gpio-controller;
852 gpio-ranges = <&scmi_iomuxc 0 66 32>;
857 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
859 #interrupt-cells = <2>;
860 interrupt-controller;
863 #gpio-cells = <2>;
864 gpio-controller;
865 gpio-ranges = <&scmi_iomuxc 0 98 10>, <&scmi_iomuxc 16 152 12>;
866 gpio-reserved-ranges = <10 6>;
871 compatible = "fsl,aips-bus", "simple-bus";
874 #address-cells = <1>;
875 #size-cells = <1>;
877 edma1: dma-controller@44000000 {
878 compatible = "fsl,imx94-edma3", "fsl,imx93-edma3";
914 clock-names = "dma";
915 #dma-cells = <3>;
916 dma-channels = <32>;
920 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
924 #mbox-cells = <2>;
929 compatible = "nxp,imx94-sysctr-timer", "nxp,imx95-sysctr-timer";
933 clock-names = "per";
934 nxp,no-divider;
938 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm";
941 #pwm-cells = <3>;
946 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm";
949 #pwm-cells = <3>;
954 compatible = "silvaco,i3c-master-v1";
957 #address-cells = <3>;
958 #size-cells = <0>;
962 clock-names = "pclk", "fast_clk", "slow_clk";
967 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
970 #address-cells = <1>;
971 #size-cells = <0>;
974 clock-names = "per", "ipg";
976 dma-names = "tx", "rx";
981 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
984 #address-cells = <1>;
985 #size-cells = <0>;
988 clock-names = "per", "ipg";
990 dma-names = "tx", "rx";
995 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
998 #address-cells = <1>;
999 #size-cells = <0>;
1002 clock-names = "per", "ipg";
1004 dma-names = "tx", "rx";
1009 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1016 clock-names = "per", "ipg";
1018 dma-names = "tx", "rx";
1023 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
1024 "fsl,imx7ulp-lpuart";
1028 clock-names = "ipg";
1030 dma-names = "rx", "tx";
1035 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
1036 "fsl,imx7ulp-lpuart";
1040 clock-names = "ipg";
1042 dma-names = "rx", "tx";
1047 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
1052 clock-names = "ipg", "per";
1053 assigned-clocks = <&scmi_clk IMX94_CLK_CAN1>;
1054 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
1055 assigned-clock-rates = <80000000>;
1056 fsl,clk-source = /bits/ 8 <0>;
1061 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
1067 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1069 dma-names = "rx", "tx";
1070 #sound-dai-cells = <0>;
1075 compatible = "fsl,imx943-micfil";
1086 clock-names = "ipg_clk", "ipg_clk_app",
1089 dma-names = "rx";
1090 #sound-dai-cells = <0>;
1094 adc1: adc@44530000 {
1095 compatible = "nxp,imx94-adc", "nxp,imx93-adc";
1101 clock-names = "ipg";
1102 #io-channel-cells = <1>;
1107 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1111 #address-cells = <1>;
1112 #size-cells = <1>;
1113 #mbox-cells = <2>;
1116 compatible = "mmio-sram";
1119 #address-cells = <1>;
1120 #size-cells = <1>;
1122 scmi_buf0: scmi-sram-section@0 {
1123 compatible = "arm,scmi-shmem";
1127 scmi_buf1: scmi-sram-section@80 {
1128 compatible = "arm,scmi-shmem";
1135 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1138 #mbox-cells = <2>;
1143 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1146 #mbox-cells = <2>;
1151 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1154 #mbox-cells = <2>;
1158 a55_irqsteer: interrupt-controller@446a0000 {
1159 compatible = "fsl,imx94-irqsteer", "fsl,imx-irqsteer";
1161 #interrupt-cells = <1>;
1162 interrupt-controller;
1170 clock-names = "ipg";
1172 fsl,num-irqs = <960>;
1177 compatible = "fsl,aips-bus", "simple-bus";
1180 #address-cells = <1>;
1181 #size-cells = <1>;
1184 compatible = "fsl,imx94-wdt", "fsl,imx93-wdt";
1188 timeout-sec = <40>;
1189 fsl,ext-reset-output;
1194 ddr-pmu@4e090dc0 {
1195 compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu";