Lines Matching +full:imx7ulp +full:- +full:edma
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2024-2025 NXP
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx94-clock.h"
12 #include "imx94-pinfunc.h"
13 #include "imx94-power.h"
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&gic>;
20 osc_24m: clock-24m {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24000000>;
24 clock-output-names = "osc_24m";
27 dummy: clock-dummy {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <0>;
31 clock-output-names = "dummy";
34 clk_ext1: clock-ext1 {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <133000000>;
38 clock-output-names = "clk_ext1";
41 sai1_mclk: clock-sai1-mclk1 {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
45 clock-output-names = "sai1_mclk";
48 sai2_mclk: clock-sai2-mclk1 {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <0>;
52 clock-output-names = "sai2_mclk";
55 sai3_mclk: clock-sai3-mclk1 {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 clock-output-names = "sai3_mclk";
62 sai4_mclk: clock-sai4-mclk1 {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 clock-output-names = "sai4_mclk";
72 #address-cells = <1>;
73 #size-cells = <0>;
76 arm,max-rx-timeout-ms = <5000>;
80 #power-domain-cells = <1>;
89 #power-domain-cells = <1>;
94 #clock-cells = <1>;
112 compatible = "arm,cortex-a55-pmu";
117 compatible = "arm,psci-1.0";
122 compatible = "arm,armv8-timer";
127 clock-frequency = <24000000>;
128 interrupt-parent = <&gic>;
129 arm,no-tick-in-suspend;
132 gic: interrupt-controller@48000000 {
133 compatible = "arm,gic-v3";
137 #interrupt-cells = <3>;
138 interrupt-controller;
140 #address-cells = <2>;
141 #size-cells = <2>;
142 dma-noncoherent;
143 interrupt-parent = <&gic>;
145 its: msi-controller@48040000 {
146 compatible = "arm,gic-v3-its";
148 #msi-cells = <1>;
149 dma-noncoherent;
150 msi-controller;
155 compatible = "simple-bus";
157 #address-cells = <2>;
158 #size-cells = <2>;
161 compatible = "fsl,aips-bus", "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
167 edma2: dma-controller@42000000 {
168 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5";
171 clock-names = "dma";
172 #dma-cells = <3>;
173 dma-channels = <64>;
174 interrupts-extended = <&a55_irqsteer 0>, <&a55_irqsteer 1>,
209 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
213 #mbox-cells = <2>;
218 compatible = "silvaco,i3c-master-v1";
221 #address-cells = <3>;
222 #size-cells = <0>;
226 clock-names = "pclk", "fast_clk", "slow_clk";
231 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
234 #address-cells = <1>;
235 #size-cells = <0>;
238 clock-names = "per", "ipg";
240 dma-names = "tx", "rx";
245 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
248 #address-cells = <1>;
249 #size-cells = <0>;
252 clock-names = "per", "ipg";
254 dma-names = "tx", "rx";
259 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
262 #address-cells = <1>;
263 #size-cells = <0>;
266 clock-names = "per", "ipg";
268 dma-names = "tx", "rx";
273 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
276 #address-cells = <1>;
277 #size-cells = <0>;
280 clock-names = "per", "ipg";
282 dma-names = "tx", "rx";
287 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
288 "fsl,imx7ulp-lpuart";
292 clock-names = "ipg";
294 dma-names = "rx", "tx";
299 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
300 "fsl,imx7ulp-lpuart";
304 clock-names = "ipg";
306 dma-names = "rx", "tx";
311 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
312 "fsl,imx7ulp-lpuart";
316 clock-names = "ipg";
318 dma-names = "rx", "tx";
323 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
324 "fsl,imx7ulp-lpuart";
328 clock-names = "ipg";
330 dma-names = "rx", "tx";
335 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
340 clock-names = "ipg", "per";
341 assigned-clocks = <&scmi_clk IMX94_CLK_CAN2>;
342 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
343 assigned-clock-rates = <80000000>;
344 fsl,clk-source = /bits/ 8 <0>;
349 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
354 clock-names = "ipg", "per";
355 assigned-clocks = <&scmi_clk IMX94_CLK_CAN3>;
356 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
357 assigned-clock-rates = <80000000>;
358 fsl,clk-source = /bits/ 8 <0>;
363 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
368 clock-names = "ipg", "per";
369 assigned-clocks = <&scmi_clk IMX94_CLK_CAN4>;
370 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
371 assigned-clock-rates = <80000000>;
372 fsl,clk-source = /bits/ 8 <0>;
377 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
382 clock-names = "ipg", "per";
383 assigned-clocks = <&scmi_clk IMX94_CLK_CAN5>;
384 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
385 assigned-clock-rates = <80000000>;
386 fsl,clk-source = /bits/ 8 <0>;
391 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
396 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
398 dma-names = "rx", "tx";
399 #sound-dai-cells = <0>;
404 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
409 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
411 dma-names = "rx", "tx";
412 #sound-dai-cells = <0>;
417 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
422 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
424 dma-names = "rx", "tx";
425 #sound-dai-cells = <0>;
430 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
431 "fsl,imx7ulp-lpuart";
435 clock-names = "ipg";
437 dma-names = "rx", "tx";
442 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
443 "fsl,imx7ulp-lpuart";
447 clock-names = "ipg";
449 dma-names = "rx", "tx";
454 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
457 #address-cells = <1>;
458 #size-cells = <0>;
461 clock-names = "per", "ipg";
463 dma-names = "tx", "rx";
468 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
471 #address-cells = <1>;
472 #size-cells = <0>;
475 clock-names = "per", "ipg";
477 dma-names = "tx", "rx";
482 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
485 #address-cells = <1>;
486 #size-cells = <0>;
489 clock-names = "per", "ipg";
491 dma-names = "tx", "rx";
496 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
499 #address-cells = <1>;
500 #size-cells = <0>;
503 clock-names = "per", "ipg";
505 dma-names = "tx", "rx";
510 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
513 #address-cells = <1>;
514 #size-cells = <0>;
517 clock-names = "per", "ipg";
519 dma-names = "tx", "rx";
524 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
527 #address-cells = <1>;
528 #size-cells = <0>;
531 clock-names = "per", "ipg";
533 dma-names = "tx", "rx";
538 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
541 #address-cells = <1>;
542 #size-cells = <0>;
545 clock-names = "per", "ipg";
547 dma-names = "tx", "rx";
552 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
555 #address-cells = <1>;
556 #size-cells = <0>;
559 clock-names = "per", "ipg";
561 dma-names = "tx", "rx";
566 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
570 #mbox-cells = <2>;
574 edma4: dma-controller@42df0000 {
575 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5";
578 clock-names = "dma";
579 #dma-cells = <3>;
580 dma-channels = <64>;
581 interrupts-extended = <&a55_irqsteer 128>, <&a55_irqsteer 129>,
617 compatible = "fsl,aips-bus", "simple-bus";
621 #address-cells = <1>;
622 #size-cells = <1>;
625 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";
631 clock-names = "ipg", "ahb", "per";
632 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC1>;
633 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>;
634 assigned-clock-rates = <400000000>;
635 bus-width = <8>;
636 fsl,tuning-start-tap = <1>;
637 fsl,tuning-step = <2>;
642 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";
648 clock-names = "ipg", "ahb", "per";
649 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC2>;
650 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>;
651 assigned-clock-rates = <200000000>;
652 bus-width = <4>;
653 fsl,tuning-start-tap = <1>;
654 fsl,tuning-step = <2>;
659 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";
665 clock-names = "ipg", "ahb", "per";
666 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC3>;
667 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>;
668 assigned-clock-rates = <200000000>;
669 bus-width = <4>;
670 fsl,tuning-start-tap = <1>;
671 fsl,tuning-step = <2>;
676 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
677 "fsl,imx7ulp-lpuart";
681 clock-names = "ipg";
683 dma-names = "rx", "tx";
688 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
689 "fsl,imx7ulp-lpuart";
693 clock-names = "ipg";
695 dma-names = "rx", "tx";
700 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
701 "fsl,imx7ulp-lpuart";
705 clock-names = "ipg";
707 dma-names = "rx", "tx";
712 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
713 "fsl,imx7ulp-lpuart";
717 clock-names = "ipg";
719 dma-names = "rx", "tx";
724 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
728 #mbox-cells = <2>;
733 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
737 #mbox-cells = <2>;
742 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
746 #mbox-cells = <2>;
751 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
755 #mbox-cells = <2>;
760 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
764 #mbox-cells = <2>;
769 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
773 #mbox-cells = <2>;
779 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
781 #interrupt-cells = <2>;
782 interrupt-controller;
785 #gpio-cells = <2>;
786 gpio-controller;
787 gpio-ranges = <&scmi_iomuxc 0 4 32>;
791 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
793 #interrupt-cells = <2>;
794 interrupt-controller;
797 #gpio-cells = <2>;
798 gpio-controller;
799 gpio-ranges = <&scmi_iomuxc 0 36 26>;
803 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
805 #interrupt-cells = <2>;
806 interrupt-controller;
809 #gpio-cells = <2>;
810 gpio-controller;
811 gpio-ranges = <&scmi_iomuxc 0 62 4>, <&scmi_iomuxc 4 0 4>,
816 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
818 #interrupt-cells = <2>;
819 interrupt-controller;
822 #gpio-cells = <2>;
823 gpio-controller;
824 gpio-ranges = <&scmi_iomuxc 0 108 32>;
828 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
830 #interrupt-cells = <2>;
831 interrupt-controller;
834 #gpio-cells = <2>;
835 gpio-controller;
836 gpio-ranges = <&scmi_iomuxc 0 66 32>;
840 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
842 #interrupt-cells = <2>;
843 interrupt-controller;
846 #gpio-cells = <2>;
847 gpio-controller;
848 gpio-ranges = <&scmi_iomuxc 0 98 10>, <&scmi_iomuxc 16 152 12>;
852 compatible = "fsl,aips-bus", "simple-bus";
855 #address-cells = <1>;
856 #size-cells = <1>;
858 edma1: dma-controller@44000000 {
859 compatible = "fsl,imx94-edma3", "fsl,imx93-edma3";
895 clock-names = "dma";
896 #dma-cells = <3>;
897 dma-channels = <32>;
901 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
905 #mbox-cells = <2>;
910 compatible = "nxp,imx94-sysctr-timer", "nxp,imx95-sysctr-timer";
914 clock-names = "per";
915 nxp,no-divider;
919 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm";
922 #pwm-cells = <3>;
927 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm";
930 #pwm-cells = <3>;
935 compatible = "silvaco,i3c-master-v1";
938 #address-cells = <3>;
939 #size-cells = <0>;
943 clock-names = "pclk", "fast_clk", "slow_clk";
948 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
951 #address-cells = <1>;
952 #size-cells = <0>;
955 clock-names = "per", "ipg";
957 dma-names = "tx", "rx";
962 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
965 #address-cells = <1>;
966 #size-cells = <0>;
969 clock-names = "per", "ipg";
971 dma-names = "tx", "rx";
976 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
979 #address-cells = <1>;
980 #size-cells = <0>;
983 clock-names = "per", "ipg";
985 dma-names = "tx", "rx";
990 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
993 #address-cells = <1>;
994 #size-cells = <0>;
997 clock-names = "per", "ipg";
999 dma-names = "tx", "rx";
1004 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
1005 "fsl,imx7ulp-lpuart";
1009 clock-names = "ipg";
1011 dma-names = "rx", "tx";
1016 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
1017 "fsl,imx7ulp-lpuart";
1021 clock-names = "ipg";
1023 dma-names = "rx", "tx";
1028 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
1035 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
1041 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1043 dma-names = "rx", "tx";
1044 #sound-dai-cells = <0>;
1049 compatible = "nxp,imx94-adc", "nxp,imx93-adc";
1055 clock-names = "ipg";
1056 #io-channel-cells = <1>;
1061 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1065 #address-cells = <1>;
1066 #size-cells = <1>;
1067 #mbox-cells = <2>;
1070 compatible = "mmio-sram";
1073 #address-cells = <1>;
1074 #size-cells = <1>;
1076 scmi_buf0: scmi-sram-section@0 {
1077 compatible = "arm,scmi-shmem";
1081 scmi_buf1: scmi-sram-section@80 {
1082 compatible = "arm,scmi-shmem";
1089 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1092 #mbox-cells = <2>;
1097 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1100 #mbox-cells = <2>;
1105 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1108 #mbox-cells = <2>;
1112 a55_irqsteer: interrupt-controller@446a0000 {
1113 compatible = "fsl,imx94-irqsteer", "fsl,imx-irqsteer";
1115 #interrupt-cells = <1>;
1116 interrupt-controller;
1124 clock-names = "ipg";
1126 fsl,num-irqs = <960>;
1131 compatible = "fsl,aips-bus", "simple-bus";
1134 #address-cells = <1>;
1135 #size-cells = <1>;
1138 compatible = "fsl,imx94-wdt", "fsl,imx93-wdt";
1142 timeout-sec = <40>;
1143 fsl,ext-reset-output;