Lines Matching +full:dma +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2024-2025 NXP
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx94-clock.h"
12 #include "imx94-pinfunc.h"
13 #include "imx94-power.h"
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&gic>;
20 osc_24m: clock-24m {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24000000>;
24 clock-output-names = "osc_24m";
27 dummy: clock-dummy {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <0>;
31 clock-output-names = "dummy";
34 clk_ext1: clock-ext1 {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <133000000>;
38 clock-output-names = "clk_ext1";
41 sai1_mclk: clock-sai1-mclk1 {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
45 clock-output-names = "sai1_mclk";
48 sai2_mclk: clock-sai2-mclk1 {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <0>;
52 clock-output-names = "sai2_mclk";
55 sai3_mclk: clock-sai3-mclk1 {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 clock-output-names = "sai3_mclk";
62 sai4_mclk: clock-sai4-mclk1 {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 clock-output-names = "sai4_mclk";
72 #address-cells = <1>;
73 #size-cells = <0>;
76 arm,max-rx-timeout-ms = <5000>;
80 #power-domain-cells = <1>;
89 #power-domain-cells = <1>;
94 #clock-cells = <1>;
112 compatible = "fsl,imx943-aonmix-mqs";
117 compatible = "fsl,imx943-wakeupmix-mqs";
122 compatible = "arm,cortex-a55-pmu";
127 compatible = "arm,psci-1.0";
132 compatible = "arm,armv8-timer";
137 clock-frequency = <24000000>;
138 interrupt-parent = <&gic>;
139 arm,no-tick-in-suspend;
142 gic: interrupt-controller@48000000 {
143 compatible = "arm,gic-v3";
147 #interrupt-cells = <3>;
148 interrupt-controller;
150 #address-cells = <2>;
151 #size-cells = <2>;
152 dma-noncoherent;
153 interrupt-parent = <&gic>;
155 its: msi-controller@48040000 {
156 compatible = "arm,gic-v3-its";
158 #msi-cells = <1>;
159 dma-noncoherent;
160 msi-controller;
165 compatible = "simple-bus";
167 #address-cells = <2>;
168 #size-cells = <2>;
171 compatible = "fsl,aips-bus", "simple-bus";
174 #address-cells = <1>;
175 #size-cells = <1>;
177 edma2: dma-controller@42000000 {
178 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5";
181 clock-names = "dma";
182 #dma-cells = <3>;
183 dma-channels = <64>;
184 interrupts-extended = <&a55_irqsteer 0>, <&a55_irqsteer 1>,
219 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
223 #mbox-cells = <2>;
228 compatible = "silvaco,i3c-master-v1";
231 #address-cells = <3>;
232 #size-cells = <0>;
236 clock-names = "pclk", "fast_clk", "slow_clk";
241 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
244 #address-cells = <1>;
245 #size-cells = <0>;
248 clock-names = "per", "ipg";
250 dma-names = "tx", "rx";
255 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
258 #address-cells = <1>;
259 #size-cells = <0>;
262 clock-names = "per", "ipg";
264 dma-names = "tx", "rx";
269 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
272 #address-cells = <1>;
273 #size-cells = <0>;
276 clock-names = "per", "ipg";
278 dma-names = "tx", "rx";
283 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
286 #address-cells = <1>;
287 #size-cells = <0>;
290 clock-names = "per", "ipg";
292 dma-names = "tx", "rx";
297 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
298 "fsl,imx7ulp-lpuart";
302 clock-names = "ipg";
304 dma-names = "rx", "tx";
309 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
310 "fsl,imx7ulp-lpuart";
314 clock-names = "ipg";
316 dma-names = "rx", "tx";
321 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
322 "fsl,imx7ulp-lpuart";
326 clock-names = "ipg";
328 dma-names = "rx", "tx";
333 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
334 "fsl,imx7ulp-lpuart";
338 clock-names = "ipg";
340 dma-names = "rx", "tx";
345 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
350 clock-names = "ipg", "per";
351 assigned-clocks = <&scmi_clk IMX94_CLK_CAN2>;
352 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
353 assigned-clock-rates = <80000000>;
354 fsl,clk-source = /bits/ 8 <0>;
359 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
364 clock-names = "ipg", "per";
365 assigned-clocks = <&scmi_clk IMX94_CLK_CAN3>;
366 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
367 assigned-clock-rates = <80000000>;
368 fsl,clk-source = /bits/ 8 <0>;
373 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
378 clock-names = "ipg", "per";
379 assigned-clocks = <&scmi_clk IMX94_CLK_CAN4>;
380 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
381 assigned-clock-rates = <80000000>;
382 fsl,clk-source = /bits/ 8 <0>;
387 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
392 clock-names = "ipg", "per";
393 assigned-clocks = <&scmi_clk IMX94_CLK_CAN5>;
394 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
395 assigned-clock-rates = <80000000>;
396 fsl,clk-source = /bits/ 8 <0>;
401 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
406 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
408 dma-names = "rx", "tx";
409 #sound-dai-cells = <0>;
414 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
419 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
421 dma-names = "rx", "tx";
422 #sound-dai-cells = <0>;
427 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
432 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
434 dma-names = "rx", "tx";
435 #sound-dai-cells = <0>;
440 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
441 "fsl,imx7ulp-lpuart";
445 clock-names = "ipg";
447 dma-names = "rx", "tx";
452 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
453 "fsl,imx7ulp-lpuart";
457 clock-names = "ipg";
459 dma-names = "rx", "tx";
464 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
467 #address-cells = <1>;
468 #size-cells = <0>;
471 clock-names = "per", "ipg";
473 dma-names = "tx", "rx";
478 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
481 #address-cells = <1>;
482 #size-cells = <0>;
485 clock-names = "per", "ipg";
487 dma-names = "tx", "rx";
492 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
495 #address-cells = <1>;
496 #size-cells = <0>;
499 clock-names = "per", "ipg";
501 dma-names = "tx", "rx";
506 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
509 #address-cells = <1>;
510 #size-cells = <0>;
513 clock-names = "per", "ipg";
515 dma-names = "tx", "rx";
520 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
523 #address-cells = <1>;
524 #size-cells = <0>;
527 clock-names = "per", "ipg";
529 dma-names = "tx", "rx";
534 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
537 #address-cells = <1>;
538 #size-cells = <0>;
541 clock-names = "per", "ipg";
543 dma-names = "tx", "rx";
548 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
551 #address-cells = <1>;
552 #size-cells = <0>;
555 clock-names = "per", "ipg";
557 dma-names = "tx", "rx";
562 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
565 #address-cells = <1>;
566 #size-cells = <0>;
569 clock-names = "per", "ipg";
571 dma-names = "tx", "rx";
576 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
580 #mbox-cells = <2>;
584 edma4: dma-controller@42df0000 {
585 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5";
588 clock-names = "dma";
589 #dma-cells = <3>;
590 dma-channels = <64>;
591 interrupts-extended = <&a55_irqsteer 128>, <&a55_irqsteer 129>,
627 compatible = "fsl,aips-bus", "simple-bus";
631 #address-cells = <1>;
632 #size-cells = <1>;
635 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";
641 clock-names = "ipg", "ahb", "per";
642 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC1>;
643 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>;
644 assigned-clock-rates = <400000000>;
645 bus-width = <8>;
646 fsl,tuning-start-tap = <1>;
647 fsl,tuning-step = <2>;
652 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";
658 clock-names = "ipg", "ahb", "per";
659 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC2>;
660 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>;
661 assigned-clock-rates = <200000000>;
662 bus-width = <4>;
663 fsl,tuning-start-tap = <1>;
664 fsl,tuning-step = <2>;
669 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc";
675 clock-names = "ipg", "ahb", "per";
676 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC3>;
677 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>;
678 assigned-clock-rates = <200000000>;
679 bus-width = <4>;
680 fsl,tuning-start-tap = <1>;
681 fsl,tuning-step = <2>;
686 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
687 "fsl,imx7ulp-lpuart";
691 clock-names = "ipg";
693 dma-names = "rx", "tx";
698 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
699 "fsl,imx7ulp-lpuart";
703 clock-names = "ipg";
705 dma-names = "rx", "tx";
710 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
711 "fsl,imx7ulp-lpuart";
715 clock-names = "ipg";
717 dma-names = "rx", "tx";
722 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
723 "fsl,imx7ulp-lpuart";
727 clock-names = "ipg";
729 dma-names = "rx", "tx";
734 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
738 #mbox-cells = <2>;
743 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
747 #mbox-cells = <2>;
752 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
756 #mbox-cells = <2>;
761 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
765 #mbox-cells = <2>;
770 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
774 #mbox-cells = <2>;
779 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
783 #mbox-cells = <2>;
789 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
791 #interrupt-cells = <2>;
792 interrupt-controller;
795 #gpio-cells = <2>;
796 gpio-controller;
797 gpio-ranges = <&scmi_iomuxc 0 4 32>;
802 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
804 #interrupt-cells = <2>;
805 interrupt-controller;
808 #gpio-cells = <2>;
809 gpio-controller;
810 gpio-ranges = <&scmi_iomuxc 0 36 26>;
815 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
817 #interrupt-cells = <2>;
818 interrupt-controller;
821 #gpio-cells = <2>;
822 gpio-controller;
823 gpio-ranges = <&scmi_iomuxc 0 62 4>, <&scmi_iomuxc 4 0 4>,
829 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
831 #interrupt-cells = <2>;
832 interrupt-controller;
835 #gpio-cells = <2>;
836 gpio-controller;
837 gpio-ranges = <&scmi_iomuxc 0 108 32>;
842 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
844 #interrupt-cells = <2>;
845 interrupt-controller;
848 #gpio-cells = <2>;
849 gpio-controller;
850 gpio-ranges = <&scmi_iomuxc 0 66 32>;
855 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio";
857 #interrupt-cells = <2>;
858 interrupt-controller;
861 #gpio-cells = <2>;
862 gpio-controller;
863 gpio-ranges = <&scmi_iomuxc 0 98 10>, <&scmi_iomuxc 16 152 12>;
864 gpio-reserved-ranges = <10 6>;
869 compatible = "fsl,aips-bus", "simple-bus";
872 #address-cells = <1>;
873 #size-cells = <1>;
875 edma1: dma-controller@44000000 {
876 compatible = "fsl,imx94-edma3", "fsl,imx93-edma3";
912 clock-names = "dma";
913 #dma-cells = <3>;
914 dma-channels = <32>;
918 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
922 #mbox-cells = <2>;
927 compatible = "nxp,imx94-sysctr-timer", "nxp,imx95-sysctr-timer";
931 clock-names = "per";
932 nxp,no-divider;
936 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm";
939 #pwm-cells = <3>;
944 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm";
947 #pwm-cells = <3>;
952 compatible = "silvaco,i3c-master-v1";
955 #address-cells = <3>;
956 #size-cells = <0>;
960 clock-names = "pclk", "fast_clk", "slow_clk";
965 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
968 #address-cells = <1>;
969 #size-cells = <0>;
972 clock-names = "per", "ipg";
974 dma-names = "tx", "rx";
979 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c";
982 #address-cells = <1>;
983 #size-cells = <0>;
986 clock-names = "per", "ipg";
988 dma-names = "tx", "rx";
993 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
996 #address-cells = <1>;
997 #size-cells = <0>;
1000 clock-names = "per", "ipg";
1002 dma-names = "tx", "rx";
1007 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi";
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1014 clock-names = "per", "ipg";
1016 dma-names = "tx", "rx";
1021 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
1022 "fsl,imx7ulp-lpuart";
1026 clock-names = "ipg";
1028 dma-names = "rx", "tx";
1033 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart",
1034 "fsl,imx7ulp-lpuart";
1038 clock-names = "ipg";
1040 dma-names = "rx", "tx";
1045 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan";
1050 clock-names = "ipg", "per";
1051 assigned-clocks = <&scmi_clk IMX94_CLK_CAN1>;
1052 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
1053 assigned-clock-rates = <80000000>;
1054 fsl,clk-source = /bits/ 8 <0>;
1059 compatible = "fsl,imx94-sai", "fsl,imx95-sai";
1065 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1067 dma-names = "rx", "tx";
1068 #sound-dai-cells = <0>;
1073 compatible = "fsl,imx943-micfil";
1084 clock-names = "ipg_clk", "ipg_clk_app",
1087 dma-names = "rx";
1088 #sound-dai-cells = <0>;
1093 compatible = "nxp,imx94-adc", "nxp,imx93-adc";
1099 clock-names = "ipg";
1100 #io-channel-cells = <1>;
1105 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1109 #address-cells = <1>;
1110 #size-cells = <1>;
1111 #mbox-cells = <2>;
1114 compatible = "mmio-sram";
1117 #address-cells = <1>;
1118 #size-cells = <1>;
1120 scmi_buf0: scmi-sram-section@0 {
1121 compatible = "arm,scmi-shmem";
1125 scmi_buf1: scmi-sram-section@80 {
1126 compatible = "arm,scmi-shmem";
1133 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1136 #mbox-cells = <2>;
1141 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1144 #mbox-cells = <2>;
1149 compatible = "fsl,imx94-mu", "fsl,imx95-mu";
1152 #mbox-cells = <2>;
1156 a55_irqsteer: interrupt-controller@446a0000 {
1157 compatible = "fsl,imx94-irqsteer", "fsl,imx-irqsteer";
1159 #interrupt-cells = <1>;
1160 interrupt-controller;
1168 clock-names = "ipg";
1170 fsl,num-irqs = <960>;
1175 compatible = "fsl,aips-bus", "simple-bus";
1178 #address-cells = <1>;
1179 #size-cells = <1>;
1182 compatible = "fsl,imx94-wdt", "fsl,imx93-wdt";
1186 timeout-sec = <40>;
1187 fsl,ext-reset-output;