Lines Matching +full:0 +full:x184
22 pinctrl-0 = <&pinctrl_led>;
40 pinctrl-0 = <&pinctrl_beeper>;
47 #clock-cells = <0>;
54 #size-cells = <0>;
56 pinctrl-0 = <&pinctrl_ecspi1>;
61 canfd: can@0 {
66 reg = <0>;
73 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
77 spidev@0 {
79 reg = <0>;
102 flash@0 {
103 reg = <0>;
160 "CPLD_D[0]", "", "", "",
201 pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
206 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4
212 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4
213 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4
214 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4
215 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4
221 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4
222 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4
229 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
237 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4
244 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4
246 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4
248 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4
250 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4
252 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
254 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x184
256 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x184
258 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x184
260 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x184
262 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x184
264 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x184
266 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x184
267 /* CPLD_D[0] */
268 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x184
270 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
272 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4
274 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4
276 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4
283 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4
285 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4
287 MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4
289 MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4
317 pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;