Lines Matching +full:imx7ulp +full:- +full:spi
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/dma/fsl-edma.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
11 dma_ipg_clk: clock-dma-ipg {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <120000000>;
15 clock-output-names = "dma_ipg_clk";
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
24 lpspi0: spi@5a000000 {
25 compatible = "fsl,imx7ulp-spi";
27 #address-cells = <1>;
28 #size-cells = <0>;
30 interrupt-parent = <&gic>;
33 clock-names = "per", "ipg";
34 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
35 assigned-clock-rates = <60000000>;
36 power-domains = <&pd IMX_SC_R_SPI_0>;
38 dma-names = "tx", "rx";
42 lpspi1: spi@5a010000 {
43 compatible = "fsl,imx7ulp-spi";
45 #address-cells = <1>;
46 #size-cells = <0>;
48 interrupt-parent = <&gic>;
51 clock-names = "per", "ipg";
52 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
53 assigned-clock-rates = <60000000>;
54 power-domains = <&pd IMX_SC_R_SPI_1>;
56 dma-names = "tx", "rx";
60 lpspi2: spi@5a020000 {
61 compatible = "fsl,imx7ulp-spi";
63 #address-cells = <1>;
64 #size-cells = <0>;
66 interrupt-parent = <&gic>;
69 clock-names = "per", "ipg";
70 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
71 assigned-clock-rates = <60000000>;
72 power-domains = <&pd IMX_SC_R_SPI_2>;
74 dma-names = "tx", "rx";
78 lpspi3: spi@5a030000 {
79 compatible = "fsl,imx7ulp-spi";
81 #address-cells = <1>;
82 #size-cells = <0>;
84 interrupt-parent = <&gic>;
87 clock-names = "per", "ipg";
88 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
89 assigned-clock-rates = <60000000>;
90 power-domains = <&pd IMX_SC_R_SPI_3>;
92 dma-names = "tx", "rx";
101 clock-names = "ipg", "baud";
102 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
103 assigned-clock-rates = <80000000>;
104 power-domains = <&pd IMX_SC_R_UART_0>;
105 dma-names = "rx", "tx";
115 clock-names = "ipg", "baud";
116 assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
117 assigned-clock-rates = <80000000>;
118 power-domains = <&pd IMX_SC_R_UART_1>;
119 dma-names = "rx", "tx";
129 clock-names = "ipg", "baud";
130 assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
131 assigned-clock-rates = <80000000>;
132 power-domains = <&pd IMX_SC_R_UART_2>;
133 dma-names = "rx", "tx";
143 clock-names = "ipg", "baud";
144 assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
145 assigned-clock-rates = <80000000>;
146 power-domains = <&pd IMX_SC_R_UART_3>;
147 dma-names = "rx", "tx";
153 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
158 clock-names = "ipg", "per";
159 assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
160 assigned-clock-rates = <24000000>;
161 #pwm-cells = <3>;
162 power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
165 edma2: dma-controller@5a1f0000 {
166 compatible = "fsl,imx8qm-edma";
168 #dma-cells = <3>;
169 dma-channels = <16>;
186 power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
204 spi0_lpcg: clock-controller@5a400000 {
205 compatible = "fsl,imx8qxp-lpcg";
207 #clock-cells = <1>;
210 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
211 clock-output-names = "spi0_lpcg_clk",
213 power-domains = <&pd IMX_SC_R_SPI_0>;
216 spi1_lpcg: clock-controller@5a410000 {
217 compatible = "fsl,imx8qxp-lpcg";
219 #clock-cells = <1>;
222 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
223 clock-output-names = "spi1_lpcg_clk",
225 power-domains = <&pd IMX_SC_R_SPI_1>;
228 spi2_lpcg: clock-controller@5a420000 {
229 compatible = "fsl,imx8qxp-lpcg";
231 #clock-cells = <1>;
234 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
235 clock-output-names = "spi2_lpcg_clk",
237 power-domains = <&pd IMX_SC_R_SPI_2>;
240 spi3_lpcg: clock-controller@5a430000 {
241 compatible = "fsl,imx8qxp-lpcg";
243 #clock-cells = <1>;
246 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
247 clock-output-names = "spi3_lpcg_clk",
249 power-domains = <&pd IMX_SC_R_SPI_3>;
252 uart0_lpcg: clock-controller@5a460000 {
253 compatible = "fsl,imx8qxp-lpcg";
255 #clock-cells = <1>;
258 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
259 clock-output-names = "uart0_lpcg_baud_clk",
261 power-domains = <&pd IMX_SC_R_UART_0>;
264 uart1_lpcg: clock-controller@5a470000 {
265 compatible = "fsl,imx8qxp-lpcg";
267 #clock-cells = <1>;
270 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
271 clock-output-names = "uart1_lpcg_baud_clk",
273 power-domains = <&pd IMX_SC_R_UART_1>;
276 uart2_lpcg: clock-controller@5a480000 {
277 compatible = "fsl,imx8qxp-lpcg";
279 #clock-cells = <1>;
282 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
283 clock-output-names = "uart2_lpcg_baud_clk",
285 power-domains = <&pd IMX_SC_R_UART_2>;
288 uart3_lpcg: clock-controller@5a490000 {
289 compatible = "fsl,imx8qxp-lpcg";
291 #clock-cells = <1>;
294 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
295 clock-output-names = "uart3_lpcg_baud_clk",
297 power-domains = <&pd IMX_SC_R_UART_3>;
300 adma_pwm_lpcg: clock-controller@5a590000 {
301 compatible = "fsl,imx8qxp-lpcg";
303 #clock-cells = <1>;
306 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
307 clock-output-names = "adma_pwm_lpcg_clk",
309 power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
314 #address-cells = <1>;
315 #size-cells = <0>;
319 clock-names = "per", "ipg";
320 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
321 assigned-clock-rates = <24000000>;
322 power-domains = <&pd IMX_SC_R_I2C_0>;
328 #address-cells = <1>;
329 #size-cells = <0>;
333 clock-names = "per", "ipg";
334 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
335 assigned-clock-rates = <24000000>;
336 power-domains = <&pd IMX_SC_R_I2C_1>;
342 #address-cells = <1>;
343 #size-cells = <0>;
347 clock-names = "per", "ipg";
348 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
349 assigned-clock-rates = <24000000>;
350 power-domains = <&pd IMX_SC_R_I2C_2>;
356 #address-cells = <1>;
357 #size-cells = <0>;
361 clock-names = "per", "ipg";
362 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
363 assigned-clock-rates = <24000000>;
364 power-domains = <&pd IMX_SC_R_I2C_3>;
369 compatible = "nxp,imx8qxp-adc";
370 #io-channel-cells = <1>;
373 interrupt-parent = <&gic>;
376 clock-names = "per", "ipg";
377 assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
378 assigned-clock-rates = <24000000>;
379 power-domains = <&pd IMX_SC_R_ADC_0>;
384 compatible = "nxp,imx8qxp-adc";
385 #io-channel-cells = <1>;
388 interrupt-parent = <&gic>;
391 clock-names = "per", "ipg";
392 assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
393 assigned-clock-rates = <24000000>;
394 power-domains = <&pd IMX_SC_R_ADC_1>;
399 compatible = "fsl,imx8qm-flexcan";
402 interrupt-parent = <&gic>;
405 clock-names = "ipg", "per";
406 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
407 assigned-clock-rates = <40000000>;
408 power-domains = <&pd IMX_SC_R_CAN_0>;
410 fsl,clk-source = /bits/ 8 <0>;
411 fsl,scu-index = /bits/ 8 <0>;
416 compatible = "fsl,imx8qm-flexcan";
419 interrupt-parent = <&gic>;
426 clock-names = "ipg", "per";
427 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
428 assigned-clock-rates = <40000000>;
429 power-domains = <&pd IMX_SC_R_CAN_1>;
431 fsl,clk-source = /bits/ 8 <0>;
432 fsl,scu-index = /bits/ 8 <1>;
437 compatible = "fsl,imx8qm-flexcan";
440 interrupt-parent = <&gic>;
447 clock-names = "ipg", "per";
448 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
449 assigned-clock-rates = <40000000>;
450 power-domains = <&pd IMX_SC_R_CAN_2>;
452 fsl,clk-source = /bits/ 8 <0>;
453 fsl,scu-index = /bits/ 8 <2>;
457 edma3: dma-controller@5a9f0000 {
458 compatible = "fsl,imx8qm-edma";
460 #dma-cells = <3>;
461 dma-channels = <8>;
470 power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
480 i2c0_lpcg: clock-controller@5ac00000 {
481 compatible = "fsl,imx8qxp-lpcg";
483 #clock-cells = <1>;
486 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
487 clock-output-names = "i2c0_lpcg_clk",
489 power-domains = <&pd IMX_SC_R_I2C_0>;
492 i2c1_lpcg: clock-controller@5ac10000 {
493 compatible = "fsl,imx8qxp-lpcg";
495 #clock-cells = <1>;
498 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
499 clock-output-names = "i2c1_lpcg_clk",
501 power-domains = <&pd IMX_SC_R_I2C_1>;
504 i2c2_lpcg: clock-controller@5ac20000 {
505 compatible = "fsl,imx8qxp-lpcg";
507 #clock-cells = <1>;
510 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
511 clock-output-names = "i2c2_lpcg_clk",
513 power-domains = <&pd IMX_SC_R_I2C_2>;
516 i2c3_lpcg: clock-controller@5ac30000 {
517 compatible = "fsl,imx8qxp-lpcg";
519 #clock-cells = <1>;
522 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
523 clock-output-names = "i2c3_lpcg_clk",
525 power-domains = <&pd IMX_SC_R_I2C_3>;
528 adc0_lpcg: clock-controller@5ac80000 {
529 compatible = "fsl,imx8qxp-lpcg";
531 #clock-cells = <1>;
534 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
535 clock-output-names = "adc0_lpcg_clk",
537 power-domains = <&pd IMX_SC_R_ADC_0>;
540 adc1_lpcg: clock-controller@5ac90000 {
541 compatible = "fsl,imx8qxp-lpcg";
543 #clock-cells = <1>;
546 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
547 clock-output-names = "adc1_lpcg_clk",
549 power-domains = <&pd IMX_SC_R_ADC_1>;
552 can0_lpcg: clock-controller@5acd0000 {
553 compatible = "fsl,imx8qxp-lpcg";
555 #clock-cells = <1>;
558 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
559 clock-output-names = "can0_lpcg_pe_clk",
562 power-domains = <&pd IMX_SC_R_CAN_0>;