Lines Matching +full:vdd +full:- +full:tx +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
14 #include "fsl-lx2160a-tqmlx2160a.dtsi"
18 compatible = "tq,lx2160a-tqmlx2160a-mblx2160a", "tq,lx2160a-tqmlx2160a",
31 stdout-path = &uart0;
34 gpio-keys {
35 compatible = "gpio-keys";
37 button-user1 {
43 button-user2 {
51 compatible = "gpio-leds";
53 led-user1 {
57 function-enumerator = <0>;
58 linux,default-trigger = "heartbeat";
61 led-user2 {
65 function-enumerator = <1>;
66 linux,default-trigger = "heartbeat";
70 sfp_xfi1: sfp-xfi1 {
72 i2c-bus = <&xfi1_i2c>;
73 mod-def0-gpios = <&gpioex2 2 GPIO_ACTIVE_LOW>;
74 los-gpios = <&gpioex2 3 GPIO_ACTIVE_HIGH>;
75 tx-fault-gpios = <&gpioex2 0 GPIO_ACTIVE_HIGH>;
76 tx-disable-gpios = <&gpioex2 1 GPIO_ACTIVE_HIGH>;
80 sfp_xfi2: sfp-xfi2 {
82 i2c-bus = <&xfi2_i2c>;
83 mod-def0-gpios = <&gpioex2 6 GPIO_ACTIVE_LOW>;
84 los-gpios = <&gpioex2 7 GPIO_ACTIVE_HIGH>;
85 tx-fault-gpios = <&gpioex2 4 GPIO_ACTIVE_HIGH>;
86 tx-disable-gpios = <&gpioex2 5 GPIO_ACTIVE_HIGH>;
100 phy-handle = <&dp83867_2_3>;
101 phy-connection-type = "rgmii-id";
105 phy-handle = <&dp83867_2_4>;
106 phy-connection-type = "rgmii-id";
112 dp83867_1_1: ethernet-phy@1 {
114 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
117 dp83867_1_2: ethernet-phy@2 {
119 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
122 dp83867_1_3: ethernet-phy@3 {
124 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
127 dp83867_1_4: ethernet-phy@4 {
129 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
132 dp83867_1_5: ethernet-phy@5 {
134 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
137 dp83867_1_6: ethernet-phy@6 {
139 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
146 dp83867_2_1: ethernet-phy@1 {
148 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
151 dp83867_2_2: ethernet-phy@2 {
153 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
156 dp83867_2_3: ethernet-phy@3 {
158 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
159 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
160 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
163 dp83867_2_4: ethernet-phy@4 {
165 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
166 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
167 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
172 sd-uhs-sdr104;
173 sd-uhs-sdr50;
174 sd-uhs-sdr25;
175 sd-uhs-sdr12;
176 no-mmc;
177 no-sdio;
178 wp-gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
179 cd-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
187 #gpio-cells = <2>;
188 gpio-controller;
189 vcc-supply = <®_vcc3v3>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201 vdd-supply = <®_vcc3v3>;
205 #address-cells = <1>;
206 #size-cells = <0>;
211 #address-cells = <1>;
212 #size-cells = <0>;
217 #address-cells = <1>;
218 #size-cells = <0>;
223 #gpio-cells = <2>;
224 gpio-controller;
225 vcc-supply = <®_vcc3v3>;
231 #gpio-cells = <2>;
232 gpio-controller;
233 vcc-supply = <®_vcc3v3>;
239 #gpio-cells = <2>;
240 gpio-controller;
241 vcc-supply = <®_vcc3v3>;
247 #address-cells = <1>;
248 #size-cells = <0>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 vdd-supply = <®_vcc3v3>;
265 #address-cells = <1>;
266 #size-cells = <0>;
271 #address-cells = <1>;
272 #size-cells = <0>;
277 #address-cells = <1>;
278 #size-cells = <0>;
283 #address-cells = <1>;
284 #size-cells = <0>;
314 #address-cells = <1>;
315 #size-cells = <0>;
321 peer-hub = <&hub_3_0>;
322 reset-gpios = <&gpioex1 0 GPIO_ACTIVE_LOW>;
323 vdd-supply = <®_vcc3v3>;
329 peer-hub = <&hub_2_0>;
330 reset-gpios = <&gpioex1 0 GPIO_ACTIVE_LOW>;
331 vdd-supply = <®_vcc3v3>;