Lines Matching +full:0 +full:x05100000
22 #size-cells = <0>;
24 cpu0: cpu@0 {
27 reg = <0>;
32 i-cache-size = <0x8000>;
35 d-cache-size = <0x8000>;
49 i-cache-size = <0x8000>;
52 d-cache-size = <0x8000>;
66 i-cache-size = <0x8000>;
69 d-cache-size = <0x8000>;
83 i-cache-size = <0x8000>;
86 d-cache-size = <0x8000>;
96 cache-size = <0x80000>;
109 #clock-cells = <0>;
151 reg = <0x1000000 0x400000>;
155 ranges = <0 0x1000000 0x400000>;
157 display_clocks: clock@0 {
159 reg = <0x0 0x10000>;
170 compatible = "allwinner,sun50i-h6-de3-mixer-0";
171 reg = <0x100000 0x100000>;
177 iommus = <&iommu 0>;
181 #size-cells = <0>;
196 reg = <0x01c00000 0x1000>;
206 reg = <0x01c0e000 0x2000>;
219 reg = <0x01800000 0x4000>;
233 reg = <0x01904000 0x1000>;
243 reg = <0x03000000 0x1000>;
250 reg = <0x00028000 0x1e000>;
253 ranges = <0 0x00028000 0x1e000>;
255 de2_sram: sram-section@0 {
258 reg = <0x0000 0x1e000>;
264 reg = <0x01a00000 0x200000>;
267 ranges = <0 0x01a00000 0x200000>;
269 ve_sram: sram-section@0 {
272 reg = <0x000000 0x200000>;
279 reg = <0x03001000 0x1000>;
288 reg = <0x03002000 0x1000>;
301 reg = <0x03003000 0x1000>;
310 reg = <0x03006000 0x400>;
315 reg = <0x14 0x8>;
319 reg = <0x1c 0x4>;
326 reg = <0x03009000 0xa0>;
335 reg = <0x030090a0 0x20>;
344 reg = <0x0300a000 0x400>;
354 reg = <0x0300b000 0x400>;
470 reg = <0x03021000 0x1000>,
471 <0x03022000 0x2000>,
472 <0x03024000 0x2000>,
473 <0x03026000 0x2000>;
481 reg = <0x030f0000 0x10000>;
491 reg = <0x04020000 0x1000>;
498 pinctrl-0 = <&mmc0_pins>;
502 #size-cells = <0>;
508 reg = <0x04021000 0x1000>;
515 pinctrl-0 = <&mmc1_pins>;
519 #size-cells = <0>;
525 reg = <0x04022000 0x1000>;
532 pinctrl-0 = <&mmc2_pins>;
536 #size-cells = <0>;
541 reg = <0x05000000 0x400>;
542 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
552 reg = <0x05000400 0x400>;
563 reg = <0x05000800 0x400>;
574 reg = <0x05000c00 0x400>;
586 reg = <0x05002000 0x400>;
591 pinctrl-0 = <&i2c0_pins>;
594 #size-cells = <0>;
600 reg = <0x05002400 0x400>;
605 pinctrl-0 = <&i2c1_pins>;
608 #size-cells = <0>;
614 reg = <0x05002800 0x400>;
619 pinctrl-0 = <&i2c2_pins>;
622 #size-cells = <0>;
628 reg = <0x05010000 0x1000>;
637 #size-cells = <0>;
643 reg = <0x05011000 0x1000>;
652 #size-cells = <0>;
659 reg = <0x05020000 0x10000>;
671 #size-cells = <0>;
676 #sound-dai-cells = <0>;
678 reg = <0x05091000 0x1000>;
689 #sound-dai-cells = <0>;
691 reg = <0x05093000 0x400>;
704 reg = <0x05100000 0x0400>;
709 phys = <&usb2phy 0>;
711 extcon = <&usb2phy 0>;
717 reg = <0x05100400 0x24>,
718 <0x05101800 0x4>,
719 <0x05311800 0x4>;
737 reg = <0x05101000 0x100>;
744 phys = <&usb2phy 0>;
751 reg = <0x05101400 0x100>;
756 phys = <&usb2phy 0>;
763 reg = <0x05200000 0x10000>;
786 reg = <0x5210000 0x10000>;
789 #phy-cells = <0>;
795 reg = <0x05311000 0x100>;
809 reg = <0x05311400 0x100>;
821 reg = <0x06000000 0x10000>;
834 pinctrl-0 = <&hdmi_pins>;
839 #size-cells = <0>;
841 hdmi_in: port@0 {
842 reg = <0>;
857 reg = <0x06010000 0x10000>;
862 #phy-cells = <0>;
867 reg = <0x06510000 0x1000>;
878 #size-cells = <0>;
880 tcon_top_mixer0_in: port@0 {
882 #size-cells = <0>;
883 reg = <0>;
885 tcon_top_mixer0_in_mixer0: endpoint@0 {
886 reg = <0>;
893 #size-cells = <0>;
904 #size-cells = <0>;
907 tcon_top_hdmi_in_tcon_tv: endpoint@0 {
908 reg = <0>;
926 reg = <0x06515000 0x1000>;
937 #size-cells = <0>;
939 tcon_tv_in: port@0 {
940 reg = <0>;
949 #size-cells = <0>;
962 reg = <0x07000000 0x400>;
972 reg = <0x07010000 0x400>;
983 reg = <0x07020400 0x20>;
992 reg = <0x07021000 0x400>;
998 reg = <0x07022000 0x400>;
1029 reg = <0x07040000 0x400>;
1036 pinctrl-0 = <&r_ir_rx_pin>;
1043 reg = <0x07081400 0x400>;
1048 pinctrl-0 = <&r_i2c_pins>;
1051 #size-cells = <0>;
1056 reg = <0x07083000 0x400>;
1062 pinctrl-0 = <&r_rsb_pins>;
1065 #size-cells = <0>;
1070 reg = <0x05070400 0x100>;
1083 polling-delay-passive = <0>;
1084 polling-delay = <0>;
1085 thermal-sensors = <&ths 0>;
1096 hysteresis = <0>;
1118 gpu_alert0: gpu-alert-0 {
1138 hysteresis = <0>;