Lines Matching +full:system +full:- +full:cache +full:- +full:controller
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/en7523-clk.h>
6 #include <dt-bindings/reset/airoha,en7581-reset.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
13 reserved-memory {
14 #address-cells = <2>;
15 #size-cells = <2>;
18 npu-binary@84000000 {
19 no-map;
23 npu-flag@84b0000 {
24 no-map;
28 npu-pkt@85000000 {
29 no-map;
33 npu-phyaddr@86b00000 {
34 no-map;
38 npu-rxdesc@86d00000 {
39 no-map;
45 compatible = "arm,psci-1.0";
50 #address-cells = <1>;
51 #size-cells = <0>;
53 cpu-map {
75 compatible = "arm,cortex-a53";
77 enable-method = "psci";
78 clock-frequency = <80000000>;
79 next-level-cache = <&l2>;
84 compatible = "arm,cortex-a53";
86 enable-method = "psci";
87 clock-frequency = <80000000>;
88 next-level-cache = <&l2>;
93 compatible = "arm,cortex-a53";
95 enable-method = "psci";
96 clock-frequency = <80000000>;
97 next-level-cache = <&l2>;
102 compatible = "arm,cortex-a53";
104 enable-method = "psci";
105 clock-frequency = <80000000>;
106 next-level-cache = <&l2>;
109 l2: l2-cache {
110 compatible = "cache";
111 cache-size = <0x80000>;
112 cache-line-size = <64>;
113 cache-level = <2>;
114 cache-unified;
119 compatible = "arm,armv8-timer";
120 interrupt-parent = <&gic>;
127 clk20m: clock-20000000 {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <20000000>;
134 compatible = "simple-bus";
135 #address-cells = <2>;
136 #size-cells = <2>;
139 gic: interrupt-controller@9000000 {
140 compatible = "arm,gic-v3";
141 interrupt-controller;
142 #interrupt-cells = <3>;
143 #address-cells = <1>;
144 #size-cells = <1>;
154 compatible = "airoha,en7581-snand";
159 clock-names = "spi";
161 #address-cells = <1>;
162 #size-cells = <0>;
167 compatible = "spi-nand";
170 spi-max-frequency = <50000000>;
171 spi-tx-bus-width = <1>;
172 spi-rx-bus-width = <2>;
176 scuclk: clock-controller@1fb00000 {
177 compatible = "airoha,en7581-scu";
179 #clock-cells = <1>;
180 #reset-cells = <1>;
184 compatible = "airoha,en7581-pbus-csr", "syscon";
189 compatible = "airoha,en7581-pcie-phy";
196 reg-names = "csr-2l", "pma0", "pma1",
197 "p0-xr-dtime", "p1-xr-dtime",
198 "rx-aeq";
199 #phy-cells = <0>;
203 compatible = "airoha,en7581-pcie";
205 linux,pci-domain = <0>;
206 #address-cells = <3>;
207 #size-cells = <2>;
210 reg-names = "pcie-mac";
213 clock-names = "sys-ck";
216 phy-names = "pcie-phy";
223 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
225 mediatek,pbus-csr = <&pbus_csr 0x0 0x4>;
228 bus-range = <0x00 0xff>;
229 #interrupt-cells = <1>;
230 interrupt-map-mask = <0 0 0 7>;
231 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
238 pcie_intc0: interrupt-controller {
239 interrupt-controller;
240 #address-cells = <0>;
241 #interrupt-cells = <1>;
246 compatible = "airoha,en7581-pcie";
248 linux,pci-domain = <1>;
249 #address-cells = <3>;
250 #size-cells = <2>;
253 reg-names = "pcie-mac";
256 clock-names = "sys-ck";
259 phy-names = "pcie-phy";
266 reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
268 mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
271 bus-range = <0x00 0xff>;
272 #interrupt-cells = <1>;
273 interrupt-map-mask = <0 0 0 7>;
274 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
281 pcie_intc1: interrupt-controller {
282 interrupt-controller;
283 #address-cells = <0>;
284 #interrupt-cells = <1>;
291 reg-io-width = <4>;
292 reg-shift = <2>;
294 clock-frequency = <1843200>;
298 compatible = "airoha,en7581-trng";
303 system-controller@1fbf0200 {
304 compatible = "airoha,en7581-gpio-sysctl", "syscon",
305 "simple-mfd";
309 compatible = "airoha,en7581-pinctrl";
311 interrupt-parent = <&gic>;
314 gpio-controller;
315 #gpio-cells = <2>;
317 interrupt-controller;
318 #interrupt-cells = <2>;
323 compatible = "mediatek,mt7621-i2c";
329 clock-frequency = <100000>;
330 #address-cells = <1>;
331 #size-cells = <0>;
337 compatible = "mediatek,mt7621-i2c";
343 clock-frequency = <100000>;
344 #address-cells = <1>;
345 #size-cells = <0>;
351 compatible = "airoha,en7581-eth";
355 reg-names = "fe", "qdma0", "qdma1";
365 reset-names = "fe", "pdma", "qdma",
366 "xsi-mac", "hsi0-mac", "hsi1-mac",
367 "hsi-mac", "xfp-mac";
382 #address-cells = <1>;
383 #size-cells = <0>;
386 compatible = "airoha,eth-mac";
388 phy-mode = "internal";
391 fixed-link {
393 full-duplex;