// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		npu-binary@84000000 {
			no-map;
			reg = <0x0 0x84000000 0x0 0xa00000>;
		};

		npu-flag@84b0000 {
			no-map;
			reg = <0x0 0x84b00000 0x0 0x100000>;
		};

		npu-pkt@85000000 {
			no-map;
			reg = <0x0 0x85000000 0x0 0x1a00000>;
		};

		npu-phyaddr@86b00000 {
			no-map;
			reg = <0x0 0x86b00000 0x0 0x100000>;
		};

		npu-rxdesc@86d00000 {
			no-map;
			reg = <0x0 0x86d00000 0x0 0x100000>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			clock-frequency = <80000000>;
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			clock-frequency = <80000000>;
			next-level-cache = <&l2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			enable-method = "psci";
			clock-frequency = <80000000>;
			next-level-cache = <&l2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			enable-method = "psci";
			clock-frequency = <80000000>;
			next-level-cache = <&l2>;
		};

		l2: l2-cache {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-level = <2>;
			cache-unified;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@9000000 {
			compatible = "arm,gic-v3";
			interrupt-controller;
			#interrupt-cells = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x0 0x09000000 0x0 0x20000>,
			      <0x0 0x09080000 0x0 0x80000>,
			      <0x0 0x09400000 0x0 0x2000>,
			      <0x0 0x09500000 0x0 0x2000>,
			      <0x0 0x09600000 0x0 0x20000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
		};

		uart1: serial@1fbf0000 {
			compatible = "ns16550";
			reg = <0x0 0x1fbf0000 0x0 0x30>;
			reg-io-width = <4>;
			reg-shift = <2>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <1843200>;
		};
	};
};