Lines Matching +full:cpu +full:- +full:map
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 interrupt-parent = <&gic>;
8 #address-cells = <2>;
9 #size-cells = <2>;
11 reserved-memory {
12 #address-cells = <2>;
13 #size-cells = <2>;
16 npu-binary@84000000 {
17 no-map;
21 npu-flag@84b0000 {
22 no-map;
26 npu-pkt@85000000 {
27 no-map;
31 npu-phyaddr@86b00000 {
32 no-map;
36 npu-rxdesc@86d00000 {
37 no-map;
43 compatible = "arm,psci-1.0";
48 #address-cells = <1>;
49 #size-cells = <0>;
51 cpu-map {
54 cpu = <&cpu0>;
58 cpu = <&cpu1>;
62 cpu = <&cpu2>;
66 cpu = <&cpu3>;
71 cpu0: cpu@0 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a53";
75 enable-method = "psci";
76 clock-frequency = <80000000>;
77 next-level-cache = <&l2>;
80 cpu1: cpu@1 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a53";
84 enable-method = "psci";
85 clock-frequency = <80000000>;
86 next-level-cache = <&l2>;
89 cpu2: cpu@2 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a53";
93 enable-method = "psci";
94 clock-frequency = <80000000>;
95 next-level-cache = <&l2>;
98 cpu3: cpu@3 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a53";
102 enable-method = "psci";
103 clock-frequency = <80000000>;
104 next-level-cache = <&l2>;
107 l2: l2-cache {
109 cache-size = <0x80000>;
110 cache-line-size = <64>;
111 cache-level = <2>;
112 cache-unified;
117 compatible = "arm,armv8-timer";
118 interrupt-parent = <&gic>;
126 compatible = "simple-bus";
127 #address-cells = <2>;
128 #size-cells = <2>;
131 gic: interrupt-controller@9000000 {
132 compatible = "arm,gic-v3";
133 interrupt-controller;
134 #interrupt-cells = <3>;
135 #address-cells = <1>;
136 #size-cells = <1>;
148 reg-io-width = <4>;
149 reg-shift = <2>;
151 clock-frequency = <1843200>;