Lines Matching refs:affected
428 The affected design reports FEAT_HAFDBS as not implemented in
478 the kernel if an affected CPU is detected.
500 the kernel if an affected CPU is detected.
523 only patch the kernel if an affected CPU is detected.
545 the kernel if an affected CPU is detected.
563 the kernel if an affected CPU is detected.
583 the kernel if an affected CPU is detected.
611 When running a compat (AArch32) userspace on an affected Cortex-A53
620 the kernel if an affected CPU is detected.
644 of hardware DBM locally on the affected cores. CPUs not affected by
709 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
714 Under very rare circumstances, affected Cortex-A55 CPUs
719 Work around this by adding the affected CPUs to the list that needs
730 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
747 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
804 is to not enable the feature on affected CPUs.
888 Workaround is to issue two TSB consecutively on affected cores.
903 Workaround is to issue two TSB consecutively on affected cores.
947 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
952 Under very rare circumstances, affected Cortex-A510 CPUs
957 Work around this by adding the affected CPUs to the list that needs
975 is stopped and before performing a system register write to one of the affected
1015 affected cpus. The firmware must have disabled the access to TRBE for the kernel
1029 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1032 Work around this problem by returning 0 when reading the affected counter in
1034 is the same to firmware disabling affected counters.
1064 On an affected Cortex-A520 core, a speculatively executed unprivileged
1078 On an affected Cortex-A510 core, a speculatively executed unprivileged
1114 On affected cores "MSR SSBS, #0" instructions may not affect
1153 the affected CPUs.