Lines Matching full:workaround
462 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
502 The workaround promotes data cache clean instructions to
504 Please note that this does not necessarily enable the workaround,
524 The workaround promotes data cache clean instructions to
526 Please note that this does not necessarily enable the workaround,
547 The workaround promotes data cache clean instructions to
550 workaround, as it depends on the alternative framework, which will
569 The workaround promotes data cache clean instructions to
571 Please note that this does not necessarily enable the workaround,
587 The workaround is to promote device loads to use Load-Acquire
589 Please note that this does not necessarily enable the workaround,
607 The workaround is to verify that the Stage 1 translation
609 Please note that this does not necessarily enable the workaround,
621 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
644 The workaround is to write the contextidr_el1 register on exception
646 Please note that this does not necessarily enable the workaround,
667 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
671 without a break-before-make. The workaround is to disable the usage
682 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
699 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
725 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
740 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
756 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
765 workaround repeats the TLBI+DSB operation.
773 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
788 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
790 This option adds a workaround for ARM Neoverse-N1 erratum
794 modified by another CPU. The workaround depends on a firmware
797 Workaround the issue by hiding the DIC feature from EL0. This
803 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
806 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
810 non-cacheable memory attributes. The workaround depends on a firmware
813 KVM guests must also have the workaround implemented or they can
829 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
831 hardware update of the page table's dirty bit. The workaround
837 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
840 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
857 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
867 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
872 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
885 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
890 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
906 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
910 Enable workaround for ARM Cortex-A710 erratum 2054223
916 Workaround is to issue two TSB consecutively on affected cores.
921 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
925 Enable workaround for ARM Neoverse-N2 erratum 2067961
931 Workaround is to issue two TSB consecutively on affected cores.
939 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
944 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
957 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
962 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
978 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
991 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
995 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
1009 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
1013 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
1032 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1036 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1050 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1054 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1067 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1070 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1077 mprotect() system call. Workaround the problem by doing a break-before-make
1086 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1090 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1100 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1104 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1114 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1117 This option adds the workaround for the following errata:
1157 Enable workaround for errata 22375 and 24313.
1236 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1246 The workaround is to ensure these bits are clear in TCR_ELx.
1247 The workaround only affects the Fujitsu-A64FX.
1344 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"