Lines Matching full:workaround
434 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
474 The workaround promotes data cache clean instructions to
476 Please note that this does not necessarily enable the workaround,
496 The workaround promotes data cache clean instructions to
498 Please note that this does not necessarily enable the workaround,
519 The workaround promotes data cache clean instructions to
522 workaround, as it depends on the alternative framework, which will
541 The workaround promotes data cache clean instructions to
543 Please note that this does not necessarily enable the workaround,
559 The workaround is to promote device loads to use Load-Acquire
561 Please note that this does not necessarily enable the workaround,
579 The workaround is to verify that the Stage 1 translation
581 Please note that this does not necessarily enable the workaround,
593 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
616 The workaround is to write the contextidr_el1 register on exception
618 Please note that this does not necessarily enable the workaround,
639 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
643 without a break-before-make. The workaround is to disable the usage
654 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
671 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
697 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
712 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
728 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
737 workaround repeats the TLBI+DSB operation.
745 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
760 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
762 This option adds a workaround for ARM Neoverse-N1 erratum
766 modified by another CPU. The workaround depends on a firmware
769 Workaround the issue by hiding the DIC feature from EL0. This
775 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
778 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
782 non-cacheable memory attributes. The workaround depends on a firmware
785 KVM guests must also have the workaround implemented or they can
801 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
803 hardware update of the page table's dirty bit. The workaround
809 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
812 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
829 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
839 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
844 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
857 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
862 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
878 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
882 Enable workaround for ARM Cortex-A710 erratum 2054223
888 Workaround is to issue two TSB consecutively on affected cores.
893 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
897 Enable workaround for ARM Neoverse-N2 erratum 2067961
903 Workaround is to issue two TSB consecutively on affected cores.
911 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
916 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
929 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
934 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
950 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
963 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
967 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
981 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
985 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
1004 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1008 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1022 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1026 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1039 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1042 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1049 mprotect() system call. Workaround the problem by doing a break-before-make
1058 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1062 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1072 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1076 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1086 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1089 This option adds the workaround for the following errata:
1127 bool "SI L1: 4311569: workaround for premature CMO completion erratum"
1130 This option adds the workaround for ARM SI L1 erratum 4311569.
1138 Enabling this option implements a software workaround by inserting a
1150 Enable workaround for C1-Pro acknowledging the DVMSync before
1161 Enable workaround for errata 22375 and 24313.
1240 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1250 The workaround is to ensure these bits are clear in TCR_ELx.
1251 The workaround only affects the Fujitsu-A64FX.
1348 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"