Lines Matching full:workaround
457 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
480 The workaround promotes data cache clean instructions to
482 Please note that this does not necessarily enable the workaround,
502 The workaround promotes data cache clean instructions to
504 Please note that this does not necessarily enable the workaround,
525 The workaround promotes data cache clean instructions to
528 workaround, as it depends on the alternative framework, which will
547 The workaround promotes data cache clean instructions to
549 Please note that this does not necessarily enable the workaround,
565 The workaround is to promote device loads to use Load-Acquire
567 Please note that this does not necessarily enable the workaround,
585 The workaround is to verify that the Stage 1 translation
587 Please note that this does not necessarily enable the workaround,
599 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
622 The workaround is to write the contextidr_el1 register on exception
624 Please note that this does not necessarily enable the workaround,
648 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
652 without a break-before-make. The workaround is to disable the usage
663 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
680 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
706 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
721 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
737 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
746 workaround repeats the TLBI+DSB operation.
754 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
769 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
771 This option adds a workaround for ARM Neoverse-N1 erratum
775 modified by another CPU. The workaround depends on a firmware
778 Workaround the issue by hiding the DIC feature from EL0. This
784 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
787 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
791 non-cacheable memory attributes. The workaround depends on a firmware
794 KVM guests must also have the workaround implemented or they can
810 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
812 hardware update of the page table's dirty bit. The workaround
818 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
821 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
838 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
848 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
853 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
866 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
871 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
887 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
891 Enable workaround for ARM Cortex-A710 erratum 2054223
897 Workaround is to issue two TSB consecutively on affected cores.
902 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
906 Enable workaround for ARM Neoverse-N2 erratum 2067961
912 Workaround is to issue two TSB consecutively on affected cores.
920 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
925 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
938 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
943 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
959 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
972 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
976 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
990 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
994 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
1013 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1017 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1031 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1035 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1048 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1051 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1058 mprotect() system call. Workaround the problem by doing a break-before-make
1067 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1071 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1081 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1085 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1095 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1098 This option adds the workaround for the following errata:
1138 Enable workaround for errata 22375 and 24313.
1217 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1227 The workaround is to ensure these bits are clear in TCR_ELx.
1228 The workaround only affects the Fujitsu-A64FX.
1316 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"