Lines Matching +full:in +full:- +full:and +full:- +full:around
1 # SPDX-License-Identifier: GPL-2.0-only
288 ARM 64-bit (AArch64) Linux support.
296 # required due to use of the -Zfixed-x18 flag.
299 # -Zsanitizer=shadow-call-stack flag.
309 depends on $(cc-option,-fpatchable-function-entry=2)
335 # VA_BITS - PTDESC_TABLE_SHIFT
413 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
418 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
421 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
454 …bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and …
457 This option adds an alternative code sequence to work around Ampere
458 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne.
460 The affected design reports FEAT_HAFDBS as not implemented in
468 at stage-2.
476 This option adds an alternative code sequence to work around Ampere
484 for corruption, and an ISB after is sufficient to prevent younger
493 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
497 This option adds an alternative code sequence to work around ARM
498 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
499 AXI master interface and an L2 cache.
501 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
502 and is unable to accept a certain write via this interface, it will
503 not progress on read data presented on the read data channel and the
507 data cache clean-and-invalidate.
515 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
519 This option adds an alternative code sequence to work around ARM
520 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
521 master interface and an L2 cache.
529 data cache clean-and-invalidate.
537 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
541 This option adds an alternative code sequence to work around ARM
542 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
545 If a Cortex-A53 processor is executing a store or prefetch for
546 write instruction at the same time as a processor in another
552 data cache clean-and-invalidate.
560 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
564 This option adds an alternative code sequence to work around ARM
565 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
568 If the processor is executing a load and store exclusive sequence at
569 the same time as a processor in another cluster is executing a cache
574 data cache clean-and-invalidate.
582 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
585 This option adds an alternative code sequence to work around ARM
586 erratum 832075 on Cortex-A57 parts up to r1p2.
588 Affected Cortex-A57 parts might deadlock when exclusive load/store
589 instructions to Write-Back memory are mixed with Device loads.
591 The workaround is to promote device loads to use Load-Acquire
600 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
603 This option adds an alternative code sequence to work around ARM
604 erratum 834220 on Cortex-A57 parts up to r1p2.
606 Affected Cortex-A57 parts might report a Stage 2 translation
609 alignment fault at Stage 1 and a translation fault at Stage 2.
620 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
624 This option removes the AES hwcap for aarch32 user-space to
625 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
636 bool "Cortex-A53: 845719: a load might read incorrect data"
640 This option adds an alternative code sequence to work around ARM
641 erratum 845719 on Cortex-A53 parts up to r0p4.
643 When running a compat (AArch32) userspace on an affected Cortex-A53
649 return to a 32-bit task.
657 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
660 This option links the kernel with '--fix-cortex-a53-843419' and
663 Cortex-A53 parts up to r0p4.
668 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
671 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
673 Affected Cortex-A55 cores (all revisions) could cause incorrect
675 without a break-before-make. The workaround is to disable the usage
682 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
686 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
687 errata 1188873 and 1418040.
689 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
699 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
703 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
705 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
712 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
716 This option adds work arounds for ARM Cortex-A57 erratum 1319537
717 and A72 erratum 1319367
719 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
725 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
729 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
731 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
741 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
744 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
746 Under very rare circumstances, affected Cortex-A55 CPUs
747 may not handle a race between a break-before-make sequence on one
748 CPU, and another CPU accessing the same page. This could allow a
751 Work around this by adding the affected CPUs to the list that needs
757 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
760 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
762 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
766 break-before-make sequence, then under very rare circumstances
774 bool "Cortex-A76: Software Step might prevent interrupt recognition"
777 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
779 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
781 subsequent interrupts when software stepping is disabled in the
782 exception handler of the system call and either kernel debugging
783 is enabled or VHE is in use.
785 Work around the erratum by triggering a dummy step exception
787 in a VHE configuration of the kernel.
792 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
794 This option adds a workaround for ARM Neoverse-N1 erratum
797 Affected Neoverse-N1 cores could execute a stale instruction when
802 forces user-space to perform cache maintenance.
807 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
810 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
812 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
813 of a store-exclusive or read of PAR_EL1 and a load with device or
814 non-cacheable memory attributes. The workaround depends on a firmware
820 Work around the issue by inserting DMB SY barriers around PAR_EL1
821 register reads and warning KVM users. The DMB barrier is sufficient
830 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
833 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
834 Affected Cortex-A510 might not respect the ordering rules for
841 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
844 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
845 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
853 previous guest entry, and can be restored from the in-memory copy.
858 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
861 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
862 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
863 BFMMLA or VMMLA instructions in rare circumstances when a pair of
866 user-space should not be using these instructions.
871 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
876 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
878 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
879 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
882 Work around the issue by always making sure we move the TRBPTR_EL1 by
883 256 bytes before enabling the buffer and filling the first 256 bytes of
889 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
894 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
896 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
897 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
900 Work around the issue by always making sure we move the TRBPTR_EL1 by
901 256 bytes before enabling the buffer and filling the first 256 bytes of
910 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
914 Enable workaround for ARM Cortex-A710 erratum 2054223
917 the PE is in trace prohibited state. This will cause losing a few bytes
925 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
929 Enable workaround for ARM Neoverse-N2 erratum 2067961
932 the PE is in trace prohibited state. This will cause losing a few bytes
943 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
948 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
950 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
953 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
955 Work around this in the driver by always making sure that there is a
961 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
966 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
968 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
971 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
973 Work around this in the driver by always making sure that there is a
979 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
982 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
984 Under very rare circumstances, affected Cortex-A510 CPUs
985 may not handle a race between a break-before-make sequence on one
986 CPU, and another CPU accessing the same page. This could allow a
989 Work around this by adding the affected CPUs to the list that needs
995 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
999 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
1001 Affected Cortex-A510 core might fail to write into system registers after the
1004 and TRBTRG_EL1 will be ignored and will not be effected.
1006 Work around this in the driver by executing TSB CSYNC and DSB after collection
1007 is stopped and before performing a system register write to one of the affected
1013 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
1017 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
1019 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1023 execution changes from a context, in which trace is prohibited to one where it
1024 isn't, or vice versa. In these mentioned conditions, the view of whether trace
1025 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
1028 Work around this in the driver by preventing an inconsistent view of whether the
1036 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1040 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1042 Affected Cortex-A510 core might cause trace data corruption, when being written
1043 into the memory. Effectively TRBE is broken and hence cannot be used to capture
1046 Work around this problem in the driver by just preventing TRBE initialization on
1054 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1058 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1061 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1064 Work around this problem by returning 0 when reading the affected counter in
1065 key locations that results in disabling all users of this counter. This effect
1071 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1074 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1076 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1077 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1080 Only user-space does executable to non-executable permission transition via
1081 mprotect() system call. Workaround the problem by doing a break-before-make
1090 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1094 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1096 On an affected Cortex-A520 core, a speculatively executed unprivileged
1099 Work around this problem by executing a TLBI before returning to EL0.
1104 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1108 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1110 On an affected Cortex-A510 core, a speculatively executed unprivileged
1113 Work around this problem by executing a TLBI before returning to EL0.
1118 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1123 * ARM Cortex-A76 erratum 3324349
1124 * ARM Cortex-A77 erratum 3324348
1125 * ARM Cortex-A78 erratum 3324344
1126 * ARM Cortex-A78C erratum 3324346
1127 * ARM Cortex-A78C erratum 3324347
1128 * ARM Cortex-A710 erratam 3324338
1129 * ARM Cortex-A715 errartum 3456084
1130 * ARM Cortex-A720 erratum 3456091
1131 * ARM Cortex-A725 erratum 3456106
1132 * ARM Cortex-X1 erratum 3324344
1133 * ARM Cortex-X1C erratum 3324346
1134 * ARM Cortex-X2 erratum 3324338
1135 * ARM Cortex-X3 erratum 3324335
1136 * ARM Cortex-X4 erratum 3194386
1137 * ARM Cortex-X925 erratum 3324334
1138 * ARM Neoverse-N1 erratum 3324349
1140 * ARM Neoverse-N3 erratum 3456111
1141 * ARM Neoverse-V1 erratum 3324341
1143 * ARM Neoverse-V3 erratum 3312417
1144 * ARM Neoverse-V3AE erratum 3312417
1150 Work around this problem by placing a Speculation Barrier (SB) or
1152 SSBS. The presence of the SSBS special-purpose register is hidden
1153 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
1162 Enable workaround for errata 22375 and 24313.
1164 This implements two gicv3-its errata workarounds for ThunderX. Both
1170 The fixes are in ITS initialization and basically ignore memory access
1171 type and table size provided by the TYPER and BASER registers.
1180 ITS SYNC command hang for cross node io and collections/cpu mapping.
1185 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1190 (access to icc_iar1_el1 is not sync'ed before and after).
1193 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1204 contains data for a non-current ASID. The fix is to
1210 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1214 1.2, and T83 Pass 1.0, KVM guest execution may disable
1215 interrupts in host. Trapping both GICv3 group-0 and group-1
1221 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1225 TTBR update and the corresponding context synchronizing operation can
1226 cause a spurious Data Abort to be delivered to any hardware thread in
1229 Work around the issue by avoiding the problematic code sequence and
1232 instruction and ensures context synchronization by virtue of the
1238 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1241 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1242 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1246 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1247 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1248 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1249 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1251 The workaround is to ensure these bits are clear in TCR_ELx.
1252 The workaround only affects the Fujitsu-A64FX.
1261 when issued ITS commands such as VMOVP and VMAPP, and requires
1262 a 128kB offset to be applied to the target address in this commands.
1270 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches
1281 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1282 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1283 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1284 then only for entries in the walk cache, since the leaf translation
1285 is unchanged. Work around the erratum by invalidating the walk cache
1323 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1333 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI
1342 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1349 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1353 MSI doorbell writes with non-zero values for the device ID.
1384 allowing only two levels of page tables and faster TLB
1385 look-up. AArch32 emulation requires applications compiled
1396 a combination of page size and virtual address space size.
1399 bool "36-bit" if EXPERT
1403 bool "39-bit"
1407 bool "42-bit"
1411 bool "47-bit"
1415 bool "48-bit"
1418 bool "52-bit"
1420 Enable 52-bit virtual addressing for userspace when explicitly
1421 requested via a hint to mmap(). The kernel will also use 52-bit
1423 this feature is available, otherwise it reverts to 48-bit).
1425 NOTE: Enabling 52-bit virtual addressing in conjunction with
1426 ARMv8.3 Pointer Authentication will result in the PAC being
1428 impact on its susceptibility to brute-force attacks.
1430 If unsure, select 48-bit virtual addressing instead.
1435 bool "Force 52-bit virtual addresses for userspace"
1438 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1439 to maintain compatibility with older software by providing 48-bit VAs
1442 This configuration option disables the 48-bit compatibility logic, and
1443 forces all userspace addresses to be 52-bit on HW that supports it. One
1464 bool "48-bit"
1468 bool "52-bit"
1471 Enable support for a 52-bit physical address space, introduced as
1472 part of the ARMv8.2-LPA extension.
1475 do not support ARMv8.2-LPA, but with some added memory overhead (and
1494 applications will need to be compiled and linked for the endianness
1498 bool "Build big-endian kernel"
1501 Say Y if you plan on running a kernel with a big-endian userspace.
1504 bool "Build little-endian kernel"
1506 Say Y if you plan on running a kernel with a little-endian userspace.
1512 int "Maximum number of CPUs (2-4096)"
1517 bool "Support for hot-pluggable CPUs"
1520 Say Y here to experiment with turning CPUs off and on. CPUs
1525 bool "NUMA Memory Allocation and Scheduler Support"
1533 Enable NUMA (Non-Uniform Memory Access) support.
1536 local memory of the CPU and add some more
1560 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1574 accounting. Time spent executing other tasks in parallel with
1578 If in doubt, say N here.
1626 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1632 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1635 # ----+-------------------+--------------+----------------------+-------------------------+
1646 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1660 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT
1663 Speculation attacks against some high-performance processors can
1664 be used to bypass MMU permission checks and leak kernel data to
1666 when running in userspace, mapping it back in on exception entry
1667 via a trampoline page in the vector table.
1675 Speculation attacks against some high-performance processors can
1677 When taking an exception from user-space, a sequence of branches
1686 user-space memory directly by pointing TTBR0_EL1 to a reserved
1687 zeroed area and reserved ASID. The user access routines
1694 When this option is enabled, user applications can opt in to a
1697 Documentation/arch/arm64/tagged-address-abi.rst.
1700 bool "Kernel support for 32-bit EL0"
1706 This option enables support for a 32-bit EL0 running under a 64-bit
1707 kernel at EL1. AArch32-specific components such as system calls,
1708 the user helper functions, VFP support and the ptrace interface are
1715 If you want to execute 32-bit userspace applications, say Y.
1720 bool "Enable kuser helpers page for 32-bit applications"
1723 Warning: disabling this option may break 32-bit user programs.
1726 helper code to userspace in read only form at a fixed location
1737 If all of the binaries and libraries which run on your platform
1738 are built specifically for your platform, and make no use of
1740 such exploits. However, in that case, if a binary or library
1747 bool "Enable vDSO for 32-bit applications"
1752 Place in the process address space of 32-bit applications an
1754 and clock_gettime.
1756 You must have a 32-bit build of glibc 2.22 or later for programs
1760 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1764 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1765 otherwise with '-marm'.
1768 bool "Fix up misaligned multi-word loads and stores in user space"
1775 that have been deprecated or obsoleted in the architecture.
1793 In some older versions of glibc [<=2.8] SWP is used during futex
1810 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1811 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1812 strongly recommended to use the ISB, DSB, and DMB
1826 The SETEND instruction alters the data-endianness of the
1827 AArch32 EL0, and is deprecated in ARMv8.
1834 for this feature to be enabled. If a new CPU - which doesn't support mixed
1835 endian - is hotplugged in after this feature has been enabled, there could
1836 be unexpected results in the applications.
1846 bool "Support for hardware updates of the Access and Dirty page flags"
1850 hardware updates of the access and dirty information in page
1851 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1854 Similarly, writes to read-only pages with the DBM bit set will
1855 clear the read-only bit (AP[2]) instead of raising a
1859 to work on pre-ARMv8.1 hardware and the performance impact is
1867 prevents the kernel or hypervisor from accessing user-space (EL0)
1873 The feature is detected at runtime, and will remain as a 'nop'
1885 atomic instructions that are designed specifically to scale in
1888 Say Y here to make use of these instructions for the in-kernel
1904 The feature is detected at runtime, and the kernel will use DC CVAC
1912 CPUs that support the Reliability, Availability and Serviceability
1913 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1914 errors, classify them and report them to software.
1917 barriers to determine if faults are pending and read the
1921 and access the new registers if the system supports the extension.
1929 be shared between different PEs in the same inner shareable
1931 caching of such entries in the TLB.
1934 at runtime, and does not affect PEs that do not implement
1946 instructions for signing and authenticating pointers against secret
1948 and other attacks.
1953 context-switched along with the process.
1955 The feature is detected at runtime. If the feature is not present in
1961 address auth and the late CPU has then the late CPU will still boot
1975 If the compiler supports the -mbranch-protection or
1976 -msign-return-address flag (e.g. GCC 7 or later), then this option
1978 protection. In this case, and if the target hardware is known to
1987 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1991 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
2009 extension. The required support is present in:
2010 * Version 1.5 and later of the ARM Trusted Firmware
2024 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2032 Memory System Resource Partitioning and Monitoring (MPAM) is an
2035 Partition identifier (PARTID) and Performance Monitoring Group
2042 the PARTID and PMG can also be used as filtering criteria to measure
2046 Use of this extension requires CPU support, support in the
2047 Memory System Components (MSC), and a description from firmware
2048 of where the MSCs are in the address space.
2050 MPAM is exposed to user-space via the resctrl pseudo filesystem.
2057 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2094 and enable enforcement of this for kernel code. When this option
2095 is enabled and the system supports BTI all kernel code including
2100 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2107 that EL0 accesses made via TTBR1 always fault in constant time,
2109 with lower overhead and without disrupting legitimate access to
2115 # Initial support for MTE went in binutils 2.32.0, checked with
2116 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2118 # is only supported in the newer 2.32.x and 2.33 binutils
2120 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2127 # Required for tag checking in the uaccess routines
2135 architectural support for run-time, always-on detection of
2137 to eliminate vulnerabilities arising from memory-unsafe
2145 not be allowed a late bring-up.
2148 explicitly opt in. The mechanism for the userspace is
2149 described in:
2151 Documentation/arch/arm64/memory-tagging-extension.rst.
2163 Access Never to be used with Execute-only mappings.
2165 The feature is detected at runtime, and will remain disabled
2170 def_bool $(as-instr,.arch_extension mops)
2182 enforcing page-based protections, but without requiring modification
2185 For details, see Documentation/core-api/protection-keys.rst
2200 memory access will update the Access Flag in each Table descriptor
2201 which is accessed during the translation table walk and for which
2205 The feature will only be enabled if all the CPUs in the system
2222 stored in the GCS, and may also be used to efficiently obtain
2225 The feature is detected at runtime, and will remain disabled
2235 execution state which complements and extends the SIMD functionality
2236 of the base architecture to support much larger vectors and to enable
2246 is present in:
2248 * version 1.5 and later of the ARM Trusted Firmware
2250 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2255 If you need the kernel to boot on SVE-capable hardware with broken
2258 booting the kernel. If unsure and you are not observing these
2273 bool "Support for NMI-like interrupts"
2276 Adds support for mimicking Non-Maskable Interrupts through the use of
2319 random u64 value in /chosen/kaslr-seed at kernel entry.
2323 to the kernel proper. In addition, it will randomise the physical
2336 but it does imply that function calls between modules and the core
2337 kernel will need to be resolved via veneers in the module PLT.
2341 core kernel, so branch relocations are almost always in range unless
2342 the region is exhausted. In this particular case of region
2346 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2366 bit, for any mappings that meet the size and alignment requirements.
2367 This reduces TLB pressure and improves performance.
2379 protocol even if the corresponding data is present in the ACPI
2386 Provide a set of default command-line options at build time by
2401 Uses the command-line options passed by the boot loader. If
2403 string provided in CMDLINE will be used.
2411 command-line options your boot loader passes to the kernel.
2433 by UEFI firmware (such as non-volatile variables, realtime
2434 clock, and platform reset). A UEFI stub is also provided to
2445 "make zinstall" first, and verifying that everything is fine
2446 in your environment before making "make install" do this for
2458 continue to boot on existing non-UEFI platforms.