Lines Matching +full:cortex +full:- +full:a53
1 # SPDX-License-Identifier: GPL-2.0-only
285 ARM 64-bit (AArch64) Linux support.
293 # required due to use of the -Zfixed-x18 flag.
296 # -Zsanitizer=shadow-call-stack flag.
306 depends on $(cc-option,-fpatchable-function-entry=2)
332 # VA_BITS - PTDESC_TABLE_SHIFT
410 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
415 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
465 at stage-2.
490 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
495 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
498 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
504 data cache clean-and-invalidate.
512 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
517 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
526 data cache clean-and-invalidate.
534 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
539 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
542 If a Cortex-A53 processor is executing a store or prefetch for
549 data cache clean-and-invalidate.
557 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
562 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
571 data cache clean-and-invalidate.
579 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
583 erratum 832075 on Cortex-A57 parts up to r1p2.
585 Affected Cortex-A57 parts might deadlock when exclusive load/store
586 instructions to Write-Back memory are mixed with Device loads.
588 The workaround is to promote device loads to use Load-Acquire
597 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)"
601 erratum 834220 on Cortex-A57 parts up to r1p2.
603 Affected Cortex-A57 parts might report a Stage 2 translation
617 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
621 This option removes the AES hwcap for aarch32 user-space to
622 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
633 bool "Cortex-A53: 845719: a load might read incorrect data"
638 erratum 845719 on Cortex-A53 parts up to r0p4.
640 When running a compat (AArch32) userspace on an affected Cortex-A53
646 return to a 32-bit task.
654 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
657 This option links the kernel with '--fix-cortex-a53-843419' and
660 Cortex-A53 parts up to r0p4.
665 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
668 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
670 Affected Cortex-A55 cores (all revisions) could cause incorrect
672 without a break-before-make. The workaround is to disable the usage
679 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
683 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
686 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
696 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
700 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
702 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
709 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
713 This option adds work arounds for ARM Cortex-A57 erratum 1319537
716 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
722 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
726 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
728 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
738 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"
741 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
743 Under very rare circumstances, affected Cortex-A55 CPUs
744 may not handle a race between a break-before-make sequence on one
754 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)"
757 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
759 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
763 break-before-make sequence, then under very rare circumstances
771 bool "Cortex-A76: Software Step might prevent interrupt recognition"
774 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
776 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
789 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
791 This option adds a workaround for ARM Neoverse-N1 erratum
794 Affected Neoverse-N1 cores could execute a stale instruction when
799 forces user-space to perform cache maintenance.
804 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
807 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
809 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
810 of a store-exclusive or read of PAR_EL1 and a load with device or
811 non-cacheable memory attributes. The workaround depends on a firmware
827 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
830 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
831 Affected Cortex-A510 might not respect the ordering rules for
838 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
841 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
842 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
850 previous guest entry, and can be restored from the in-memory copy.
855 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
858 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
859 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
863 user-space should not be using these instructions.
868 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
873 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
875 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
886 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
891 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
893 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
907 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
911 Enable workaround for ARM Cortex-A710 erratum 2054223
922 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
926 Enable workaround for ARM Neoverse-N2 erratum 2067961
940 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
945 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
947 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
958 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
963 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
965 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
976 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"
979 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
981 Under very rare circumstances, affected Cortex-A510 CPUs
982 may not handle a race between a break-before-make sequence on one
992 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
996 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
998 Affected Cortex-A510 core might fail to write into system registers after the
1010 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
1014 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
1016 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1033 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1037 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1039 Affected Cortex-A510 core might cause trace data corruption, when being written
1051 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1055 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1058 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1068 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1071 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1073 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1074 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1077 Only user-space does executable to non-executable permission transition via
1078 mprotect() system call. Workaround the problem by doing a break-before-make
1087 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1091 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1093 On an affected Cortex-A520 core, a speculatively executed unprivileged
1101 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1105 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1107 On an affected Cortex-A510 core, a speculatively executed unprivileged
1115 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1120 * ARM Cortex-A76 erratum 3324349
1121 * ARM Cortex-A77 erratum 3324348
1122 * ARM Cortex-A78 erratum 3324344
1123 * ARM Cortex-A78C erratum 3324346
1124 * ARM Cortex-A78C erratum 3324347
1125 * ARM Cortex-A710 erratam 3324338
1126 * ARM Cortex-A715 errartum 3456084
1127 * ARM Cortex-A720 erratum 3456091
1128 * ARM Cortex-A725 erratum 3456106
1129 * ARM Cortex-X1 erratum 3324344
1130 * ARM Cortex-X1C erratum 3324346
1131 * ARM Cortex-X2 erratum 3324338
1132 * ARM Cortex-X3 erratum 3324335
1133 * ARM Cortex-X4 erratum 3194386
1134 * ARM Cortex-X925 erratum 3324334
1135 * ARM Neoverse-N1 erratum 3324349
1137 * ARM Neoverse-N3 erratum 3456111
1138 * ARM Neoverse-V1 erratum 3324341
1140 * ARM Neoverse-V3 erratum 3312417
1148 SSBS. The presence of the SSBS special-purpose register is hidden
1160 This implements two gicv3-its errata workarounds for ThunderX. Both
1200 contains data for a non-current ASID. The fix is to
1211 interrupts in host. Trapping both GICv3 group-0 and group-1
1234 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1237 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1238 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1242 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1243 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1244 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1245 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1248 The workaround only affects the Fujitsu-A64FX.
1319 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1338 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1345 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1349 MSI doorbell writes with non-zero values for the device ID.
1381 look-up. AArch32 emulation requires applications compiled
1395 bool "36-bit" if EXPERT
1399 bool "39-bit"
1403 bool "42-bit"
1407 bool "47-bit"
1411 bool "48-bit"
1414 bool "52-bit"
1416 Enable 52-bit virtual addressing for userspace when explicitly
1417 requested via a hint to mmap(). The kernel will also use 52-bit
1419 this feature is available, otherwise it reverts to 48-bit).
1421 NOTE: Enabling 52-bit virtual addressing in conjunction with
1424 impact on its susceptibility to brute-force attacks.
1426 If unsure, select 48-bit virtual addressing instead.
1431 bool "Force 52-bit virtual addresses for userspace"
1434 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1435 to maintain compatibility with older software by providing 48-bit VAs
1438 This configuration option disables the 48-bit compatibility logic, and
1439 forces all userspace addresses to be 52-bit on HW that supports it. One
1460 bool "48-bit"
1464 bool "52-bit"
1467 Enable support for a 52-bit physical address space, introduced as
1468 part of the ARMv8.2-LPA extension.
1471 do not support ARMv8.2-LPA, but with some added memory overhead (and
1494 bool "Build big-endian kernel"
1495 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1498 Say Y if you plan on running a kernel with a big-endian userspace.
1501 bool "Build little-endian kernel"
1503 Say Y if you plan on running a kernel with a little-endian userspace.
1509 bool "Multi-core scheduler support"
1511 Multi-core scheduler support improves the CPU scheduler's decision
1512 making when dealing with multi-core CPU chips at a cost of slightly
1521 by sharing mid-level caches, last-level cache tags or internal
1532 int "Maximum number of CPUs (2-4096)"
1537 bool "Support for hot-pluggable CPUs"
1553 Enable NUMA (Non-Uniform Memory Access) support.
1581 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1653 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1656 # ----+-------------------+--------------+----------------------+-------------------------+
1684 Speculation attacks against some high-performance processors can
1696 Speculation attacks against some high-performance processors can
1698 When taking an exception from user-space, a sequence of branches
1705 Apply read-only attributes of VM areas to the linear alias of
1706 the backing pages as well. This prevents code or read-only data
1721 user-space memory directly by pointing TTBR0_EL1 to a reserved
1732 Documentation/arch/arm64/tagged-address-abi.rst.
1735 bool "Kernel support for 32-bit EL0"
1741 This option enables support for a 32-bit EL0 running under a 64-bit
1742 kernel at EL1. AArch32-specific components such as system calls,
1750 If you want to execute 32-bit userspace applications, say Y.
1755 bool "Enable kuser helpers page for 32-bit applications"
1758 Warning: disabling this option may break 32-bit user programs.
1782 bool "Enable vDSO for 32-bit applications"
1788 Place in the process address space of 32-bit applications an
1792 You must have a 32-bit build of glibc 2.22 or later for programs
1796 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1800 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1801 otherwise with '-marm'.
1804 bool "Fix up misaligned multi-word loads and stores in user space"
1846 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1847 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1862 The SETEND instruction alters the data-endianness of the
1870 for this feature to be enabled. If a new CPU - which doesn't support mixed
1871 endian - is hotplugged in after this feature has been enabled, there could
1890 Similarly, writes to read-only pages with the DBM bit set will
1891 clear the read-only bit (AP[2]) instead of raising a
1895 to work on pre-ARMv8.1 hardware and the performance impact is
1903 prevents the kernel or hypervisor from accessing user-space (EL0)
1924 Say Y here to make use of these instructions for the in-kernel
1989 context-switched along with the process.
2011 If the compiler supports the -mbranch-protection or
2012 -msign-return-address flag (e.g. GCC 7 or later), then this option
2023 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
2027 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
2060 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2068 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2111 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2127 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2131 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2146 architectural support for run-time, always-on detection of
2148 to eliminate vulnerabilities arising from memory-unsafe
2156 not be allowed a late bring-up.
2162 Documentation/arch/arm64/memory-tagging-extension.rst.
2174 Access Never to be used with Execute-only mappings.
2181 def_bool $(as-instr,.arch_extension mops)
2193 enforcing page-based protections, but without requiring modification
2196 For details, see Documentation/core-api/protection-keys.rst
2267 If you need the kernel to boot on SVE-capable hardware with broken
2285 bool "Support for NMI-like interrupts"
2288 Adds support for mimicking Non-Maskable Interrupts through the use of
2331 random u64 value in /chosen/kaslr-seed at kernel entry.
2358 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2366 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated
2399 Provide a set of default command-line options at build time by
2414 Uses the command-line options passed by the boot loader. If
2424 command-line options your boot loader passes to the kernel.
2446 by UEFI firmware (such as non-volatile variables, realtime
2471 continue to boot on existing non-UEFI platforms.