Lines Matching +full:config +full:- +full:space
1 # SPDX-License-Identifier: GPL-2.0-only
2 config ARM64
287 ARM 64-bit (AArch64) Linux support.
289 config RUSTC_SUPPORTS_ARM64
295 # required due to use of the -Zfixed-x18 flag.
298 # -Zsanitizer=shadow-call-stack flag.
301 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
306 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
308 depends on $(cc-option,-fpatchable-function-entry=2)
310 config 64BIT
313 config MMU
316 config ARM64_CONT_PTE_SHIFT
322 config ARM64_CONT_PMD_SHIFT
328 config ARCH_MMAP_RND_BITS_MIN
334 # VA_BITS - PTDESC_TABLE_SHIFT
335 config ARCH_MMAP_RND_BITS_MAX
347 config ARCH_MMAP_RND_COMPAT_BITS_MIN
352 config ARCH_MMAP_RND_COMPAT_BITS_MAX
355 config NO_IOPORT_MAP
358 config STACKTRACE_SUPPORT
361 config ILLEGAL_POINTER_VALUE
365 config LOCKDEP_SUPPORT
368 config GENERIC_BUG
372 config GENERIC_BUG_RELATIVE_POINTERS
376 config GENERIC_HWEIGHT
379 config GENERIC_CSUM
382 config GENERIC_CALIBRATE_DELAY
385 config SMP
388 config KERNEL_MODE_NEON
391 config FIX_EARLYCON_MEM
394 config PGTABLE_LEVELS
405 config ARCH_SUPPORTS_UPROBES
408 config ARCH_PROC_KCORE_TEXT
411 config BROKEN_GAS_INST
412 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
414 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
417 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
428 config KASAN_SHADOW_OFFSET
443 config UNWIND_TABLES
452 config AMPERE_ERRATUM_AC03_CPU_38
467 at stage-2.
471 config AMPERE_ERRATUM_AC04_CPU_23
488 config ARM64_WORKAROUND_CLEAN_CACHE
491 config ARM64_ERRATUM_826319
492 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
497 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
500 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
506 data cache clean-and-invalidate.
513 config ARM64_ERRATUM_827319
514 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
519 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
528 data cache clean-and-invalidate.
535 config ARM64_ERRATUM_824069
536 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
541 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
544 If a Cortex-A53 processor is executing a store or prefetch for
551 data cache clean-and-invalidate.
558 config ARM64_ERRATUM_819472
559 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
564 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
573 data cache clean-and-invalidate.
580 config ARM64_ERRATUM_832075
581 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
585 erratum 832075 on Cortex-A57 parts up to r1p2.
587 Affected Cortex-A57 parts might deadlock when exclusive load/store
588 instructions to Write-Back memory are mixed with Device loads.
590 The workaround is to promote device loads to use Load-Acquire
598 config ARM64_ERRATUM_834220
599 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
603 erratum 834220 on Cortex-A57 parts up to r1p2.
605 Affected Cortex-A57 parts might report a Stage 2 translation
618 config ARM64_ERRATUM_1742098
619 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
623 This option removes the AES hwcap for aarch32 user-space to
624 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
634 config ARM64_ERRATUM_845719
635 bool "Cortex-A53: 845719: a load might read incorrect data"
640 erratum 845719 on Cortex-A53 parts up to r0p4.
642 When running a compat (AArch32) userspace on an affected Cortex-A53
648 return to a 32-bit task.
655 config ARM64_ERRATUM_843419
656 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
659 This option links the kernel with '--fix-cortex-a53-843419' and
662 Cortex-A53 parts up to r0p4.
666 config ARM64_ERRATUM_1024718
667 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
670 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
672 Affected Cortex-A55 cores (all revisions) could cause incorrect
674 without a break-before-make. The workaround is to disable the usage
680 config ARM64_ERRATUM_1418040
681 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
685 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
688 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
694 config ARM64_WORKAROUND_SPECULATIVE_AT
697 config ARM64_ERRATUM_1165522
698 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
702 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
704 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
710 config ARM64_ERRATUM_1319367
711 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
715 This option adds work arounds for ARM Cortex-A57 erratum 1319537
718 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
723 config ARM64_ERRATUM_1530923
724 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
728 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
730 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
736 config ARM64_WORKAROUND_REPEAT_TLBI
739 config ARM64_ERRATUM_2441007
740 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
743 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
745 Under very rare circumstances, affected Cortex-A55 CPUs
746 may not handle a race between a break-before-make sequence on one
755 config ARM64_ERRATUM_1286807
756 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
759 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
761 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
765 break-before-make sequence, then under very rare circumstances
772 config ARM64_ERRATUM_1463225
773 bool "Cortex-A76: Software Step might prevent interrupt recognition"
776 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
778 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
790 config ARM64_ERRATUM_1542419
791 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
793 This option adds a workaround for ARM Neoverse-N1 erratum
796 Affected Neoverse-N1 cores could execute a stale instruction when
801 forces user-space to perform cache maintenance.
805 config ARM64_ERRATUM_1508412
806 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
809 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
811 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
812 of a store-exclusive or read of PAR_EL1 and a load with device or
813 non-cacheable memory attributes. The workaround depends on a firmware
825 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
828 config ARM64_ERRATUM_2051678
829 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
832 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
833 Affected Cortex-A510 might not respect the ordering rules for
839 config ARM64_ERRATUM_2077057
840 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
843 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
844 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
852 previous guest entry, and can be restored from the in-memory copy.
856 config ARM64_ERRATUM_2658417
857 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
860 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
861 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
865 user-space should not be using these instructions.
869 config ARM64_ERRATUM_2119858
870 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
875 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
877 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
887 config ARM64_ERRATUM_2139208
888 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
893 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
895 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
905 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
908 config ARM64_ERRATUM_2054223
909 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
913 Enable workaround for ARM Cortex-A710 erratum 2054223
923 config ARM64_ERRATUM_2067961
924 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
928 Enable workaround for ARM Neoverse-N2 erratum 2067961
938 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
941 config ARM64_ERRATUM_2253138
942 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
947 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
949 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
951 virtually addressed page following the last page of the TRBE address space
955 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
959 config ARM64_ERRATUM_2224489
960 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
965 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
967 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
969 virtually addressed page following the last page of the TRBE address space
973 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
977 config ARM64_ERRATUM_2441009
978 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
981 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
983 Under very rare circumstances, affected Cortex-A510 CPUs
984 may not handle a race between a break-before-make sequence on one
993 config ARM64_ERRATUM_2064142
994 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
998 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
1000 Affected Cortex-A510 core might fail to write into system registers after the
1011 config ARM64_ERRATUM_2038923
1012 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
1016 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
1018 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1034 config ARM64_ERRATUM_1902691
1035 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1039 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1041 Affected Cortex-A510 core might cause trace data corruption, when being written
1052 config ARM64_ERRATUM_2457168
1053 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1057 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1060 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1069 config ARM64_ERRATUM_2645198
1070 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1073 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1075 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1076 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1079 Only user-space does executable to non-executable permission transition via
1080 mprotect() system call. Workaround the problem by doing a break-before-make
1081 TLB invalidation, for all changes to executable user space mappings.
1085 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1088 config ARM64_ERRATUM_2966298
1089 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1093 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1095 On an affected Cortex-A520 core, a speculatively executed unprivileged
1102 config ARM64_ERRATUM_3117295
1103 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1107 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1109 On an affected Cortex-A510 core, a speculatively executed unprivileged
1116 config ARM64_ERRATUM_3194386
1117 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1122 * ARM Cortex-A76 erratum 3324349
1123 * ARM Cortex-A77 erratum 3324348
1124 * ARM Cortex-A78 erratum 3324344
1125 * ARM Cortex-A78C erratum 3324346
1126 * ARM Cortex-A78C erratum 3324347
1127 * ARM Cortex-A710 erratam 3324338
1128 * ARM Cortex-A715 errartum 3456084
1129 * ARM Cortex-A720 erratum 3456091
1130 * ARM Cortex-A725 erratum 3456106
1131 * ARM Cortex-X1 erratum 3324344
1132 * ARM Cortex-X1C erratum 3324346
1133 * ARM Cortex-X2 erratum 3324338
1134 * ARM Cortex-X3 erratum 3324335
1135 * ARM Cortex-X4 erratum 3194386
1136 * ARM Cortex-X925 erratum 3324334
1137 * ARM Neoverse-N1 erratum 3324349
1139 * ARM Neoverse-N3 erratum 3456111
1140 * ARM Neoverse-V1 erratum 3324341
1142 * ARM Neoverse-V3 erratum 3312417
1143 * ARM Neoverse-V3AE erratum 3312417
1151 SSBS. The presence of the SSBS special-purpose register is hidden
1157 config CAVIUM_ERRATUM_22375
1163 This implements two gicv3-its errata workarounds for ThunderX. Both
1174 config CAVIUM_ERRATUM_23144
1183 config CAVIUM_ERRATUM_23154
1197 config CAVIUM_ERRATUM_27456
1203 contains data for a non-current ASID. The fix is to
1208 config CAVIUM_ERRATUM_30115
1214 interrupts in host. Trapping both GICv3 group-0 and group-1
1219 config CAVIUM_TX2_ERRATUM_219
1236 config FUJITSU_ERRATUM_010001
1237 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1240 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1241 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1245 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1246 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1247 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1248 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1251 The workaround only affects the Fujitsu-A64FX.
1255 config HISILICON_ERRATUM_161600802
1265 config HISILICON_ERRATUM_162100801
1276 config QCOM_FALKOR_ERRATUM_1003
1287 config QCOM_FALKOR_ERRATUM_1009
1298 config QCOM_QDF2400_ERRATUM_0065
1308 config QCOM_FALKOR_ERRATUM_E1041
1318 config NVIDIA_CARMEL_CNP_ERRATUM
1322 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1328 config ROCKCHIP_ERRATUM_3568002
1333 addressing limited to the first 32bit of physical address space.
1337 config ROCKCHIP_ERRATUM_3588001
1341 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1347 config SOCIONEXT_SYNQUACER_PREITS
1348 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1352 MSI doorbell writes with non-zero values for the device ID.
1364 config ARM64_4K_PAGES
1370 config ARM64_16K_PAGES
1378 config ARM64_64K_PAGES
1384 look-up. AArch32 emulation requires applications compiled
1390 prompt "Virtual address space size"
1394 space sizes. The level of translation table is determined by
1395 a combination of page size and virtual address space size.
1397 config ARM64_VA_BITS_36
1398 bool "36-bit" if EXPERT
1401 config ARM64_VA_BITS_39
1402 bool "39-bit"
1405 config ARM64_VA_BITS_42
1406 bool "42-bit"
1409 config ARM64_VA_BITS_47
1410 bool "47-bit"
1413 config ARM64_VA_BITS_48
1414 bool "48-bit"
1416 config ARM64_VA_BITS_52
1417 bool "52-bit"
1419 Enable 52-bit virtual addressing for userspace when explicitly
1420 requested via a hint to mmap(). The kernel will also use 52-bit
1422 this feature is available, otherwise it reverts to 48-bit).
1424 NOTE: Enabling 52-bit virtual addressing in conjunction with
1427 impact on its susceptibility to brute-force attacks.
1429 If unsure, select 48-bit virtual addressing instead.
1433 config ARM64_FORCE_52BIT
1434 bool "Force 52-bit virtual addresses for userspace"
1437 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1438 to maintain compatibility with older software by providing 48-bit VAs
1441 This configuration option disables the 48-bit compatibility logic, and
1442 forces all userspace addresses to be 52-bit on HW that supports it. One
1446 config ARM64_VA_BITS
1456 prompt "Physical address space size"
1462 config ARM64_PA_BITS_48
1463 bool "48-bit"
1466 config ARM64_PA_BITS_52
1467 bool "52-bit"
1470 Enable support for a 52-bit physical address space, introduced as
1471 part of the ARMv8.2-LPA extension.
1474 do not support ARMv8.2-LPA, but with some added memory overhead (and
1479 config ARM64_PA_BITS
1484 config ARM64_LPA2
1496 config CPU_BIG_ENDIAN
1497 bool "Build big-endian kernel"
1500 Say Y if you plan on running a kernel with a big-endian userspace.
1502 config CPU_LITTLE_ENDIAN
1503 bool "Build little-endian kernel"
1505 Say Y if you plan on running a kernel with a little-endian userspace.
1510 config NR_CPUS
1511 int "Maximum number of CPUs (2-4096)"
1515 config HOTPLUG_CPU
1516 bool "Support for hot-pluggable CPUs"
1523 config NUMA
1532 Enable NUMA (Non-Uniform Memory Access) support.
1538 config NODES_SHIFT
1549 config ARCH_SPARSEMEM_ENABLE
1553 config HW_PERF_EVENTS
1558 config CC_HAVE_SHADOW_CALL_STACK
1559 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1561 config PARAVIRT
1568 config PARAVIRT_TIME_ACCOUNTING
1579 config ARCH_SUPPORTS_KEXEC
1582 config ARCH_SUPPORTS_KEXEC_FILE
1585 config ARCH_SELECTS_KEXEC_FILE
1590 config ARCH_SUPPORTS_KEXEC_SIG
1593 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG
1596 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG
1599 config ARCH_SUPPORTS_KEXEC_HANDOVER
1602 config ARCH_SUPPORTS_CRASH_DUMP
1605 config ARCH_DEFAULT_CRASH_DUMP
1608 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
1611 config TRANS_TABLE
1615 config XEN_DOM0
1619 config XEN
1631 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1634 # ----+-------------------+--------------+----------------------+-------------------------+
1638 config ARCH_FORCE_MAX_ORDER
1658 config UNMAP_KERNEL_AT_EL0
1662 Speculation attacks against some high-performance processors can
1670 config MITIGATE_SPECTRE_BRANCH_HISTORY
1674 Speculation attacks against some high-performance processors can
1676 When taking an exception from user-space, a sequence of branches
1679 config ARM64_SW_TTBR0_PAN
1685 user-space memory directly by pointing TTBR0_EL1 to a reserved
1689 config ARM64_TAGGED_ADDR_ABI
1696 Documentation/arch/arm64/tagged-address-abi.rst.
1699 bool "Kernel support for 32-bit EL0"
1705 This option enables support for a 32-bit EL0 running under a 64-bit
1706 kernel at EL1. AArch32-specific components such as system calls,
1714 If you want to execute 32-bit userspace applications, say Y.
1718 config KUSER_HELPERS
1719 bool "Enable kuser helpers page for 32-bit applications"
1722 Warning: disabling this option may break 32-bit user programs.
1745 config COMPAT_VDSO
1746 bool "Enable vDSO for 32-bit applications"
1751 Place in the process address space of 32-bit applications an
1755 You must have a 32-bit build of glibc 2.22 or later for programs
1758 config THUMB2_COMPAT_VDSO
1759 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1763 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1764 otherwise with '-marm'.
1766 config COMPAT_ALIGNMENT_FIXUPS
1767 bool "Fix up misaligned multi-word loads and stores in user space"
1776 Enable this config to enable selective emulation of these
1783 config SWP_EMULATION
1806 config CP15_BARRIER_EMULATION
1809 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1810 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1822 config SETEND_EMULATION
1825 The SETEND instruction alters the data-endianness of the
1833 for this feature to be enabled. If a new CPU - which doesn't support mixed
1834 endian - is hotplugged in after this feature has been enabled, there could
1844 config ARM64_HW_AFDBM
1853 Similarly, writes to read-only pages with the DBM bit set will
1854 clear the read-only bit (AP[2]) instead of raising a
1858 to work on pre-ARMv8.1 hardware and the performance impact is
1861 config ARM64_PAN
1866 prevents the kernel or hypervisor from accessing user-space (EL0)
1875 config ARM64_LSE_ATOMICS
1879 config ARM64_USE_LSE_ATOMICS
1887 Say Y here to make use of these instructions for the in-kernel
1895 config ARM64_PMEM
1907 config ARM64_RAS_EXTN
1923 config ARM64_CNP
1940 config ARM64_PTR_AUTH
1952 context-switched along with the process.
1964 config ARM64_PTR_AUTH_KERNEL
1974 If the compiler supports the -mbranch-protection or
1975 -msign-return-address flag (e.g. GCC 7 or later), then this option
1984 config CC_HAS_BRANCH_PROT_PAC_RET
1986 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1988 config AS_HAS_CFI_NEGATE_RA_STATE
1990 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1996 config ARM64_AMU_EXTN
2019 config ARM64_TLB_RANGE
2023 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2030 config AS_HAS_ARMV8_5
2031 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2033 config ARM64_BTI
2055 config ARM64_BTI_KERNEL
2072 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
2074 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2076 config ARM64_E0PD
2088 config ARM64_AS_HAS_MTE
2090 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2094 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2096 config ARM64_MTE
2109 architectural support for run-time, always-on detection of
2111 to eliminate vulnerabilities arising from memory-unsafe
2119 not be allowed a late bring-up.
2125 Documentation/arch/arm64/memory-tagging-extension.rst.
2131 config ARM64_EPAN
2137 Access Never to be used with Execute-only mappings.
2143 config AS_HAS_MOPS
2144 def_bool $(as-instr,.arch_extension mops)
2148 config ARM64_POE
2156 enforcing page-based protections, but without requiring modification
2159 For details, see Documentation/core-api/protection-keys.rst
2163 config ARCH_PKEY_BITS
2167 config ARM64_HAFT
2186 config ARM64_GCS
2204 config ARM64_SVE
2229 If you need the kernel to boot on SVE-capable hardware with broken
2235 config ARM64_SME
2246 config ARM64_PSEUDO_NMI
2247 bool "Support for NMI-like interrupts"
2250 Adds support for mimicking Non-Maskable Interrupts through the use of
2261 config ARM64_DEBUG_PRIORITY_MASKING
2271 config RELOCATABLE
2284 config RANDOMIZE_BASE
2293 random u64 value in /chosen/kaslr-seed at kernel entry.
2302 config RANDOMIZE_MODULE_REGION_FULL
2319 config CC_HAVE_STACKPROTECTOR_SYSREG
2320 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2322 config STACKPROTECTOR_PER_TASK
2326 config UNWIND_PATCH_PAC_INTO_SCS
2334 config ARM64_CONTPTE
2347 config ARM64_ACPI_PARKING_PROTOCOL
2356 config CMDLINE
2360 Provide a set of default command-line options at build time by
2372 config CMDLINE_FROM_BOOTLOADER
2375 Uses the command-line options passed by the boot loader. If
2379 config CMDLINE_FORCE
2385 command-line options your boot loader passes to the kernel.
2389 config EFI_STUB
2392 config EFI
2407 by UEFI firmware (such as non-volatile variables, realtime
2412 config COMPRESSED_INSTALL
2423 config DMI
2432 continue to boot on existing non-UEFI platforms.
2440 config ARCH_HIBERNATION_POSSIBLE
2444 config ARCH_HIBERNATION_HEADER
2448 config ARCH_SUSPEND_POSSIBLE