Lines Matching +full:0 +full:x41000000
30 * the least significant 16 bits to be 0x8000, but we could probably
31 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
34 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
35 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
40 #define PG_DIR_SIZE 0x5000
43 #define PG_DIR_SIZE 0x4000
60 .long 0
61 .long 0
63 .long 0
64 .long 0
77 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
81 * 0xc0008000, you call this at __pa(0xc0008000).
107 mrc p15, 0, r9, c0, c0 @ get processor id
109 movs r10, r5 @ invalid processor (r5=0)?
114 mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0
115 and r3, r3, #0xf @ extract VMSA support
164 mov r5, #0 @ high TTBR0
194 mov r3, #0
209 add r3, r4, #0x1000 @ first PMD table address
221 add r3, r3, #0x1000 @ next PMD table
225 add r4, r4, #0x1000 @ point to the PMD tables
287 add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
288 str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ENTRY_ORDER]!
303 cmp r2, #0
356 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
357 orr r3, r7, #0x7c000000
362 * Map in screen at 0x02000000 & SCREEN2_BASE
366 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
367 orr r3, r7, #0x02000000
369 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
374 sub r4, r4, #0x1000 @ point to the PGD table
404 mrc p15, 0, r9, c0, c0 @ get processor id
420 ldrd r4, r5, [r3, #0] @ get secondary_data.pgdir
438 mrc p15, 0, ip, c2, c0, 1 @ read TTBR1
439 mcr p15, 0, ip, c2, c0, 0 @ set TTBR0
445 mov fp, #0
483 mcrr p15, 0, r4, r5, c2 @ load TTBR0
486 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
487 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
511 mcr p15, 0, r0, c1, c0, 0 @ write control reg
512 mrc p15, 0, r3, c0, c0, 0 @ read id reg
525 and r3, r9, #0x000f0000 @ architecture version
526 teq r3, #0x000f0000 @ CPU ID supported?
529 bic r3, r9, #0x00ff0000
530 bic r3, r3, #0x0000000f @ mask 0xff00fff0
531 mov r4, #0x41000000
532 orr r4, r4, #0x0000b000
533 orr r4, r4, #0x00000020 @ val 0x4100b020
537 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
538 and r0, r0, #0xc0000000 @ multiprocessing extensions and
539 teq r0, #0x80000000 @ not part of a uniprocessor system?
544 mov r4, #0x41000000
545 orr r4, r4, #0x0000c000
546 orr r4, r4, #0x00000090
550 @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the
554 teq r0, #0x0 @ '0' on actual UP A9 hardware
558 and r0, r0, #0x3 @ number of CPUs
559 teq r0, #0x0 @ is 1?
573 ALT_UP(.long 0)