Lines Matching +full:0 +full:x021b8000
61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
128 #clock-cells = <0>;
129 clock-frequency = <0>;
135 #clock-cells = <0>;
136 clock-frequency = <0>;
154 #phy-cells = <0>;
166 reg = <0x008f8000 0x4000>;
167 ranges = <0 0x008f8000 0x4000>;
175 reg = <0x00900000 0x20000>;
176 ranges = <0 0x00900000 0x20000>;
186 reg = <0x00a01000 0x1000>,
187 <0x00a00100 0x100>;
193 reg = <0x00a02000 0x1000>;
203 reg = <0x01800000 0x4000>;
214 reg = <0x01804000 0x2000>;
228 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
239 dmas = <&dma_apbh 0>;
248 reg = <0x02000000 0x100000>;
255 reg = <0x02000000 0x40000>;
260 reg = <0x02004000 0x4000>;
262 dmas = <&sdma 14 18 0>,
263 <&sdma 15 18 0>;
268 <&clks 0>, <&clks 0>, <&clks 0>,
270 <&clks 0>, <&clks 0>,
282 #size-cells = <0>;
284 reg = <0x02008000 0x4000>;
294 #size-cells = <0>;
296 reg = <0x0200c000 0x4000>;
306 #size-cells = <0>;
308 reg = <0x02010000 0x4000>;
318 #size-cells = <0>;
320 reg = <0x02014000 0x4000>;
331 reg = <0x02020000 0x4000>;
336 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
343 reg = <0x02024000 0x4000>;
351 dmas = <&sdma 23 21 0>,
352 <&sdma 24 21 0>;
358 #sound-dai-cells = <0>;
360 reg = <0x02028000 0x4000>;
365 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
372 #sound-dai-cells = <0>;
374 reg = <0x0202c000 0x4000>;
379 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
386 #sound-dai-cells = <0>;
388 reg = <0x02030000 0x4000>;
393 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
401 reg = <0x02034000 0x4000>;
404 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
405 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
406 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
407 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
408 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
428 reg = <0x02080000 0x4000>;
438 reg = <0x02084000 0x4000>;
448 reg = <0x02088000 0x4000>;
458 reg = <0x0208c000 0x4000>;
468 reg = <0x02090000 0x4000>;
473 fsl,stop-mode = <&gpr 0x10 1>;
479 reg = <0x02094000 0x4000>;
484 fsl,stop-mode = <&gpr 0x10 2>;
490 reg = <0x02098000 0x4000>;
499 reg = <0x0209c000 0x4000>;
506 gpio-ranges = <&iomuxc 0 5 26>;
511 reg = <0x020a0000 0x4000>;
518 gpio-ranges = <&iomuxc 0 31 20>;
523 reg = <0x020a4000 0x4000>;
530 gpio-ranges = <&iomuxc 0 51 29>;
535 reg = <0x020a8000 0x4000>;
542 gpio-ranges = <&iomuxc 0 80 32>;
547 reg = <0x020ac000 0x4000>;
554 gpio-ranges = <&iomuxc 0 112 24>;
559 reg = <0x020b0000 0x4000>;
566 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
571 reg = <0x020b4000 0x4000>;
578 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
583 reg = <0x020b8000 0x4000>;
591 reg = <0x020bc000 0x4000>;
598 reg = <0x020c0000 0x4000>;
606 reg = <0x020c4000 0x4000>;
617 reg = <0x020c8000 0x1000>;
628 anatop-reg-offset = <0x110>;
634 anatop-enable-bit = <0>;
643 anatop-reg-offset = <0x120>;
646 anatop-min-bit-val = <0>;
649 anatop-enable-bit = <0>;
658 anatop-reg-offset = <0x130>;
661 anatop-min-bit-val = <0>;
664 anatop-enable-bit = <0>;
673 anatop-reg-offset = <0x140>;
674 anatop-vol-bit-shift = <0>;
676 anatop-delay-reg-offset = <0x170>;
689 anatop-reg-offset = <0x140>;
692 anatop-delay-reg-offset = <0x170>;
706 anatop-reg-offset = <0x140>;
709 anatop-delay-reg-offset = <0x170>;
730 reg = <0x020c9000 0x1000>;
738 reg = <0x020ca000 0x1000>;
745 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
746 reg = <0x020cc000 0x4000>;
749 compatible = "fsl,sec-v4.0-mon-rtc-lp";
751 offset = <0x34>;
758 offset = <0x38>;
759 value = <0x60>;
760 mask = <0x60>;
765 compatible = "fsl,sec-v4.0-pwrkey";
775 reg = <0x020d0000 0x4000>;
780 reg = <0x020d4000 0x4000>;
786 reg = <0x020d8000 0x4000>;
794 reg = <0x020dc000 0x4000>;
804 #size-cells = <0>;
806 power-domain@0 {
807 reg = <0>;
808 #power-domain-cells = <0>;
813 #power-domain-cells = <0>;
820 #power-domain-cells = <0>;
832 #power-domain-cells = <0>;
840 reg = <0x020e0000 0x4000>;
848 reg = <0x020e4000 0x4000>;
852 reg = <0x18 0x4>;
859 #size-cells = <0>;
861 port@0 {
862 reg = <0>;
880 reg = <0x020ec000 0x4000>;
895 reg = <0x02100000 0x100000>;
899 compatible = "fsl,sec-v4.0";
902 reg = <0x2100000 0x10000>;
903 ranges = <0 0x2100000 0x10000>;
912 compatible = "fsl,sec-v4.0-job-ring";
913 reg = <0x1000 0x1000>;
918 compatible = "fsl,sec-v4.0-job-ring";
919 reg = <0x2000 0x1000>;
926 reg = <0x02184000 0x200>;
930 fsl,usbmisc = <&usbmisc 0>;
931 ahb-burst-config = <0x0>;
932 tx-burst-size-dword = <0x10>;
933 rx-burst-size-dword = <0x10>;
939 reg = <0x02184200 0x200>;
944 ahb-burst-config = <0x0>;
945 tx-burst-size-dword = <0x10>;
946 rx-burst-size-dword = <0x10>;
952 reg = <0x02184400 0x200>;
959 ahb-burst-config = <0x0>;
960 tx-burst-size-dword = <0x10>;
961 rx-burst-size-dword = <0x10>;
968 reg = <0x02184800 0x200>;
974 reg = <0x02188000 0x4000>;
987 fsl,stop-mode = <&gpr 0x10 3>;
992 reg = <0x0218c000 0x4000>;
1002 reg = <0x02190000 0x4000>;
1016 reg = <0x02194000 0x4000>;
1030 reg = <0x02198000 0x4000>;
1044 reg = <0x0219c000 0x4000>;
1056 #size-cells = <0>;
1058 reg = <0x021a0000 0x4000>;
1066 #size-cells = <0>;
1068 reg = <0x021a4000 0x4000>;
1076 #size-cells = <0>;
1078 reg = <0x021a8000 0x4000>;
1086 reg = <0x021b0000 0x4000>;
1092 reg = <0x021b4000 0x4000>;
1103 fsl,stop-mode = <&gpr 0x10 4>;
1111 reg = <0x021b8000 0x4000>;
1122 reg = <0x021bc000 0x4000>;
1126 reg = <0x10 4>;
1130 reg = <0x38 4>;
1134 reg = <0x20 4>;
1140 reg = <0x021d4000 0x4000>;
1144 <&clks 0>, <&clks 0>;
1147 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1153 reg = <0x021d8000 0x4000>;
1159 reg = <0x021dc000 0x4000>;
1163 <&clks 0>, <&clks 0>;
1166 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1172 #size-cells = <0>;
1174 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1185 #size-cells = <0>;
1187 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1199 reg = <0x021e8000 0x4000>;
1204 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1212 reg = <0x021ec000 0x4000>;
1217 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1225 reg = <0x021f0000 0x4000>;
1230 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1238 reg = <0x021f4000 0x4000>;
1243 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1250 #size-cells = <0>;
1252 reg = <0x021f8000 0x4000>;
1263 reg = <0x02200000 0x100000>;
1270 reg = <0x02240000 0x40000>;
1274 reg = <0x02214000 0x4000>;
1285 reg = <0x02218000 0x4000>;
1294 reg = <0x0221c000 0x4000>;
1305 reg = <0x02220000 0x4000>;
1326 reg = <0x02224000 0x4000>;
1337 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1349 reg = <0x02280000 0x4000>;
1360 reg = <0x02284000 0x4000>;
1371 reg = <0x02288000 0x4000>;
1379 #size-cells = <0>;
1381 reg = <0x0228c000 0x4000>;
1392 reg = <0x022a0000 0x4000>;
1397 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1404 reg = <0x022a4000 0x4000>;
1414 reg = <0x022a8000 0x4000>;
1424 reg = <0x022ac000 0x4000>;
1434 reg = <0x022b0000 0x4000>;
1445 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1450 bus-range = <0x00 0xff>;
1451 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */
1452 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1457 interrupt-map-mask = <0 0 0 0x7>;
1458 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1459 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1460 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1461 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;