Lines Matching refs:erratum

569 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
578 	  r1p* erratum. If a code sequence containing an ARM/Thumb
595 	  erratum. For very specific sequences of memory operations, it is
611 	  erratum. Any asynchronous access to the L2 cache may encounter a
626 	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
642 	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
660 	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
670 	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
672 	  As a consequence of this erratum, some TLB entries which should be
683 	  (r2p*) erratum. Under very rare conditions, a faulty
699 	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
713 	  r3p*) erratum. A speculative memory access may cause a page table walk
724 	  r2p0) erratum. The Store Buffer does not have any automatic draining
735 	  r0p2 erratum (possible cache data corruption with
746 	  This option enables the workaround for erratum 764369
760 	  This option enables the workaround for the 764319 Cortex-A9 erratum.
772 	 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
783 	  option enables the Linux kernel workaround for this erratum
792 	  (up to r0p4) erratum. In certain rare sequences of code, the
794 	  workaround disables the loop buffer to avoid the erratum.
815 	  (all revs) erratum. In very rare timing conditions, a sequence
825 	  (all revs) erratum. Within rare timing constraints, executing a
834 	  (all revs) erratum. Under very rare timing conditions, the CPU might
842 	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
854 	  This is identical to Cortex-A12 erratum 852422.  It is a separate
855 	  config option from the A12 erratum due to the way errata are checked
862 	  This option enables the workaround for the 857272 Cortex-A17 erratum.
863 	  This erratum is not known to be fixed in any A17 revision.
864 	  This is identical to Cortex-A12 erratum 857271.  It is a separate
865 	  config option from the A12 erratum due to the way errata are checked
894 	  However, because of this erratum, an L2 set/way cache maintenance