Lines Matching +full:timer +full:- +full:secure
1 # SPDX-License-Identifier: GPL-2.0
50 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de
168 The ARM series is a line of low-power-consumption RISC chip designs
170 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
171 manufactured, but legacy ARM-based PC hardware remains popular in
179 relocations. The combined range is -/+ 256 MiB, which is usually
272 Patch phys-to-virt and virt-to-phys translation functions at
276 This can only be used with non-XIP MMU kernels where the base
322 bool "MMU-based Paged Memory Management Support"
325 Select if you want MMU-based virtualised addressing space
360 # This is sorted alphabetically by mach-* pathname. However, plat-*
362 # plat- suffix) or along side the corresponding mach-* source.
364 source "arch/arm/mach-actions/Kconfig"
366 source "arch/arm/mach-alpine/Kconfig"
368 source "arch/arm/mach-artpec/Kconfig"
370 source "arch/arm/mach-aspeed/Kconfig"
372 source "arch/arm/mach-at91/Kconfig"
374 source "arch/arm/mach-axxia/Kconfig"
376 source "arch/arm/mach-bcm/Kconfig"
378 source "arch/arm/mach-berlin/Kconfig"
380 source "arch/arm/mach-clps711x/Kconfig"
382 source "arch/arm/mach-davinci/Kconfig"
384 source "arch/arm/mach-digicolor/Kconfig"
386 source "arch/arm/mach-dove/Kconfig"
388 source "arch/arm/mach-ep93xx/Kconfig"
390 source "arch/arm/mach-exynos/Kconfig"
392 source "arch/arm/mach-footbridge/Kconfig"
394 source "arch/arm/mach-gemini/Kconfig"
396 source "arch/arm/mach-highbank/Kconfig"
398 source "arch/arm/mach-hisi/Kconfig"
400 source "arch/arm/mach-imx/Kconfig"
402 source "arch/arm/mach-ixp4xx/Kconfig"
404 source "arch/arm/mach-keystone/Kconfig"
406 source "arch/arm/mach-lpc32xx/Kconfig"
408 source "arch/arm/mach-mediatek/Kconfig"
410 source "arch/arm/mach-meson/Kconfig"
412 source "arch/arm/mach-milbeaut/Kconfig"
414 source "arch/arm/mach-mmp/Kconfig"
416 source "arch/arm/mach-mstar/Kconfig"
418 source "arch/arm/mach-mv78xx0/Kconfig"
420 source "arch/arm/mach-mvebu/Kconfig"
422 source "arch/arm/mach-mxs/Kconfig"
424 source "arch/arm/mach-nomadik/Kconfig"
426 source "arch/arm/mach-npcm/Kconfig"
428 source "arch/arm/mach-omap1/Kconfig"
430 source "arch/arm/mach-omap2/Kconfig"
432 source "arch/arm/mach-orion5x/Kconfig"
434 source "arch/arm/mach-pxa/Kconfig"
436 source "arch/arm/mach-qcom/Kconfig"
438 source "arch/arm/mach-realtek/Kconfig"
440 source "arch/arm/mach-rpc/Kconfig"
442 source "arch/arm/mach-rockchip/Kconfig"
444 source "arch/arm/mach-s3c/Kconfig"
446 source "arch/arm/mach-s5pv210/Kconfig"
448 source "arch/arm/mach-sa1100/Kconfig"
450 source "arch/arm/mach-shmobile/Kconfig"
452 source "arch/arm/mach-socfpga/Kconfig"
454 source "arch/arm/mach-spear/Kconfig"
456 source "arch/arm/mach-sti/Kconfig"
458 source "arch/arm/mach-stm32/Kconfig"
460 source "arch/arm/mach-sunxi/Kconfig"
462 source "arch/arm/mach-tegra/Kconfig"
464 source "arch/arm/mach-ux500/Kconfig"
466 source "arch/arm/mach-versatile/Kconfig"
468 source "arch/arm/mach-vt8500/Kconfig"
470 source "arch/arm/mach-zte/Kconfig"
472 source "arch/arm/mach-zynq/Kconfig"
474 # ARMv7-M architecture
483 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
494 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
495 with a range of available cores like Cortex-M3/M4/M7.
529 and support is deprecated in new gcc-14. While there were a
538 source "arch/arm/Kconfig-nommu"
556 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
559 Executing a SWP instruction to read-only memory does not set bit 11
577 This option enables the workaround for the 430973 Cortex-A8
580 same virtual address, whether due to self-modifying code or virtual
581 to physical address re-mapping, Cortex-A8 does not recover from the
582 stale interworking branch prediction. This results in Cortex-A8
587 available in non-secure mode.
594 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
601 register may not be available in non-secure mode and thus is not
610 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
614 workaround disables the write-allocate mode for the L2 cache via the
616 may not be available in non-secure mode and thus is not available on
625 This option enables the workaround for the 742230 Cortex-A9
629 the diagnostic register of the Cortex-A9 which causes the DMB
632 register may not be available in non-secure mode and thus is not
641 This option enables the workaround for the 742231 Cortex-A9
643 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
648 register of the Cortex-A9 which reduces the linefill issuing
650 diagnostics register may not be available in non-secure mode and thus
659 This option enables the workaround for the 643719 Cortex-A9 (prior to
669 This option enables the workaround for the 720789 Cortex-A9 (prior to
682 This option enables the workaround for the 743622 Cortex-A9
684 optimisation in the Cortex-A9 Store Buffer may lead to data
686 register of the Cortex-A9 which disables the Store Buffer
690 may not be available in non-secure mode and thus is not available on a
698 This option enables the workaround for the 751472 Cortex-A9 (prior
704 not be available in non-secure mode and thus is not available on
712 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
715 can populate the micro-TLB with a stale entry which may be hit with
723 This option enables the workaround for the 754327 Cortex-A9 (prior to
731 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
736 hit-under-miss enabled). It sets the undocumented bit 31 in
738 register, thus disabling hit-under-miss without putting the
747 affecting Cortex-A9 MPCore with two or more processors (all
760 This option enables the workaround for the 764319 Cortex-A9 erratum.
771 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
778 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
781 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
791 This option enables the workaround for the 773022 Cortex-A15
801 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
803 - Cortex-A12 852422: Execution of a sequence of instructions might
805 any Cortex-A12 cores yet.
814 This option enables the workaround for the 821420 Cortex-A12
818 deadlock when the VMOV instructions are issued out-of-order.
824 This option enables the workaround for the 825619 Cortex-A12
827 and Device/Strongly-Ordered loads and stores might cause deadlock
833 This option enables the workaround for the 857271 Cortex-A12
841 This option enables the workaround for the 852421 Cortex-A17
851 - Cortex-A17 852423: Execution of a sequence of instructions might
853 any Cortex-A17 cores yet.
854 This is identical to Cortex-A12 erratum 852422. It is a separate
862 This option enables the workaround for the 857272 Cortex-A17 erratum.
864 This is identical to Cortex-A12 erratum 857271. It is a separate
896 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
906 This option should be selected by machines which have an SMP-
909 The only effect of this option is to make the SMP-related
913 bool "Symmetric Multi-Processing"
923 If you say N here, the kernel will run on uni- and multiprocessor
929 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
930 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
931 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
940 SMP kernels contain instructions which fail on non-SMP processors.
974 bool "Architected timer support"
978 This option enables support for the ARM architected timer
983 This options enables support for the ARM timer and watchdog unit
986 bool "Multi-Cluster Power Management"
990 for (multi-)cluster based systems, such as big.LITTLE based
1066 int "Maximum number of CPUs (2-32)"
1074 debugging is enabled, which uses half of the per-CPU fixmap
1078 bool "Support for hot-pluggable CPUs"
1091 implementing the PSCI specification for CPU-centric power
1103 prompt "Timer frequency"
1139 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1145 Thumb-2 mode.
1176 was dropped in gcc-4.8 and most distributions after ca. 2013.
1230 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1238 user-space 2nd level page tables to reside in high memory.
1241 bool "Enable privileged no-access"
1247 use-after-free bugs becoming an exploitable privilege escalation
1258 Enable use of CPU domains to implement privileged no-access.
1260 CPUs with low-vector mappings use a best-efforts implementation.
1268 Enable privileged no-access by disabling TTBR0 page table walks when
1290 Disabling this is usually safe for small single-platform
1314 address divisible by 4. On 32-bit ARM processors, these non-aligned
1317 correct operation of some network protocols. With an IP-only
1326 cores where a 8-word STM instruction give significantly higher
1333 However, if the CPU data cache is using a write-allocate mode,
1374 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1430 The physical address at which the ROM-able zImage is to be
1432 ROM-able zImage formats normally set this to a suitable
1442 for the ROM-able zImage which must be available while the
1445 Platforms which normally make use of ROM-able zImage formats
1498 Uses the command-line options passed by the boot loader instead of
1505 The command-line arguments provided by the boot loader will be
1516 architectures, you should supply some command-line options at build
1528 Uses the command-line options passed by the boot loader. If
1535 The command-line arguments provided by the boot loader will be
1544 command-line options your boot loader passes to the kernel.
1548 bool "Kernel Execute-In-Place from ROM"
1552 Execute-In-Place allows the kernel to run from non-volatile storage
1555 to RAM. Read-write sections, such as the data section and stack,
1612 will be determined at run-time, either by masking the current IP
1630 by UEFI firmware (such as non-volatile variables, realtime
1645 continue to boot on existing non-UEFI platforms.
1651 to be enabled much earlier than we do on ARM, which is non-trivial.
1683 Say Y to include 80-bit support in the kernel floating-point
1684 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1685 Note that gcc does not generate 80-bit operations by default,
1698 It is very simple, and approximately 3-6 times faster than NWFPE.
1706 bool "VFP-format floating point maths"
1712 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1739 default $(cc_can_link_user,-mlittle-endian) if CPU_LITTLE_ENDIAN
1740 default $(cc_can_link_user,-mbig-endian -mbe8) if CPU_ENDIAN_BE8
1741 default $(cc_can_link_user,-mbig-endian -mbe32) if CPU_ENDIAN_BE32
1745 default "-mlittle-endian" if CPU_LITTLE_ENDIAN
1746 default "-mbig-endian -mbe8" if CPU_ENDIAN_BE8
1747 default "-mbig-endian -mbe32" if CPU_ENDIAN_BE32