Lines Matching +full:non +full:- +full:default
1 # SPDX-License-Identifier: GPL-2.0
4 default y
47 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de
164 The ARM series is a line of low-power-consumption RISC chip designs
166 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
167 manufactured, but legacy ARM-based PC hardware remains popular in
175 relocations. The combined range is -/+ 256 MiB, which is usually
188 default 8
190 DMA mapping framework by default aligns all buffers to the smallest
222 default y
226 default y
242 default y
246 default y
265 default y
268 Patch phys-to-virt and virt-to-phys translation functions at
272 This can only be used with non-XIP MMU kernels where the base
296 default DRAM_BASE if !MMU
297 default 0x00000000 if ARCH_FOOTBRIDGE
298 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
299 default 0xa0000000 if ARCH_PXA
300 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
301 default 0
312 default 3 if ARM_LPAE
313 default 2
318 bool "MMU-based Paged Memory Management Support"
319 default y
321 Select if you want MMU-based virtualised addressing space
331 default 8
334 default 14 if PAGE_OFFSET=0x40000000
335 default 15 if PAGE_OFFSET=0x80000000
336 default 16
341 default y
356 # This is sorted alphabetically by mach-* pathname. However, plat-*
358 # plat- suffix) or along side the corresponding mach-* source.
360 source "arch/arm/mach-actions/Kconfig"
362 source "arch/arm/mach-alpine/Kconfig"
364 source "arch/arm/mach-artpec/Kconfig"
366 source "arch/arm/mach-aspeed/Kconfig"
368 source "arch/arm/mach-at91/Kconfig"
370 source "arch/arm/mach-axxia/Kconfig"
372 source "arch/arm/mach-bcm/Kconfig"
374 source "arch/arm/mach-berlin/Kconfig"
376 source "arch/arm/mach-clps711x/Kconfig"
378 source "arch/arm/mach-davinci/Kconfig"
380 source "arch/arm/mach-digicolor/Kconfig"
382 source "arch/arm/mach-dove/Kconfig"
384 source "arch/arm/mach-ep93xx/Kconfig"
386 source "arch/arm/mach-exynos/Kconfig"
388 source "arch/arm/mach-footbridge/Kconfig"
390 source "arch/arm/mach-gemini/Kconfig"
392 source "arch/arm/mach-highbank/Kconfig"
394 source "arch/arm/mach-hisi/Kconfig"
396 source "arch/arm/mach-imx/Kconfig"
398 source "arch/arm/mach-ixp4xx/Kconfig"
400 source "arch/arm/mach-keystone/Kconfig"
402 source "arch/arm/mach-lpc32xx/Kconfig"
404 source "arch/arm/mach-mediatek/Kconfig"
406 source "arch/arm/mach-meson/Kconfig"
408 source "arch/arm/mach-milbeaut/Kconfig"
410 source "arch/arm/mach-mmp/Kconfig"
412 source "arch/arm/mach-mstar/Kconfig"
414 source "arch/arm/mach-mv78xx0/Kconfig"
416 source "arch/arm/mach-mvebu/Kconfig"
418 source "arch/arm/mach-mxs/Kconfig"
420 source "arch/arm/mach-nomadik/Kconfig"
422 source "arch/arm/mach-npcm/Kconfig"
424 source "arch/arm/mach-omap1/Kconfig"
426 source "arch/arm/mach-omap2/Kconfig"
428 source "arch/arm/mach-orion5x/Kconfig"
430 source "arch/arm/mach-pxa/Kconfig"
432 source "arch/arm/mach-qcom/Kconfig"
434 source "arch/arm/mach-realtek/Kconfig"
436 source "arch/arm/mach-rpc/Kconfig"
438 source "arch/arm/mach-rockchip/Kconfig"
440 source "arch/arm/mach-s3c/Kconfig"
442 source "arch/arm/mach-s5pv210/Kconfig"
444 source "arch/arm/mach-sa1100/Kconfig"
446 source "arch/arm/mach-shmobile/Kconfig"
448 source "arch/arm/mach-socfpga/Kconfig"
450 source "arch/arm/mach-spear/Kconfig"
452 source "arch/arm/mach-sti/Kconfig"
454 source "arch/arm/mach-stm32/Kconfig"
456 source "arch/arm/mach-sunxi/Kconfig"
458 source "arch/arm/mach-tegra/Kconfig"
460 source "arch/arm/mach-ux500/Kconfig"
462 source "arch/arm/mach-versatile/Kconfig"
464 source "arch/arm/mach-vt8500/Kconfig"
466 source "arch/arm/mach-zynq/Kconfig"
468 # ARMv7-M architecture
477 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
486 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
487 with a range of available cores like Cortex-M3/M4/M7.
514 default y if PXA27x || PXA3xx || ARCH_MMP
520 source "arch/arm/Kconfig-nommu"
526 default y
538 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
541 Executing a SWP instruction to read-only memory does not set bit 11
559 This option enables the workaround for the 430973 Cortex-A8
562 same virtual address, whether due to self-modifying code or virtual
563 to physical address re-mapping, Cortex-A8 does not recover from the
564 stale interworking branch prediction. This results in Cortex-A8
569 available in non-secure mode.
576 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
583 register may not be available in non-secure mode and thus is not
592 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
596 workaround disables the write-allocate mode for the L2 cache via the
598 may not be available in non-secure mode and thus is not available on
607 This option enables the workaround for the 742230 Cortex-A9
611 the diagnostic register of the Cortex-A9 which causes the DMB
614 register may not be available in non-secure mode and thus is not
623 This option enables the workaround for the 742231 Cortex-A9
625 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
630 register of the Cortex-A9 which reduces the linefill issuing
632 diagnostics register may not be available in non-secure mode and thus
639 default y
641 This option enables the workaround for the 643719 Cortex-A9 (prior to
651 This option enables the workaround for the 720789 Cortex-A9 (prior to
664 This option enables the workaround for the 743622 Cortex-A9
666 optimisation in the Cortex-A9 Store Buffer may lead to data
668 register of the Cortex-A9 which disables the Store Buffer
672 may not be available in non-secure mode and thus is not available on a
680 This option enables the workaround for the 751472 Cortex-A9 (prior
686 not be available in non-secure mode and thus is not available on
694 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
697 can populate the micro-TLB with a stale entry which may be hit with
705 This option enables the workaround for the 754327 Cortex-A9 (prior to
713 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
718 hit-under-miss enabled). It sets the undocumented bit 31 in
720 register, thus disabling hit-under-miss without putting the
729 affecting Cortex-A9 MPCore with two or more processors (all
742 This option enables the workaround for the 764319 Cortex-A9 erratum.
753 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
760 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
763 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
773 This option enables the workaround for the 773022 Cortex-A15
783 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
785 - Cortex-A12 852422: Execution of a sequence of instructions might
787 any Cortex-A12 cores yet.
796 This option enables the workaround for the 821420 Cortex-A12
800 deadlock when the VMOV instructions are issued out-of-order.
806 This option enables the workaround for the 825619 Cortex-A12
809 and Device/Strongly-Ordered loads and stores might cause deadlock
815 This option enables the workaround for the 857271 Cortex-A12
823 This option enables the workaround for the 852421 Cortex-A17
833 - Cortex-A17 852423: Execution of a sequence of instructions might
835 any Cortex-A17 cores yet.
836 This is identical to Cortex-A12 erratum 852422. It is a separate
844 This option enables the workaround for the 857272 Cortex-A17 erratum.
846 This is identical to Cortex-A12 erratum 857271. It is a separate
878 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
888 This option should be selected by machines which have an SMP-
891 The only effect of this option is to make the SMP-related
895 bool "Symmetric Multi-Processing"
905 If you say N here, the kernel will run on uni- and multiprocessor
911 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
912 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
913 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
920 default y
922 SMP kernels contain instructions which fail on non-SMP processors.
944 default y
968 bool "Multi-Cluster Power Management"
972 for (multi-)cluster based systems, such as big.LITTLE based
980 to 2 clusters by default.
1012 default VMSPLIT_3G
1032 default PHYS_OFFSET if !MMU
1033 default 0x40000000 if VMSPLIT_1G
1034 default 0x80000000 if VMSPLIT_2G
1035 default 0xB0000000 if VMSPLIT_3G_OPT
1036 default 0xC0000000
1041 default 0x1f000000 if PAGE_OFFSET=0x40000000
1042 default 0x5f000000 if PAGE_OFFSET=0x80000000
1043 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1044 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1045 default 0xffffffff
1048 int "Maximum number of CPUs (2-32)"
1052 default "4"
1056 debugging is enabled, which uses half of the per-CPU fixmap
1060 bool "Support for hot-pluggable CPUs"
1073 implementing the PSCI specification for CPU-centric power
1080 default 128 if SOC_AT91RM9200
1081 default 0
1109 default HZ_FIXED if HZ_FIXED != 0
1110 default 100 if HZ_100
1111 default 200 if HZ_200
1112 default 250 if HZ_250
1113 default 300 if HZ_300
1114 default 500 if HZ_500
1115 default 1000
1121 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1123 default y if CPU_THUMBONLY
1127 Thumb-2 mode.
1134 default y
1152 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1172 (only for non "thumb" binaries). This option adds a tiny
1215 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1217 default y
1223 user-space 2nd level page tables to reside in high memory.
1226 bool "Enable privileged no-access"
1228 default y
1232 use-after-free bugs becoming an exploitable privilege escalation
1243 Enable use of CPU domains to implement privileged no-access.
1245 CPUs with low-vector mappings use a best-efforts implementation.
1253 Enable privileged no-access by disabling TTBR0 page table walks when
1264 default y
1275 Disabling this is usually safe for small single-platform
1280 default "11" if SOC_AM33XX
1281 default "8" if SA1111
1282 default "10"
1288 overriding the default setting when ability to allocate very
1299 address divisible by 4. On 32-bit ARM processors, these non-aligned
1302 correct operation of some network protocols. With an IP-only
1308 default y if CPU_FEROCEON
1311 cores where a 8-word STM instruction give significantly higher
1318 However, if the CPU data cache is using a write-allocate mode,
1358 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1364 default y
1391 default y
1409 default 0x0
1411 The physical address at which the ROM-able zImage is to be
1413 ROM-able zImage formats normally set this to a suitable
1420 default 0x0
1423 for the ROM-able zImage which must be available while the
1426 Platforms which normally make use of ROM-able zImage formats
1474 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1479 Uses the command-line options passed by the boot loader instead of
1486 The command-line arguments provided by the boot loader will be
1492 string "Default kernel command string"
1493 default ""
1497 architectures, you should supply some command-line options at build
1504 default CMDLINE_FROM_BOOTLOADER
1509 Uses the command-line options passed by the boot loader. If
1510 the boot loader doesn't provide any, the default kernel command
1516 The command-line arguments provided by the boot loader will be
1517 appended to the default kernel command string.
1520 bool "Always use the default kernel command string"
1522 Always use the default kernel command string, even if the boot
1525 command-line options your boot loader passes to the kernel.
1529 bool "Kernel Execute-In-Place from ROM"
1533 Execute-In-Place allows the kernel to run from non-volatile storage
1536 to RAM. Read-write sections, such as the data section and stack,
1553 default "0x00080000"
1576 default y
1589 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
1593 will be determined at run-time, either by masking the current IP
1611 by UEFI firmware (such as non-volatile variables, realtime
1620 default y
1626 continue to boot on existing non-UEFI platforms.
1632 to be enabled much earlier than we do on ARM, which is non-trivial.
1655 your machine has an FPA or floating point co-processor podule.
1664 Say Y to include 80-bit support in the kernel floating-point
1665 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1666 Note that gcc does not generate 80-bit operations by default,
1679 It is very simple, and approximately 3-6 times faster than NWFPE.
1687 bool "VFP-format floating point maths"
1693 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1701 default y if CPU_V7
1734 default y if ARCH_SUSPEND_POSSIBLE