Lines Matching +full:in +full:- +full:kernel
1 # SPDX-License-Identifier: GPL-2.0
162 The ARM series is a line of low-power-consumption RISC chip designs
164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
165 manufactured, but legacy ARM-based PC hardware remains popular in
173 relocations. The combined range is -/+ 256 MiB, which is usually
266 Patch phys-to-virt and virt-to-phys translation functions at
268 kernel in system memory.
270 This can only be used with non-XIP MMU kernels where the base
274 this feature (eg, building a kernel for a single machine) and
275 you need to shrink the kernel to the minimal size.
302 location of main memory in your system.
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
337 bool "Require kernel to be portable to multiple machines" if EXPERT
341 In general, all Arm machines can be supported in a single
342 kernel image, covering either Armv4/v5 or Armv6/v7.
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
356 # plat- suffix) or along side the corresponding mach-* source.
358 source "arch/arm/mach-actions/Kconfig"
360 source "arch/arm/mach-alpine/Kconfig"
362 source "arch/arm/mach-artpec/Kconfig"
364 source "arch/arm/mach-aspeed/Kconfig"
366 source "arch/arm/mach-at91/Kconfig"
368 source "arch/arm/mach-axxia/Kconfig"
370 source "arch/arm/mach-bcm/Kconfig"
372 source "arch/arm/mach-berlin/Kconfig"
374 source "arch/arm/mach-clps711x/Kconfig"
376 source "arch/arm/mach-davinci/Kconfig"
378 source "arch/arm/mach-digicolor/Kconfig"
380 source "arch/arm/mach-dove/Kconfig"
382 source "arch/arm/mach-ep93xx/Kconfig"
384 source "arch/arm/mach-exynos/Kconfig"
386 source "arch/arm/mach-footbridge/Kconfig"
388 source "arch/arm/mach-gemini/Kconfig"
390 source "arch/arm/mach-highbank/Kconfig"
392 source "arch/arm/mach-hisi/Kconfig"
394 source "arch/arm/mach-imx/Kconfig"
396 source "arch/arm/mach-ixp4xx/Kconfig"
398 source "arch/arm/mach-keystone/Kconfig"
400 source "arch/arm/mach-lpc32xx/Kconfig"
402 source "arch/arm/mach-mediatek/Kconfig"
404 source "arch/arm/mach-meson/Kconfig"
406 source "arch/arm/mach-milbeaut/Kconfig"
408 source "arch/arm/mach-mmp/Kconfig"
410 source "arch/arm/mach-mstar/Kconfig"
412 source "arch/arm/mach-mv78xx0/Kconfig"
414 source "arch/arm/mach-mvebu/Kconfig"
416 source "arch/arm/mach-mxs/Kconfig"
418 source "arch/arm/mach-nomadik/Kconfig"
420 source "arch/arm/mach-npcm/Kconfig"
422 source "arch/arm/mach-omap1/Kconfig"
424 source "arch/arm/mach-omap2/Kconfig"
426 source "arch/arm/mach-orion5x/Kconfig"
428 source "arch/arm/mach-pxa/Kconfig"
430 source "arch/arm/mach-qcom/Kconfig"
432 source "arch/arm/mach-realtek/Kconfig"
434 source "arch/arm/mach-rpc/Kconfig"
436 source "arch/arm/mach-rockchip/Kconfig"
438 source "arch/arm/mach-s3c/Kconfig"
440 source "arch/arm/mach-s5pv210/Kconfig"
442 source "arch/arm/mach-sa1100/Kconfig"
444 source "arch/arm/mach-shmobile/Kconfig"
446 source "arch/arm/mach-socfpga/Kconfig"
448 source "arch/arm/mach-spear/Kconfig"
450 source "arch/arm/mach-sti/Kconfig"
452 source "arch/arm/mach-stm32/Kconfig"
454 source "arch/arm/mach-sunxi/Kconfig"
456 source "arch/arm/mach-tegra/Kconfig"
458 source "arch/arm/mach-ux500/Kconfig"
460 source "arch/arm/mach-versatile/Kconfig"
462 source "arch/arm/mach-vt8500/Kconfig"
464 source "arch/arm/mach-zynq/Kconfig"
466 # ARMv7-M architecture
475 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
484 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
485 with a range of available cores like Cortex-M3/M4/M7.
518 source "arch/arm/Kconfig-nommu"
529 instructions. This sensitivity can result in a CPU hang scenario.
536 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
539 Executing a SWP instruction to read-only memory does not set bit 11
540 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
549 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
557 This option enables the workaround for the 430973 Cortex-A8
560 same virtual address, whether due to self-modifying code or virtual
561 to physical address re-mapping, Cortex-A8 does not recover from the
562 stale interworking branch prediction. This results in Cortex-A8
563 executing the new code sequence in the incorrect ARM or Thumb state.
566 Note that setting specific bits in the ACTLR register may not be
567 available in non-secure mode.
574 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
580 in the ACTLR register. Note that setting specific bits in the ACTLR
581 register may not be available in non-secure mode and thus is not
582 available on a multiplatform kernel. This should be applied by the
590 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
592 situation in which recent store transactions to the L2 cache are lost
594 workaround disables the write-allocate mode for the L2 cache via the
595 ACTLR register. Note that setting specific bits in the ACTLR register
596 may not be available in non-secure mode and thus is not available on
597 a multiplatform kernel. This should be applied by the bootloader
605 This option enables the workaround for the 742230 Cortex-A9
608 ordering of the two writes. This workaround sets a specific bit in
609 the diagnostic register of the Cortex-A9 which causes the DMB
611 the two writes. Note that setting specific bits in the diagnostics
612 register may not be available in non-secure mode and thus is not
613 available on a multiplatform kernel. This should be applied by the
617 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
621 This option enables the workaround for the 742231 Cortex-A9
623 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
624 accessing some data located in the same cache line, may get corrupted
627 accessing it. This workaround sets specific bits in the diagnostic
628 register of the Cortex-A9 which reduces the linefill issuing
629 capabilities of the processor. Note that setting specific bits in the
630 diagnostics register may not be available in non-secure mode and thus
631 is not available on a multiplatform kernel. This should be applied by
635 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
639 This option enables the workaround for the 643719 Cortex-A9 (prior to
649 This option enables the workaround for the 720789 Cortex-A9 (prior to
653 invalidated are not, resulting in an incoherency in the system page
658 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
662 This option enables the workaround for the 743622 Cortex-A9
664 optimisation in the Cortex-A9 Store Buffer may lead to data
665 corruption. This workaround sets a specific bit in the diagnostic
666 register of the Cortex-A9 which disables the Store Buffer
669 processor. Note that setting specific bits in the diagnostics register
670 may not be available in non-secure mode and thus is not available on a
671 multiplatform kernel. This should be applied by the bootloader instead.
678 This option enables the workaround for the 751472 Cortex-A9 (prior
682 potentially leading to corrupted entries in the cache or TLB.
683 Note that setting specific bits in the diagnostics register may
684 not be available in non-secure mode and thus is not available on
685 a multiplatform kernel. This should be applied by the bootloader
692 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
695 can populate the micro-TLB with a stale entry which may be hit with
696 the new ASID. This workaround places two dsb instructions in the mm
703 This option enables the workaround for the 754327 Cortex-A9 (prior to
711 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
716 hit-under-miss enabled). It sets the undocumented bit 31 in
717 the auxiliary control register and the FI bit in the control
718 register, thus disabling hit-under-miss without putting the
727 affecting Cortex-A9 MPCore with two or more processors (all
734 in the diagnostic control register of the SCU.
740 This option enables the workaround for the 764319 Cortex-A9 erratum.
744 from a privileged mode. This work around catches the exception in a
745 way the kernel does not stop execution.
751 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
752 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
758 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
761 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
763 option enables the Linux kernel workaround for this erratum
771 This option enables the workaround for the 773022 Cortex-A15
772 (up to r0p4) erratum. In certain rare sequences of code, the
781 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
782 instruction might deadlock. Fixed in r0p1.
783 - Cortex-A12 852422: Execution of a sequence of instructions might
784 lead to either a data corruption or a CPU deadlock. Not fixed in
785 any Cortex-A12 cores yet.
794 This option enables the workaround for the 821420 Cortex-A12
795 (all revs) erratum. In very rare timing conditions, a sequence
797 one is in the shadow of a branch or abort, can lead to a
798 deadlock when the VMOV instructions are issued out-of-order.
804 This option enables the workaround for the 825619 Cortex-A12
807 and Device/Strongly-Ordered loads and stores might cause deadlock
813 This option enables the workaround for the 857271 Cortex-A12
821 This option enables the workaround for the 852421 Cortex-A17
831 - Cortex-A17 852423: Execution of a sequence of instructions might
832 lead to either a data corruption or a CPU deadlock. Not fixed in
833 any Cortex-A17 cores yet.
834 This is identical to Cortex-A12 erratum 852422. It is a separate
842 This option enables the workaround for the 857272 Cortex-A17 erratum.
843 This erratum is not known to be fixed in any A17 revision.
844 This is identical to Cortex-A12 erratum 857271. It is a separate
873 each other, in program order.
876 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
881 menu "Kernel Features"
886 This option should be selected by machines which have an SMP-
889 The only effect of this option is to make the SMP-related
893 bool "Symmetric Multi-Processing"
903 If you say N here, the kernel will run on uni- and multiprocessor
905 you say Y here, the kernel will run on many, but not all,
906 uniprocessor machines. On a uniprocessor machine, the kernel
909 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
910 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
911 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
916 bool "Allow booting SMP kernel on uniprocessor systems"
920 SMP kernels contain instructions which fail on non-SMP processors.
921 Enabling this option allows the kernel to modify itself to make
966 bool "Multi-Cluster Power Management"
970 for (multi-)cluster based systems, such as big.LITTLE based
997 and a cluster of A7's in a big.LITTLE system.
1012 Select the desired split between kernel and user memory.
1018 bool "3G/1G user/kernel split"
1021 bool "3G/1G user/kernel split (for full 1G low memory)"
1023 bool "2G/2G user/kernel split"
1025 bool "1G/3G user/kernel split"
1046 int "Maximum number of CPUs (2-32)"
1052 The maximum number of CPUs that the kernel can support.
1054 debugging is enabled, which uses half of the per-CPU fixmap
1058 bool "Support for hot-pluggable CPUs"
1071 implementing the PSCI specification for CPU-centric power
1072 management operations described in ARM document number ARM DEN
1119 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1124 By enabling this option, the kernel will be compiled in
1125 Thumb-2 mode.
1140 Enabling this option allows the kernel to modify itself to
1148 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1152 This option allows for the kernel to be compiled using the latest
1158 option also changes the kernel syscall calling convention to
1165 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1171 in memory differs between the legacy ABI and the new ARM EABI
1173 overhead to all syscalls and produces a slightly larger kernel.
1182 UNPREDICTABLE (in fact it can be predicted that it won't work
1183 at all). If in doubt say N.
1202 and it has to accommodate user address space, kernel address
1205 memory can be "permanently mapped" by the kernel. The physical
1208 Depending on the selected kernel/user memory split, minimum
1210 option which should result in a slightly faster kernel.
1215 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1223 user-space 2nd level page tables to reside in high memory.
1226 bool "Enable privileged no-access"
1230 Increase kernel security by ensuring that normal kernel accesses
1232 use-after-free bugs becoming an exploitable privilege escalation
1243 Enable use of CPU domains to implement privileged no-access.
1245 CPUs with low-vector mappings use a best-efforts implementation.
1253 Enable privileged no-access by disabling TTBR0 page table walks when
1254 running in kernel mode.
1268 in the instructions themselves can be bounced via veneers in the
1269 module's PLT. This allows modules to be allocated in the generic
1275 Disabling this is usually safe for small single-platform
1284 The kernel page allocator limits the size of maximal physically
1299 address divisible by 4. On 32-bit ARM processors, these non-aligned
1300 fetch/store instructions will be emulated in software if you say
1302 correct operation of some network protocols. With an IP-only
1306 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1311 cores where a 8-word STM instruction give significantly higher
1314 A possible side effect is a slight increase in scheduling latency
1318 However, if the CPU data cache is using a write-allocate mode,
1324 This changes the kernel so it can modify itself when it is run
1333 accounting. Time spent executing other tasks in parallel with
1337 If in doubt, say N here.
1355 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1358 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1368 change at reboot time on SMP systems, and all tasks running in the
1369 kernel's address space are forced to use the same canary value for
1393 This is the traditional way of passing data to the kernel at boot
1396 to remove ATAGS support from your kernel binary.
1399 bool "Provide old way to pass kernel parameters"
1402 This was deprecated in 2001 and announced to live on for 5 years.
1405 # Compressed boot loader in ROM. Yes, we really want to ask about
1406 # TEXT and BSS so we preserve their values in the config files.
1411 The physical address at which the ROM-able zImage is to be
1412 placed in the target. Platforms which normally make use of
1413 ROM-able zImage formats normally set this to a suitable
1414 value in their defconfig file.
1422 The base address of an area of read/write memory in the target
1423 for the ROM-able zImage which must be available while the
1425 entire decompressed kernel plus an additional 128 KiB.
1426 Platforms which normally make use of ROM-able zImage formats
1427 normally set this to a suitable value in their defconfig file.
1432 bool "Compressed boot loader in ROM/flash"
1436 Say Y here if you intend to execute your compressed kernel image
1451 Beware that there is very little in terms of protection against
1452 this option being confused by leftover garbage in memory that might
1454 to zImage. Do not leave this option active in a production kernel
1465 the kernel cmdline string, etc. Such information is dynamically
1466 provided by the bootloader and can't always be stored in a static
1467 DTB. To allow a device tree enabled kernel to be used with such
1472 prompt "Kernel command line type"
1477 bool "Use bootloader kernel arguments if available"
1479 Uses the command-line options passed by the boot loader instead of
1484 bool "Extend with bootloader kernel arguments"
1486 The command-line arguments provided by the boot loader will be
1492 string "Default kernel command string"
1496 for the boot loader to pass arguments to the kernel. For these
1497 architectures, you should supply some command-line options at build
1502 prompt "Kernel command line type"
1507 bool "Use bootloader kernel arguments if available"
1509 Uses the command-line options passed by the boot loader. If
1510 the boot loader doesn't provide any, the default kernel command
1511 string provided in CMDLINE will be used.
1514 bool "Extend bootloader kernel arguments"
1516 The command-line arguments provided by the boot loader will be
1517 appended to the default kernel command string.
1520 bool "Always use the default kernel command string"
1522 Always use the default kernel command string, even if the boot
1523 loader passes other arguments to the kernel.
1525 command-line options your boot loader passes to the kernel.
1529 bool "Kernel Execute-In-Place from ROM"
1533 Execute-In-Place allows the kernel to run from non-volatile storage
1535 space since the text section of the kernel is not loaded from flash
1536 to RAM. Read-write sections, such as the data section and stack,
1537 are still copied to RAM. The XIP kernel is not compressed since
1539 store it. The flash address used to link the kernel object files,
1542 store the kernel image depending on your own flash memory usage.
1545 "make zImage" or "make Image". The final kernel binary to put in
1551 hex "XIP Kernel Physical Location"
1555 This is the physical address in your flash memory the kernel will
1560 bool "Store kernel .data section compressed in ROM"
1564 Before the kernel is actually executed, its .data section has to be
1566 in compressed form and decompressed to RAM rather than merely being
1574 bool "Export atags in procfs"
1578 Should the atags used to boot the kernel be exported in an "atags"
1579 file in procfs. Useful with kexec.
1588 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
1591 ZRELADDR is the physical address where the decompressed kernel
1593 will be determined at run-time, either by masking the current IP
1594 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1595 This assumes the zImage being placed in the first 128MB from
1611 by UEFI firmware (such as non-volatile variables, realtime
1613 allow the kernel to be booted as an EFI application. This
1625 However, even with this option, the resultant kernel should
1626 continue to boot on existing non-UEFI platforms.
1632 to be enabled much earlier than we do on ARM, which is non-trivial.
1652 Say Y to include the NWFPE floating point emulator in the kernel.
1655 your machine has an FPA or floating point co-processor podule.
1658 early in the bootup.
1664 Say Y to include 80-bit support in the kernel floating-point
1665 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1666 Note that gcc does not generate 80-bit operations by default,
1667 so in most cases this option only enlarges the size of the
1676 Say Y here to include the FAST floating point emulator in the kernel.
1679 It is very simple, and approximately 3-6 times faster than NWFPE.
1687 bool "VFP-format floating point maths"
1690 Say Y to include VFP support code in the kernel. This is needed
1693 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1711 bool "Support for NEON in kernel mode"
1714 Say Y to include support for NEON in kernel mode.
1720 source "kernel/power/Kconfig"