Lines Matching full:erratum

549 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
558 	  r1p* erratum. If a code sequence containing an ARM/Thumb
575 	  erratum. For very specific sequences of memory operations, it is
591 	  erratum. Any asynchronous access to the L2 cache may encounter a
606 	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
622 	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
640 	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
650 	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
652 	  As a consequence of this erratum, some TLB entries which should be
663 	  (r2p*) erratum. Under very rare conditions, a faulty
679 	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
693 	  r3p*) erratum. A speculative memory access may cause a page table walk
704 	  r2p0) erratum. The Store Buffer does not have any automatic draining
715 	  r0p2 erratum (possible cache data corruption with
726 	  This option enables the workaround for erratum 764369
740 	  This option enables the workaround for the 764319 Cortex-A9 erratum.
752 	 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
763 	  option enables the Linux kernel workaround for this erratum
772 	  (up to r0p4) erratum. In certain rare sequences of code, the
774 	  workaround disables the loop buffer to avoid the erratum.
795 	  (all revs) erratum. In very rare timing conditions, a sequence
805 	  (all revs) erratum. Within rare timing constraints, executing a
814 	  (all revs) erratum. Under very rare timing conditions, the CPU might
822 	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
834 	  This is identical to Cortex-A12 erratum 852422.  It is a separate
835 	  config option from the A12 erratum due to the way errata are checked
842 	  This option enables the workaround for the 857272 Cortex-A17 erratum.
843 	  This erratum is not known to be fixed in any A17 revision.
844 	  This is identical to Cortex-A12 erratum 857271.  It is a separate
845 	  config option from the A12 erratum due to the way errata are checked
874 	  However, because of this erratum, an L2 set/way cache maintenance