Lines Matching full:errata

345 	  specific physical addresses or enable errata workarounds that may
522 	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
536 	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
545 	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
554 	bool "ARM errata: Stale prediction on replaced interworking branch"
570 	bool "ARM errata: Processor deadlock when a false hazard is created"
586 	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
601 	bool "ARM errata: DMB operation may be faulty"
617 	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
635 	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
646 	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
658 	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
674 	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
689 	bool "ARM errata: possible faulty MMU translations following an ASID switch"
700 	bool "ARM errata: no automatic Store Buffer drain"
711 	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
723 	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
737 	bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
748        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
758 	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
768 	bool "ARM errata: incorrect instructions may be executed from loop buffer"
777 	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
786 	  This workaround for all both errata involves setting bit[12] of the
791 	bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
801 	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
810 	bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
818 	bool "ARM errata: A17: DMB ST might fail to create order between stores"
827 	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
835 	  config option from the A12 erratum due to the way errata are checked
839 	bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
845 	  config option from the A12 erratum due to the way errata are checked
868 	bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
876 	  This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,