Lines Matching +full:default +full:- +full:on
1 # SPDX-License-Identifier: GPL-2.0
4 default y
162 The ARM series is a line of low-power-consumption RISC chip designs
164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
165 manufactured, but legacy ARM-based PC hardware remains popular in
173 relocations. The combined range is -/+ 256 MiB, which is usually
186 default 8
188 DMA mapping framework by default aligns all buffers to the smallest
220 default y
224 default y
240 default y
244 default y
263 default y
264 depends on MMU
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
293 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
294 default DRAM_BASE if !MMU
295 default 0x00000000 if ARCH_FOOTBRIDGE
296 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
297 default 0xa0000000 if ARCH_PXA
298 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
299 default 0
306 depends on BUG
310 default 3 if ARM_LPAE
311 default 2
316 bool "MMU-based Paged Memory Management Support"
317 default y
319 Select if you want MMU-based virtualised addressing space
329 default 8
332 default 14 if PAGE_OFFSET=0x40000000
333 default 15 if PAGE_OFFSET=0x80000000
334 default 16
338 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
339 default y
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
356 # plat- suffix) or along side the corresponding mach-* source.
358 source "arch/arm/mach-actions/Kconfig"
360 source "arch/arm/mach-alpine/Kconfig"
362 source "arch/arm/mach-artpec/Kconfig"
364 source "arch/arm/mach-aspeed/Kconfig"
366 source "arch/arm/mach-at91/Kconfig"
368 source "arch/arm/mach-axxia/Kconfig"
370 source "arch/arm/mach-bcm/Kconfig"
372 source "arch/arm/mach-berlin/Kconfig"
374 source "arch/arm/mach-clps711x/Kconfig"
376 source "arch/arm/mach-davinci/Kconfig"
378 source "arch/arm/mach-digicolor/Kconfig"
380 source "arch/arm/mach-dove/Kconfig"
382 source "arch/arm/mach-ep93xx/Kconfig"
384 source "arch/arm/mach-exynos/Kconfig"
386 source "arch/arm/mach-footbridge/Kconfig"
388 source "arch/arm/mach-gemini/Kconfig"
390 source "arch/arm/mach-highbank/Kconfig"
392 source "arch/arm/mach-hisi/Kconfig"
394 source "arch/arm/mach-imx/Kconfig"
396 source "arch/arm/mach-ixp4xx/Kconfig"
398 source "arch/arm/mach-keystone/Kconfig"
400 source "arch/arm/mach-lpc32xx/Kconfig"
402 source "arch/arm/mach-mediatek/Kconfig"
404 source "arch/arm/mach-meson/Kconfig"
406 source "arch/arm/mach-milbeaut/Kconfig"
408 source "arch/arm/mach-mmp/Kconfig"
410 source "arch/arm/mach-mstar/Kconfig"
412 source "arch/arm/mach-mv78xx0/Kconfig"
414 source "arch/arm/mach-mvebu/Kconfig"
416 source "arch/arm/mach-mxs/Kconfig"
418 source "arch/arm/mach-nomadik/Kconfig"
420 source "arch/arm/mach-npcm/Kconfig"
422 source "arch/arm/mach-omap1/Kconfig"
424 source "arch/arm/mach-omap2/Kconfig"
426 source "arch/arm/mach-orion5x/Kconfig"
428 source "arch/arm/mach-pxa/Kconfig"
430 source "arch/arm/mach-qcom/Kconfig"
432 source "arch/arm/mach-realtek/Kconfig"
434 source "arch/arm/mach-rpc/Kconfig"
436 source "arch/arm/mach-rockchip/Kconfig"
438 source "arch/arm/mach-s3c/Kconfig"
440 source "arch/arm/mach-s5pv210/Kconfig"
442 source "arch/arm/mach-sa1100/Kconfig"
444 source "arch/arm/mach-shmobile/Kconfig"
446 source "arch/arm/mach-socfpga/Kconfig"
448 source "arch/arm/mach-spear/Kconfig"
450 source "arch/arm/mach-sti/Kconfig"
452 source "arch/arm/mach-stm32/Kconfig"
454 source "arch/arm/mach-sunxi/Kconfig"
456 source "arch/arm/mach-tegra/Kconfig"
458 source "arch/arm/mach-ux500/Kconfig"
460 source "arch/arm/mach-versatile/Kconfig"
462 source "arch/arm/mach-vt8500/Kconfig"
464 source "arch/arm/mach-zynq/Kconfig"
466 # ARMv7-M architecture
469 depends on ARM_SINGLE_ARMV7M
475 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
480 depends on ARM_SINGLE_ARMV7M
484 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
485 with a range of available cores like Cortex-M3/M4/M7.
511 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
512 default y if PXA27x || PXA3xx || ARCH_MMP
515 running on a CPU that supports it.
518 source "arch/arm/Kconfig-nommu"
523 depends on CPU_PJ4B && MACH_ARMADA_370
524 default y
536 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
537 depends on CPU_V6
539 Executing a SWP instruction to read-only memory does not set bit 11
540 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
546 depends on CPU_V6 || CPU_V6K
554 bool "ARM errata: Stale prediction on replaced interworking branch"
555 depends on CPU_V7
557 This option enables the workaround for the 430973 Cortex-A8
560 same virtual address, whether due to self-modifying code or virtual
561 to physical address re-mapping, Cortex-A8 does not recover from the
562 stale interworking branch prediction. This results in Cortex-A8
567 available in non-secure mode.
571 depends on CPU_V7
572 depends on !ARCH_MULTIPLATFORM
574 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
581 register may not be available in non-secure mode and thus is not
582 available on a multiplatform kernel. This should be applied by the
587 depends on CPU_V7
588 depends on !ARCH_MULTIPLATFORM
590 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
594 workaround disables the write-allocate mode for the L2 cache via the
596 may not be available in non-secure mode and thus is not available on
602 depends on CPU_V7 && SMP
603 depends on !ARCH_MULTIPLATFORM
605 This option enables the workaround for the 742230 Cortex-A9
609 the diagnostic register of the Cortex-A9 which causes the DMB
612 register may not be available in non-secure mode and thus is not
613 available on a multiplatform kernel. This should be applied by the
618 depends on CPU_V7 && SMP
619 depends on !ARCH_MULTIPLATFORM
621 This option enables the workaround for the 742231 Cortex-A9
623 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
628 register of the Cortex-A9 which reduces the linefill issuing
630 diagnostics register may not be available in non-secure mode and thus
631 is not available on a multiplatform kernel. This should be applied by
636 depends on CPU_V7 && SMP
637 default y
639 This option enables the workaround for the 643719 Cortex-A9 (prior to
640 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
647 depends on CPU_V7
649 This option enables the workaround for the 720789 Cortex-A9 (prior to
659 depends on CPU_V7
660 depends on !ARCH_MULTIPLATFORM
662 This option enables the workaround for the 743622 Cortex-A9
664 optimisation in the Cortex-A9 Store Buffer may lead to data
666 register of the Cortex-A9 which disables the Store Buffer
668 visible impact on the overall performance or power consumption of the
670 may not be available in non-secure mode and thus is not available on a
675 depends on CPU_V7
676 depends on !ARCH_MULTIPLATFORM
678 This option enables the workaround for the 751472 Cortex-A9 (prior
684 not be available in non-secure mode and thus is not available on
690 depends on CPU_V7
692 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
695 can populate the micro-TLB with a stale entry which may be hit with
701 depends on CPU_V7 && SMP
703 This option enables the workaround for the 754327 Cortex-A9 (prior to
711 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
712 depends on CPU_V6
716 hit-under-miss enabled). It sets the undocumented bit 31 in
718 register, thus disabling hit-under-miss without putting the
724 depends on CPU_V7 && SMP
727 affecting Cortex-A9 MPCore with two or more processors (all
738 depends on CPU_V7
740 This option enables the workaround for the 764319 Cortex-A9 erratum.
749 depends on CPU_V7
751 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
755 an abort may occur on cache maintenance.
758 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
759 depends on CPU_V7 && SMP
761 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
769 depends on CPU_V7
771 This option enables the workaround for the 773022 Cortex-A15
778 depends on CPU_V7
781 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
783 - Cortex-A12 852422: Execution of a sequence of instructions might
785 any Cortex-A12 cores yet.
792 depends on CPU_V7
794 This option enables the workaround for the 821420 Cortex-A12
798 deadlock when the VMOV instructions are issued out-of-order.
802 depends on CPU_V7
804 This option enables the workaround for the 825619 Cortex-A12
807 and Device/Strongly-Ordered loads and stores might cause deadlock
811 depends on CPU_V7
813 This option enables the workaround for the 857271 Cortex-A12
819 depends on CPU_V7
821 This option enables the workaround for the 852421 Cortex-A17
828 depends on CPU_V7
831 - Cortex-A17 852423: Execution of a sequence of instructions might
833 any Cortex-A17 cores yet.
834 This is identical to Cortex-A12 erratum 852422. It is a separate
840 depends on CPU_V7
842 This option enables the workaround for the 857272 Cortex-A17 erratum.
844 This is identical to Cortex-A12 erratum 857271. It is a separate
857 Find out whether you have ISA slots on your motherboard. ISA is the
869 depends on CPU_V7
876 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
886 This option should be selected by machines which have an SMP-
889 The only effect of this option is to make the SMP-related
893 bool "Symmetric Multi-Processing"
894 depends on CPU_V6K || CPU_V7
895 depends on HAVE_SMP
896 depends on MMU || ARM_MPU
903 If you say N here, the kernel will run on uni- and multiprocessor
905 you say Y here, the kernel will run on many, but not all,
906 uniprocessor machines. On a uniprocessor machine, the kernel
909 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
910 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
911 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
916 bool "Allow booting SMP kernel on uniprocessor systems"
917 depends on SMP && MMU
918 default y
920 SMP kernels contain instructions which fail on non-SMP processors.
930 depends on CPU_32v6K && !CPU_V6
939 depends on SMP && CPU_V7
942 default y
955 depends on CPU_V7
966 bool "Multi-Cluster Power Management"
967 depends on CPU_V7 && SMP
970 for (multi-)cluster based systems, such as big.LITTLE based
975 depends on MCPM
978 to 2 clusters by default.
984 depends on CPU_V7 && SMP
992 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1001 depends on BL_SWITCHER && DEBUG_KERNEL
1009 depends on MMU
1010 default VMSPLIT_3G
1020 depends on !ARM_LPAE
1030 default PHYS_OFFSET if !MMU
1031 default 0x40000000 if VMSPLIT_1G
1032 default 0x80000000 if VMSPLIT_2G
1033 default 0xB0000000 if VMSPLIT_3G_OPT
1034 default 0xC0000000
1038 depends on KASAN
1039 default 0x1f000000 if PAGE_OFFSET=0x40000000
1040 default 0x5f000000 if PAGE_OFFSET=0x80000000
1041 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1042 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1043 default 0xffffffff
1046 int "Maximum number of CPUs (2-32)"
1049 depends on SMP
1050 default "4"
1054 debugging is enabled, which uses half of the per-CPU fixmap
1058 bool "Support for hot-pluggable CPUs"
1059 depends on SMP
1062 Say Y here to experiment with turning CPUs off and on. CPUs
1067 depends on HAVE_ARM_SMCCC
1071 implementing the PSCI specification for CPU-centric power
1073 0022A ("Power State Coordination Interface System Software on
1078 default 128 if SOC_AT91RM9200
1079 default 0
1082 depends on HZ_FIXED = 0
1107 default HZ_FIXED if HZ_FIXED != 0
1108 default 100 if HZ_100
1109 default 200 if HZ_200
1110 default 250 if HZ_250
1111 default 300 if HZ_300
1112 default 500 if HZ_500
1113 default 1000
1119 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1120 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1121 default y if CPU_THUMBONLY
1125 Thumb-2 mode.
1131 depends on CPU_32v7
1132 default y
1135 __aeabi_uidiv() when it needs to perform division on signed
1143 it is running on supports them. Typically this will be faster
1150 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1166 depends on AEABI && !THUMB2_KERNEL
1197 depends on MMU
1208 Depending on the selected kernel/user memory split, minimum
1215 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1216 depends on HIGHMEM
1217 default y
1223 user-space 2nd level page tables to reside in high memory.
1226 bool "Enable privileged no-access"
1227 depends on MMU
1228 default y
1232 use-after-free bugs becoming an exploitable privilege escalation
1241 depends on ARM_PAN && !ARM_LPAE
1243 Enable use of CPU domains to implement privileged no-access.
1245 CPUs with low-vector mappings use a best-efforts implementation.
1251 depends on ARM_PAN && ARM_LPAE
1253 Enable privileged no-access by disabling TTBR0 page table walks when
1258 depends on ARM_PMU
1262 depends on MODULES
1264 default y
1275 Disabling this is usually safe for small single-platform
1280 default "11" if SOC_AM33XX
1281 default "8" if SA1111
1282 default "10"
1288 overriding the default setting when ability to allocate very
1298 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1299 address divisible by 4. On 32-bit ARM processors, these non-aligned
1302 correct operation of some network protocols. With an IP-only
1307 depends on MMU
1308 default y if CPU_FEROCEON
1311 cores where a 8-word STM instruction give significantly higher
1318 However, if the CPU data cache is using a write-allocate mode,
1341 depends on XEN
1344 bool "Xen guest support on ARM"
1345 depends on ARM && AEABI && OF
1346 depends on CPU_V7 && !CPU_V6
1347 depends on !GENERIC_ATOMIC64
1348 depends on MMU
1355 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1358 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1362 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1363 depends on CC_HAVE_STACKPROTECTOR_TLS
1364 default y
1368 change at reboot time on SMP systems, and all tasks running in the
1391 default y
1394 time. If you are solely relying on the flattened device tree (or
1400 depends on ATAGS
1402 This was deprecated in 2001 and announced to live on for 5 years.
1409 default 0x0
1411 The physical address at which the ROM-able zImage is to be
1413 ROM-able zImage formats normally set this to a suitable
1420 default 0x0
1423 for the ROM-able zImage which must be available while the
1426 Platforms which normally make use of ROM-able zImage formats
1433 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1434 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1441 depends on OF
1461 depends on ARM_APPENDED_DTB
1473 depends on ARM_ATAG_DTB_COMPAT
1474 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1479 Uses the command-line options passed by the boot loader instead of
1486 The command-line arguments provided by the boot loader will be
1492 string "Default kernel command string"
1493 default ""
1495 On some architectures (e.g. CATS), there is currently no way
1497 architectures, you should supply some command-line options at build
1503 depends on CMDLINE != ""
1504 default CMDLINE_FROM_BOOTLOADER
1509 Uses the command-line options passed by the boot loader. If
1510 the boot loader doesn't provide any, the default kernel command
1516 The command-line arguments provided by the boot loader will be
1517 appended to the default kernel command string.
1520 bool "Always use the default kernel command string"
1522 Always use the default kernel command string, even if the boot
1525 command-line options your boot loader passes to the kernel.
1529 bool "Kernel Execute-In-Place from ROM"
1530 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1531 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP
1533 Execute-In-Place allows the kernel to run from non-volatile storage
1536 to RAM. Read-write sections, such as the data section and stack,
1542 store the kernel image depending on your own flash memory usage.
1552 depends on XIP_KERNEL
1553 default "0x00080000"
1556 be linked for and stored to. This address is dependent on your
1561 depends on XIP_KERNEL
1575 depends on ATAGS && KEXEC
1576 default y
1589 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
1593 will be determined at run-time, either by masking the current IP
1603 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1611 by UEFI firmware (such as non-volatile variables, realtime
1614 is only useful for kernels that may run on systems that have
1619 depends on EFI
1620 default y
1624 This option is only useful on systems that have UEFI firmware.
1626 continue to boot on existing non-UEFI platforms.
1632 to be enabled much earlier than we do on ARM, which is non-trivial.
1650 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1655 your machine has an FPA or floating point co-processor podule.
1662 depends on FPE_NWFPE
1664 Say Y to include 80-bit support in the kernel floating-point
1665 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1666 Note that gcc does not generate 80-bit operations by default,
1674 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1679 It is very simple, and approximately 3-6 times faster than NWFPE.
1687 bool "VFP-format floating point maths"
1688 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1693 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1700 depends on VFP
1701 default y if CPU_V7
1705 depends on VFPv3 && CPU_V7
1712 depends on NEON && AEABI
1723 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1729 depends on ARCH_SUSPEND_POSSIBLE
1733 depends on MMU
1734 default y if ARCH_SUSPEND_POSSIBLE