Lines Matching full:deadlock
575 bool "ARM errata: Processor deadlock when a false hazard is created"
583 hazard might then cause a processor deadlock. The workaround enables
753 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
759 to deadlock. This workaround puts DSB before executing ISB if
782 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
787 instruction might deadlock. Fixed in r0p1.
789 lead to either a data corruption or a CPU deadlock. Not fixed in
803 deadlock when the VMOV instructions are issued out-of-order.
806 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
812 and Device/Strongly-Ordered loads and stores might cause deadlock
815 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
832 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
837 lead to either a data corruption or a CPU deadlock. Not fixed in
844 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"