Lines Matching +full:bootloader +full:- +full:config
1 # SPDX-License-Identifier: GPL-2.0
2 config ARM
159 The ARM series is a line of low-power-consumption RISC chip designs
161 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
162 manufactured, but legacy ARM-based PC hardware remains popular in
166 config ARM_HAS_GROUP_RELOCS
173 supported in LLD until version 14. The combined range is -/+ 256 MiB,
177 config ARM_DMA_USE_IOMMU
183 config ARM_DMA_IOMMU_ALIGNMENT
202 config SYS_SUPPORTS_APM_EMULATION
205 config HAVE_TCM
209 config HAVE_PROC_CPU
212 config NO_IOPORT_MAP
215 config SBUS
218 config STACKTRACE_SUPPORT
222 config LOCKDEP_SUPPORT
226 config ARCH_HAS_ILOG2_U32
229 config ARCH_HAS_ILOG2_U64
232 config ARCH_HAS_BANDGAP
235 config FIX_EARLYCON_MEM
238 config GENERIC_HWEIGHT
242 config GENERIC_CALIBRATE_DELAY
246 config ARCH_MAY_HAVE_PC_FDC
249 config ARCH_SUPPORTS_UPROBES
252 config GENERIC_ISA_DMA
255 config FIQ
258 config ARCH_MTD_XIP
261 config ARM_PATCH_PHYS_VIRT
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
277 config NEED_MACH_IO_H
284 config NEED_MACH_MEMORY_H
291 config PHYS_OFFSET
304 config GENERIC_BUG
308 config PGTABLE_LEVELS
315 config MMU
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
322 config ARM_SINGLE_ARMV7M
328 config ARCH_MMAP_RND_BITS_MIN
331 config ARCH_MMAP_RND_BITS_MAX
336 config ARCH_MULTIPLATFORM
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
356 # plat- suffix) or along side the corresponding mach-* source.
358 source "arch/arm/mach-actions/Kconfig"
360 source "arch/arm/mach-alpine/Kconfig"
362 source "arch/arm/mach-artpec/Kconfig"
364 source "arch/arm/mach-aspeed/Kconfig"
366 source "arch/arm/mach-at91/Kconfig"
368 source "arch/arm/mach-axxia/Kconfig"
370 source "arch/arm/mach-bcm/Kconfig"
372 source "arch/arm/mach-berlin/Kconfig"
374 source "arch/arm/mach-clps711x/Kconfig"
376 source "arch/arm/mach-davinci/Kconfig"
378 source "arch/arm/mach-digicolor/Kconfig"
380 source "arch/arm/mach-dove/Kconfig"
382 source "arch/arm/mach-ep93xx/Kconfig"
384 source "arch/arm/mach-exynos/Kconfig"
386 source "arch/arm/mach-footbridge/Kconfig"
388 source "arch/arm/mach-gemini/Kconfig"
390 source "arch/arm/mach-highbank/Kconfig"
392 source "arch/arm/mach-hisi/Kconfig"
394 source "arch/arm/mach-hpe/Kconfig"
396 source "arch/arm/mach-imx/Kconfig"
398 source "arch/arm/mach-ixp4xx/Kconfig"
400 source "arch/arm/mach-keystone/Kconfig"
402 source "arch/arm/mach-lpc32xx/Kconfig"
404 source "arch/arm/mach-mediatek/Kconfig"
406 source "arch/arm/mach-meson/Kconfig"
408 source "arch/arm/mach-milbeaut/Kconfig"
410 source "arch/arm/mach-mmp/Kconfig"
412 source "arch/arm/mach-mstar/Kconfig"
414 source "arch/arm/mach-mv78xx0/Kconfig"
416 source "arch/arm/mach-mvebu/Kconfig"
418 source "arch/arm/mach-mxs/Kconfig"
420 source "arch/arm/mach-nomadik/Kconfig"
422 source "arch/arm/mach-npcm/Kconfig"
424 source "arch/arm/mach-omap1/Kconfig"
426 source "arch/arm/mach-omap2/Kconfig"
428 source "arch/arm/mach-orion5x/Kconfig"
430 source "arch/arm/mach-pxa/Kconfig"
432 source "arch/arm/mach-qcom/Kconfig"
434 source "arch/arm/mach-realtek/Kconfig"
436 source "arch/arm/mach-rpc/Kconfig"
438 source "arch/arm/mach-rockchip/Kconfig"
440 source "arch/arm/mach-s3c/Kconfig"
442 source "arch/arm/mach-s5pv210/Kconfig"
444 source "arch/arm/mach-sa1100/Kconfig"
446 source "arch/arm/mach-shmobile/Kconfig"
448 source "arch/arm/mach-socfpga/Kconfig"
450 source "arch/arm/mach-spear/Kconfig"
452 source "arch/arm/mach-sti/Kconfig"
454 source "arch/arm/mach-stm32/Kconfig"
456 source "arch/arm/mach-sunxi/Kconfig"
458 source "arch/arm/mach-tegra/Kconfig"
460 source "arch/arm/mach-ux500/Kconfig"
462 source "arch/arm/mach-versatile/Kconfig"
464 source "arch/arm/mach-vt8500/Kconfig"
466 source "arch/arm/mach-zynq/Kconfig"
468 # ARMv7-M architecture
469 config ARCH_LPC18XX
477 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
480 config ARCH_MPS2
486 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
487 with a range of available cores like Cortex-M3/M4/M7.
493 config ARCH_ACORN
496 config PLAT_ORION
502 config PLAT_ORION_LEGACY
506 config PLAT_VERSATILE
511 config IWMMXT
520 source "arch/arm/Kconfig-nommu"
523 config PJ4B_ERRATA_4742
537 config ARM_ERRATA_326103
538 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
541 Executing a SWP instruction to read-only memory does not set bit 11
546 config ARM_ERRATA_411920
555 config ARM_ERRATA_430973
559 This option enables the workaround for the 430973 Cortex-A8
562 same virtual address, whether due to self-modifying code or virtual
563 to physical address re-mapping, Cortex-A8 does not recover from the
564 stale interworking branch prediction. This results in Cortex-A8
569 available in non-secure mode.
571 config ARM_ERRATA_458693
576 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
583 register may not be available in non-secure mode and thus is not
585 bootloader instead.
587 config ARM_ERRATA_460075
592 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
596 workaround disables the write-allocate mode for the L2 cache via the
598 may not be available in non-secure mode and thus is not available on
599 a multiplatform kernel. This should be applied by the bootloader
602 config ARM_ERRATA_742230
607 This option enables the workaround for the 742230 Cortex-A9
611 the diagnostic register of the Cortex-A9 which causes the DMB
614 register may not be available in non-secure mode and thus is not
616 bootloader instead.
618 config ARM_ERRATA_742231
623 This option enables the workaround for the 742231 Cortex-A9
625 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
630 register of the Cortex-A9 which reduces the linefill issuing
632 diagnostics register may not be available in non-secure mode and thus
634 the bootloader instead.
636 config ARM_ERRATA_643719
641 This option enables the workaround for the 643719 Cortex-A9 (prior to
647 config ARM_ERRATA_720789
651 This option enables the workaround for the 720789 Cortex-A9 (prior to
659 config ARM_ERRATA_743622
664 This option enables the workaround for the 743622 Cortex-A9
666 optimisation in the Cortex-A9 Store Buffer may lead to data
668 register of the Cortex-A9 which disables the Store Buffer
672 may not be available in non-secure mode and thus is not available on a
673 multiplatform kernel. This should be applied by the bootloader instead.
675 config ARM_ERRATA_751472
680 This option enables the workaround for the 751472 Cortex-A9 (prior
686 not be available in non-secure mode and thus is not available on
687 a multiplatform kernel. This should be applied by the bootloader
690 config ARM_ERRATA_754322
694 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
697 can populate the micro-TLB with a stale entry which may be hit with
701 config ARM_ERRATA_754327
705 This option enables the workaround for the 754327 Cortex-A9 (prior to
712 config ARM_ERRATA_364296
713 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
718 hit-under-miss enabled). It sets the undocumented bit 31 in
720 register, thus disabling hit-under-miss without putting the
724 config ARM_ERRATA_764369
729 affecting Cortex-A9 MPCore with two or more processors (all
738 config ARM_ERRATA_764319
742 This option enables the workaround for the 764319 Cortex-A9 erratum.
749 config ARM_ERRATA_775420
753 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
759 config ARM_ERRATA_798181
760 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
763 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
769 config ARM_ERRATA_773022
773 This option enables the workaround for the 773022 Cortex-A15
778 config ARM_ERRATA_818325_852422
783 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
785 - Cortex-A12 852422: Execution of a sequence of instructions might
787 any Cortex-A12 cores yet.
792 config ARM_ERRATA_821420
796 This option enables the workaround for the 821420 Cortex-A12
800 deadlock when the VMOV instructions are issued out-of-order.
802 config ARM_ERRATA_825619
806 This option enables the workaround for the 825619 Cortex-A12
809 and Device/Strongly-Ordered loads and stores might cause deadlock
811 config ARM_ERRATA_857271
815 This option enables the workaround for the 857271 Cortex-A12
819 config ARM_ERRATA_852421
823 This option enables the workaround for the 852421 Cortex-A17
828 config ARM_ERRATA_852423
833 - Cortex-A17 852423: Execution of a sequence of instructions might
835 any Cortex-A17 cores yet.
836 This is identical to Cortex-A12 erratum 852422. It is a separate
837 config option from the A12 erratum due to the way errata are checked
840 config ARM_ERRATA_857272
844 This option enables the workaround for the 857272 Cortex-A17 erratum.
846 This is identical to Cortex-A12 erratum 857271. It is a separate
847 config option from the A12 erratum due to the way errata are checked
856 config ISA
866 config ISA_DMA_API
869 config ARM_ERRATA_814220
878 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
885 config HAVE_SMP
888 This option should be selected by machines which have an SMP-
891 The only effect of this option is to make the SMP-related
894 config SMP
895 bool "Symmetric Multi-Processing"
905 If you say N here, the kernel will run on uni- and multiprocessor
911 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
912 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
913 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
917 config SMP_ON_UP
922 SMP kernels contain instructions which fail on non-SMP processors.
930 config CURRENT_POINTER_IN_TPIDRURO
934 config IRQSTACKS
939 config ARM_CPU_TOPOLOGY
948 config SCHED_MC
949 bool "Multi-core scheduler support"
952 Multi-core scheduler support improves the CPU scheduler's decision
953 making when dealing with multi-core CPU chips at a cost of slightly
956 config SCHED_SMT
964 config HAVE_ARM_SCU
969 config HAVE_ARM_ARCH_TIMER
976 config HAVE_ARM_TWD
981 config MCPM
982 bool "Multi-Cluster Power Management"
986 for (multi-)cluster based systems, such as big.LITTLE based
989 config MCPM_QUAD_CLUSTER
998 config BIG_LITTLE
1006 config BL_SWITCHER
1015 config BL_SWITCHER_DUMMY_IF
1033 config VMSPLIT_3G
1035 config VMSPLIT_3G_OPT
1038 config VMSPLIT_2G
1040 config VMSPLIT_1G
1044 config PAGE_OFFSET
1052 config KASAN_SHADOW_OFFSET
1061 config NR_CPUS
1062 int "Maximum number of CPUs (2-32)"
1070 debugging is enabled, which uses half of the per-CPU fixmap
1073 config HOTPLUG_CPU
1074 bool "Support for hot-pluggable CPUs"
1081 config ARM_PSCI
1087 implementing the PSCI specification for CPU-centric power
1092 config HZ_FIXED
1101 config HZ_100
1104 config HZ_200
1107 config HZ_250
1110 config HZ_300
1113 config HZ_500
1116 config HZ_1000
1121 config HZ
1131 config SCHED_HRTICK
1134 config THUMB2_KERNEL
1135 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1141 Thumb-2 mode.
1145 config ARM_PATCH_IDIV
1163 config AEABI
1180 config OABI_COMPAT
1201 config ARCH_SELECT_MEMORY_MODEL
1204 config ARCH_FLATMEM_ENABLE
1207 config ARCH_SPARSEMEM_ENABLE
1211 config HIGHMEM
1230 config HIGHPTE
1231 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1239 user-space 2nd level page tables to reside in high memory.
1241 config ARM_PAN
1242 bool "Enable privileged no-access"
1248 use-after-free bugs becoming an exploitable privilege escalation
1255 config CPU_SW_DOMAIN_PAN
1259 Enable use of CPU domains to implement privileged no-access.
1261 CPUs with low-vector mappings use a best-efforts implementation.
1265 config CPU_TTBR0_PAN
1269 Enable privileged no-access by disabling TTBR0 page table walks when
1272 config HW_PERF_EVENTS
1276 config ARM_MODULE_PLTS
1291 Disabling this is usually safe for small single-platform
1294 config ARCH_FORCE_MAX_ORDER
1309 config ALIGNMENT_TRAP
1315 address divisible by 4. On 32-bit ARM processors, these non-aligned
1318 correct operation of some network protocols. With an IP-only
1321 config UACCESS_WITH_MEMCPY
1327 cores where a 8-word STM instruction give significantly higher
1334 However, if the CPU data cache is using a write-allocate mode,
1337 config PARAVIRT
1344 config PARAVIRT_TIME_ACCOUNTING
1355 config XEN_DOM0
1359 config XEN
1373 config CC_HAVE_STACKPROTECTOR_TLS
1374 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1376 config STACKPROTECTOR_PER_TASK
1396 config USE_OF
1403 config ARCH_WANT_FLAT_DTB_INSTALL
1406 config ATAGS
1415 config DEPRECATED_PARAM_STRUCT
1423 # TEXT and BSS so we preserve their values in the config files.
1424 config ZBOOT_ROM_TEXT
1428 The physical address at which the ROM-able zImage is to be
1430 ROM-able zImage formats normally set this to a suitable
1435 config ZBOOT_ROM_BSS
1440 for the ROM-able zImage which must be available while the
1443 Platforms which normally make use of ROM-able zImage formats
1448 config ZBOOT_ROM
1456 config ARM_APPENDED_DTB
1465 systems with a bootloader that can't be upgraded to accommodate
1473 location into r2 of a bootloader provided DTB is always preferable
1476 config ARM_ATAG_DTB_COMPAT
1483 provided by the bootloader and can't always be stored in a static
1493 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1494 bool "Use bootloader kernel arguments if available"
1496 Uses the command-line options passed by the boot loader instead of
1500 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1501 bool "Extend with bootloader kernel arguments"
1503 The command-line arguments provided by the boot loader will be
1508 config CMDLINE
1514 architectures, you should supply some command-line options at build
1523 config CMDLINE_FROM_BOOTLOADER
1524 bool "Use bootloader kernel arguments if available"
1526 Uses the command-line options passed by the boot loader. If
1530 config CMDLINE_EXTEND
1531 bool "Extend bootloader kernel arguments"
1533 The command-line arguments provided by the boot loader will be
1536 config CMDLINE_FORCE
1542 command-line options your boot loader passes to the kernel.
1545 config XIP_KERNEL
1546 bool "Kernel Execute-In-Place from ROM"
1550 Execute-In-Place allows the kernel to run from non-volatile storage
1553 to RAM. Read-write sections, such as the data section and stack,
1567 config XIP_PHYS_ADDR
1576 config XIP_DEFLATED_DATA
1587 config ARCH_SUPPORTS_KEXEC
1590 config ATAGS_PROC
1598 config ARCH_SUPPORTS_CRASH_DUMP
1601 config ARCH_DEFAULT_CRASH_DUMP
1604 config AUTO_ZRELADDR
1610 will be determined at run-time, either by masking the current IP
1615 config EFI_STUB
1618 config EFI
1628 by UEFI firmware (such as non-volatile variables, realtime
1634 config DMI
1643 continue to boot on existing non-UEFI platforms.
1649 to be enabled much earlier than we do on ARM, which is non-trivial.
1665 config FPE_NWFPE
1672 your machine has an FPA or floating point co-processor podule.
1677 config FPE_NWFPE_XP
1681 Say Y to include 80-bit support in the kernel floating-point
1682 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1683 Note that gcc does not generate 80-bit operations by default,
1689 config FPE_FASTFPE
1696 It is very simple, and approximately 3-6 times faster than NWFPE.
1703 config VFP
1704 bool "VFP-format floating point maths"
1710 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1715 config VFPv3
1720 config NEON
1727 config KERNEL_MODE_NEON
1739 config ARCH_SUSPEND_POSSIBLE
1744 config ARM_CPU_SUSPEND
1748 config ARCH_HIBERNATION_POSSIBLE