Lines Matching +full:armv7 +full:- +full:timer +full:- +full:mem
1 # SPDX-License-Identifier: GPL-2.0
162 The ARM series is a line of low-power-consumption RISC chip designs
164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
165 manufactured, but legacy ARM-based PC hardware remains popular in
176 supported in LLD until version 14. The combined range is -/+ 256 MiB,
269 Patch phys-to-virt and virt-to-phys translation functions at
273 This can only be used with non-XIP MMU kernels where the base
319 bool "MMU-based Paged Memory Management Support"
322 Select if you want MMU-based virtualised addressing space
357 # This is sorted alphabetically by mach-* pathname. However, plat-*
359 # plat- suffix) or along side the corresponding mach-* source.
361 source "arch/arm/mach-actions/Kconfig"
363 source "arch/arm/mach-alpine/Kconfig"
365 source "arch/arm/mach-artpec/Kconfig"
367 source "arch/arm/mach-aspeed/Kconfig"
369 source "arch/arm/mach-at91/Kconfig"
371 source "arch/arm/mach-axxia/Kconfig"
373 source "arch/arm/mach-bcm/Kconfig"
375 source "arch/arm/mach-berlin/Kconfig"
377 source "arch/arm/mach-clps711x/Kconfig"
379 source "arch/arm/mach-davinci/Kconfig"
381 source "arch/arm/mach-digicolor/Kconfig"
383 source "arch/arm/mach-dove/Kconfig"
385 source "arch/arm/mach-ep93xx/Kconfig"
387 source "arch/arm/mach-exynos/Kconfig"
389 source "arch/arm/mach-footbridge/Kconfig"
391 source "arch/arm/mach-gemini/Kconfig"
393 source "arch/arm/mach-highbank/Kconfig"
395 source "arch/arm/mach-hisi/Kconfig"
397 source "arch/arm/mach-hpe/Kconfig"
399 source "arch/arm/mach-imx/Kconfig"
401 source "arch/arm/mach-ixp4xx/Kconfig"
403 source "arch/arm/mach-keystone/Kconfig"
405 source "arch/arm/mach-lpc32xx/Kconfig"
407 source "arch/arm/mach-mediatek/Kconfig"
409 source "arch/arm/mach-meson/Kconfig"
411 source "arch/arm/mach-milbeaut/Kconfig"
413 source "arch/arm/mach-mmp/Kconfig"
415 source "arch/arm/mach-mstar/Kconfig"
417 source "arch/arm/mach-mv78xx0/Kconfig"
419 source "arch/arm/mach-mvebu/Kconfig"
421 source "arch/arm/mach-mxs/Kconfig"
423 source "arch/arm/mach-nomadik/Kconfig"
425 source "arch/arm/mach-npcm/Kconfig"
427 source "arch/arm/mach-omap1/Kconfig"
429 source "arch/arm/mach-omap2/Kconfig"
431 source "arch/arm/mach-orion5x/Kconfig"
433 source "arch/arm/mach-pxa/Kconfig"
435 source "arch/arm/mach-qcom/Kconfig"
437 source "arch/arm/mach-realtek/Kconfig"
439 source "arch/arm/mach-rpc/Kconfig"
441 source "arch/arm/mach-rockchip/Kconfig"
443 source "arch/arm/mach-s3c/Kconfig"
445 source "arch/arm/mach-s5pv210/Kconfig"
447 source "arch/arm/mach-sa1100/Kconfig"
449 source "arch/arm/mach-shmobile/Kconfig"
451 source "arch/arm/mach-socfpga/Kconfig"
453 source "arch/arm/mach-spear/Kconfig"
455 source "arch/arm/mach-sti/Kconfig"
457 source "arch/arm/mach-stm32/Kconfig"
459 source "arch/arm/mach-sunxi/Kconfig"
461 source "arch/arm/mach-tegra/Kconfig"
463 source "arch/arm/mach-ux500/Kconfig"
465 source "arch/arm/mach-versatile/Kconfig"
467 source "arch/arm/mach-vt8500/Kconfig"
469 source "arch/arm/mach-zynq/Kconfig"
471 # ARMv7-M architecture
480 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
489 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
490 with a range of available cores like Cortex-M3/M4/M7.
523 source "arch/arm/Kconfig-nommu"
541 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
544 Executing a SWP instruction to read-only memory does not set bit 11
562 This option enables the workaround for the 430973 Cortex-A8
565 same virtual address, whether due to self-modifying code or virtual
566 to physical address re-mapping, Cortex-A8 does not recover from the
567 stale interworking branch prediction. This results in Cortex-A8
572 available in non-secure mode.
579 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
586 register may not be available in non-secure mode and thus is not
595 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
599 workaround disables the write-allocate mode for the L2 cache via the
601 may not be available in non-secure mode and thus is not available on
610 This option enables the workaround for the 742230 Cortex-A9
614 the diagnostic register of the Cortex-A9 which causes the DMB
617 register may not be available in non-secure mode and thus is not
626 This option enables the workaround for the 742231 Cortex-A9
628 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
633 register of the Cortex-A9 which reduces the linefill issuing
635 diagnostics register may not be available in non-secure mode and thus
644 This option enables the workaround for the 643719 Cortex-A9 (prior to
654 This option enables the workaround for the 720789 Cortex-A9 (prior to
667 This option enables the workaround for the 743622 Cortex-A9
669 optimisation in the Cortex-A9 Store Buffer may lead to data
671 register of the Cortex-A9 which disables the Store Buffer
675 may not be available in non-secure mode and thus is not available on a
683 This option enables the workaround for the 751472 Cortex-A9 (prior
689 not be available in non-secure mode and thus is not available on
697 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
700 can populate the micro-TLB with a stale entry which may be hit with
708 This option enables the workaround for the 754327 Cortex-A9 (prior to
716 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
721 hit-under-miss enabled). It sets the undocumented bit 31 in
723 register, thus disabling hit-under-miss without putting the
732 affecting Cortex-A9 MPCore with two or more processors (all
745 This option enables the workaround for the 764319 Cortex-A9 erratum.
756 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
763 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
766 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
776 This option enables the workaround for the 773022 Cortex-A15
786 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
788 - Cortex-A12 852422: Execution of a sequence of instructions might
790 any Cortex-A12 cores yet.
799 This option enables the workaround for the 821420 Cortex-A12
803 deadlock when the VMOV instructions are issued out-of-order.
809 This option enables the workaround for the 825619 Cortex-A12
812 and Device/Strongly-Ordered loads and stores might cause deadlock
818 This option enables the workaround for the 857271 Cortex-A12
826 This option enables the workaround for the 852421 Cortex-A17
836 - Cortex-A17 852423: Execution of a sequence of instructions might
838 any Cortex-A17 cores yet.
839 This is identical to Cortex-A12 erratum 852422. It is a separate
847 This option enables the workaround for the 857272 Cortex-A17 erratum.
849 This is identical to Cortex-A12 erratum 857271. It is a separate
881 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
891 This option should be selected by machines which have an SMP-
894 The only effect of this option is to make the SMP-related
898 bool "Symmetric Multi-Processing"
908 If you say N here, the kernel will run on uni- and multiprocessor
914 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
915 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
916 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
925 SMP kernels contain instructions which fail on non-SMP processors.
952 bool "Multi-core scheduler support"
955 Multi-core scheduler support improves the CPU scheduler's decision
956 making when dealing with multi-core CPU chips at a cost of slightly
973 bool "Architected timer support"
977 This option enables support for the ARM architected timer
982 This options enables support for the ARM timer and watchdog unit
985 bool "Multi-Cluster Power Management"
989 for (multi-)cluster based systems, such as big.LITTLE based
1065 int "Maximum number of CPUs (2-32)"
1073 debugging is enabled, which uses half of the per-CPU fixmap
1077 bool "Support for hot-pluggable CPUs"
1090 implementing the PSCI specification for CPU-centric power
1102 prompt "Timer frequency"
1138 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1144 Thumb-2 mode.
1234 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1242 user-space 2nd level page tables to reside in high memory.
1245 bool "Enable privileged no-access"
1251 use-after-free bugs becoming an exploitable privilege escalation
1262 Enable use of CPU domains to implement privileged no-access.
1264 CPUs with low-vector mappings use a best-efforts implementation.
1272 Enable privileged no-access by disabling TTBR0 page table walks when
1294 Disabling this is usually safe for small single-platform
1318 address divisible by 4. On 32-bit ARM processors, these non-aligned
1321 correct operation of some network protocols. With an IP-only
1325 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1330 cores where a 8-word STM instruction give significantly higher
1337 However, if the CPU data cache is using a write-allocate mode,
1377 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1431 The physical address at which the ROM-able zImage is to be
1433 ROM-able zImage formats normally set this to a suitable
1443 for the ROM-able zImage which must be available while the
1446 Platforms which normally make use of ROM-able zImage formats
1499 Uses the command-line options passed by the boot loader instead of
1506 The command-line arguments provided by the boot loader will be
1517 architectures, you should supply some command-line options at build
1519 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1529 Uses the command-line options passed by the boot loader. If
1536 The command-line arguments provided by the boot loader will be
1545 command-line options your boot loader passes to the kernel.
1549 bool "Kernel Execute-In-Place from ROM"
1553 Execute-In-Place allows the kernel to run from non-volatile storage
1556 to RAM. Read-write sections, such as the data section and stack,
1613 will be determined at run-time, either by masking the current IP
1631 by UEFI firmware (such as non-volatile variables, realtime
1646 continue to boot on existing non-UEFI platforms.
1652 to be enabled much earlier than we do on ARM, which is non-trivial.
1675 your machine has an FPA or floating point co-processor podule.
1684 Say Y to include 80-bit support in the kernel floating-point
1685 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1686 Note that gcc does not generate 80-bit operations by default,
1699 It is very simple, and approximately 3-6 times faster than NWFPE.
1707 bool "VFP-format floating point maths"
1713 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1727 Say Y to include support code for NEON, the ARMv7 Advanced SIMD